CN106406974A - High-performance timer implementation method used for virtual machine, and virtual machine - Google Patents
High-performance timer implementation method used for virtual machine, and virtual machine Download PDFInfo
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Abstract
The invention provides a high-performance timer implementation method used for a virtual machine, and a virtual machine. The method comprises the following steps of: a partitioning GuestOS (Operating System) generates a timing requirement and writes a timing value to a high-accuracy timer register0x380; a partitioning CPU (Central Processing Unit) captures an operation for writing a privileged instruction into the 0x380 register, and generates VM_Exit to a Hypervisor to be processed; the embedded Hypervisor obtains and add the offset and writing value of the register into a timer configuration message through the CPU, and the timer configuration message is sent to a high-speed communication queue; and a high-accuracy timer module obtains the timer configuration message from the high-speed communication queue, and writes the timer configuration message into a hardware core register. Through the implementation of the method, in a process that the timer configuration message is generated and written into the timer, hardware carries out instruction decoding and directly transfers the offset address and the writing value of the register into the Hypervisor to be processed, and a time bottleneck generated by software instruction decoding is essentially eliminated.
Description
Technical field
The present invention relates to virtual machine high-performance timing field, more particularly, to a kind of high-performance for virtual machine is calmly
When device implementation method, virtual machine.
Background technology
At present in the application in virtualization field, virtual machine performance is a key index of everybody common concern,
Can one virtual machine have with physical machine identical performance is that virtualization field is relatively difficult to solve for a long time
A difficult problem, and embedded type virtual has the characteristic of high real-time requires due to its carrying business, therefore to void
Property indices after planization require more harsh, and affect the most key one in virtual machine operating index
Individual is exactly virtual machine precision of timer problem.
Existing embedded type virtual high-resolution timer handling process is：GuestOS configuration skew is 0x380
Timer Initial Count register timing value；Hardware is write 0x380 register generation VM_Exit and is arrived
Hypervisor writes real hardware register after carrying out instruction decoding；System is returned to by Hypervisor
GuestOS continues to run with；High-resolution timer is timed to hardware and produces and interrupts occurring VM_Exit to arrive
Hypervisor has no progeny in processing and for this interruption to be converted to the IDT interrupt processing that virtual interrupt injects GuestOS
Flow process.
The key factor that the method has impact embedded type virtual machine high-resolution timer performance has two aspects：
First is to produce VM_Exit a to Hypervisor to 0x380 register write timing value every time to process product
Raw instruction decoding operation forming properties bottleneck；Second is that high-resolution timer can send middle stopping pregnancy when being timed to
Raw VM_Exit to Hypervisor reinjects interruption after processing and arrives GuestOS IDT interrupt handling program,
This process increased VM_Exit to Hypervisor switching and hardware Interrupt Process expense, for virtual machine
Precision of timer has larger performance impact.
Therefore, how to provide a kind of high-performance timer implementation method possessing higher precision of timer, be this
Skilled person's technical problem urgently to be resolved hurrily.
Content of the invention
The invention provides a kind of high-performance timer implementation method for virtual machine, virtual machine, to solve
The problem of virtual machine precision of timer difference.
The invention provides a kind of high-performance timer implementation method for virtual machine, it includes：Subregion
GuestOS produces timing demands, to high-resolution timer register 0x380 write timing value；Subregion CPU
0x380 register privileged instruction operation is write in capture, produces VM_Exit to Hypervisor and processes；Embedded
Formula Hypervisor writes register offset by CPU acquisition and write value is added to timer configuration message, sends out
Deliver to high speed communication queue；High-resolution timer module obtains timer configuration message from high speed communication queue,
And write hardware core register.
Further, when there is multiple subregion, also include：Embedded Hypervisor will initiate register
The core id that the subregion VCPU of write operation is located, corresponding hardware Posted Interrupt descriptor address are whole
Close, and add to timer configuration message.
Further, after sending timer configuration message to high speed communication queue, also include:Notify high
Precision timer module is write register manipulation and is completed；High-resolution timer module upon receipt of a notification, from a high speed
Timer configuration message is obtained in communication queue.
Further, timer configuration message write hardware core register is included by high-resolution timer module：
High-resolution timer module parses timer configuration message, obtains and writes register offset and write value, and it is fixed to determine
When device skew and timing value, write hardware Core timer.
Further, when there is multiple subregion, also include：High-resolution timer module parsing timer is joined
Put message, obtain and write register offset and write value, initiate what the subregion VCPU of register writes was located
Core id, corresponding hardware Posted Interrupt descriptor address, with timer offsetting and timing value as VCPU
The core id being located, hardware Posted Interrupt descriptor address store virtual machine timer model；Look for
The minimum timing value write hardware Core timer going out.
Further, also include：Judge whether hardware Core timer is in non-timed state；If hardware
Core timer is in non-timed state, then high-resolution timer module searches virtual machine timer data model,
The minimum timing found out value is write hardware Core timer；If hardware Core timer is in timing shape
State, does not carry out the write operation of hardware Core timer.
Further, also include：The core of deployment partitioned virtual machine is closed high-precision fixed by Hypervisor
When device.
Further, also include：Select a core, in this operation of core embedded Hypervisor high accuracy
Timer module.
Further, also include：In embedded Hypervisor each partitioned virtual machine of software layer building and height
High speed communication passage between precision timer module.
Further, also include：Hardware Core timer, when timing reaches, sends interrupt notification extremely high-precision
Degree timer module, high-resolution timer module writes high-resolution timer interrupt identification to subregion PI descriptor,
Send PI physical discontinuity to subregion core.
Further, when there is multiple subregion, also include：High-resolution timer module is from virtual machine timing
Core id and the virtual machine PI descriptor address information of the VCPU of the virtual machine being timed to is obtained in device model,
Mark is interrupted to corresponding PI descriptor write high-resolution timer according to the virtual machine PI descriptor address obtaining
Will, the core id according to the VCPU obtaining sends PI physical discontinuity to corresponding core.
Further, also include：High-resolution timer module is deleted complete from virtual machine timer model
Become the subregion timer data of Interruption injection, and from the virtual machine timer data model read next one
Little timing value, by the virtual machine reading next one minimum timing value write hardware Core timer.
The invention provides a kind of virtual machine, it includes：Subregion GuestOS, for producing timing demands,
To high-resolution timer register 0x380 write timing value；Subregion CPU, writes 0x380 register for capture
Privileged instruction operation, produces VM_Exit to Hypervisor and processes；Embedded Hypervisor, for leading to
Cross CPU and obtain and write register offset and write value is added to timer configuration message, send to high speed communication team
Row；High-resolution timer module, for obtaining timer configuration message from high speed communication queue, and writes
Hardware core register.
Further, when there is multiple subregion, embedded Hypervisor is additionally operable to initiate register write
The core id that the subregion VCPU of operation is located, corresponding hardware Posted Interrupt descriptor address are integrated,
And add to timer configuration message.
Further, embedded Hypervisor by timer configuration message send to high speed communication queue it
Afterwards, it is additionally operable to notify high-resolution timer module to write register manipulation and complete；High-resolution timer module is also used
In upon receipt of a notification, obtain timer configuration message from high speed communication queue.
Further, high-resolution timer module is used for parsing timer configuration message, and it is inclined that register is write in acquisition
Move and write value, determine timer offsetting and timing value, write hardware Core timer.
Further, when there is multiple subregion, high-resolution timer module is additionally operable to parse timer configuration
Message, obtains and writes register offset and write value, initiates the core that the subregion VCPU of register writes is located
Id, corresponding hardware Posted Interrupt descriptor address, with timer offsetting and timing value for VCPU institute
Core id, hardware Posted Interrupt descriptor address store virtual machine timer model；Find out
Minimum timing value write hardware Core timer.
Further, high-resolution timer module is additionally operable to judge whether hardware Core timer is in the non-timed
State；If hardware Core timer is in non-timed state, search virtual machine timer data model,
The minimum timing found out value is write hardware Core timer；If hardware Core timer is in timing shape
State, does not carry out the write operation of hardware Core timer.
Further, the core of deployment partitioned virtual machine is additionally operable to close high precision timing by Hypervisor
Device.
Further, embedded Hypervisor is additionally operable to select a core, embedded in this operation of core
Hypervisor high-resolution timer module.
Further, embedded Hypervisor be additionally operable to each partitioned virtual machine of software layer building with high-precision
High speed communication passage between degree timer module.
Further, hardware Core timer is additionally operable to hardware Core timer when timing reaches, and sends
Interrupt notification is to high accuracy timer module；High-resolution timer module is additionally operable to write to subregion PI descriptor
High-resolution timer interrupt identification, sends PI physical discontinuity to subregion core.
Further, when there is multiple subregion, high-resolution timer module is additionally operable to from virtual machine timer
Core id and the virtual machine PI descriptor address information of the VCPU of the virtual machine being timed to is obtained in model,
Mark is interrupted to corresponding PI descriptor write high-resolution timer according to the virtual machine PI descriptor address obtaining
Will, the core id according to the VCPU obtaining sends PI physical discontinuity to corresponding core.
Further, high-resolution timer module is additionally operable to delete from virtual machine timer model and has completed
The subregion timer data of Interruption injection, and next minimum from virtual machine timer data model read
Timing value, by the virtual machine reading next one minimum timing value write hardware Core timer.
Beneficial effects of the present invention：
The invention provides a kind of new high-performance timer implementation method, generating timer configuration message simultaneously
Write timer during it is not necessary to as prior art hardware write 0x380 register produce VM_Exit
Carry out writing real hardware register after instruction decoding to Hypervisor, so, GuestOS writes 0x380
Register does not need software to carry out instruction decoding, and hardware can carry out instruction decoding and directly in VM_Exit event
Middle register offset address and write value are passed to Hypervisor process, inherently eliminate software and refer to
The time bottleneck that order decoding produces；Further, after timer arrival, high-resolution timer module first to
Posted Interrupt descriptor writes high-resolution timer interrupt identification, then to corresponding core id
Send the internuclear interruption of Posted Interrupt, Intel Posted Interrupt hardware virtualization mechanism can be automatically
According to the above-mentioned interruption injection configuring paired different subregions virtual machine high-resolution timer, will not during this
Produce any VM_Exit and intervene interrupt processing also without Hypervisor, therefore performance can reach and thing
The consistent level of reason machine.
Brief description
The structural representation of the virtual machine that Fig. 1 provides for first embodiment of the invention；
The flow chart of the high-performance timer implementation method that Fig. 2 provides for second embodiment of the invention；
The flow chart of the high-performance timer implementation method that Fig. 3 provides for third embodiment of the invention.
Specific embodiment
Now combined by specific embodiment and by way of accompanying drawing, the present invention is made with further annotation explanation.
First embodiment：
The structural representation of the virtual machine that Fig. 1 provides for first embodiment of the invention, as shown in Figure 1, at this
In embodiment, the virtual machine 1 that the present invention provides includes：
Subregion GuestOS11, for producing timing demands, it is fixed to write to high-resolution timer register 0x380
Duration；
Subregion CPU12, writes 0x380 register privileged instruction operation for capture, produces VM_Exit and arrives
Hypervisor process；
Embedded Hypervisor13, writes register offset and write value is added to fixed for obtaining by CPU
When device configuration message, send to high speed communication queue；
High-resolution timer module 14, for obtaining timer configuration message from high speed communication queue, and writes
Enter hardware core register 15；
Hardware core register 15 is used for executing timer.
In certain embodiments, the embedded Hypervisor13 when there is multiple subregion, in above-described embodiment
It is additionally operable to core id, the corresponding hardware Posted that the subregion VCPU initiating register writes is located
Interrupt descriptor address is integrated, and adds to timer configuration message.
In certain embodiments, the embedded Hypervisor13 in above-described embodiment is by timer configuration report
Literary composition sends to after high speed communication queue, is additionally operable to notify high-resolution timer module to write register manipulation and complete；
High-resolution timer module is additionally operable to upon receipt of a notification, obtains timer configuration report from high speed communication queue
Literary composition.
In certain embodiments, the high-resolution timer module 14 in above-described embodiment is used for parsing timer and joins
Put message, obtain and write register offset and write value, determine timer offsetting and timing value, write hardware Core
Timer.
In certain embodiments, the high-resolution timer module when there is multiple subregion, in above-described embodiment
14 are additionally operable to parse timer configuration message, obtain and write register offset and write value, initiate register write behaviour
The core id at subregion VCPU place of work, corresponding hardware Posted Interrupt descriptor address, with fixed
When device skew and timing value be located for VCPU core id, hardware Posted Interrupt descriptor address
Store virtual machine timer model；The minimum timing value write hardware Core timer 15 found out.
In certain embodiments, the high-resolution timer module 14 in above-described embodiment is additionally operable to judge hardware
Whether Core timer 15 is in non-timed state；If hardware Core timer is in non-timed state,
Then search virtual machine timer data model, the minimum timing found out value is write hardware Core timer；As
Fruit hardware Core timer is in definition status, does not carry out the write operation of hardware Core timer.
In certain embodiments, the core of the deployment partitioned virtual machine in above-described embodiment is additionally operable to pass through
Hypervisor13 closes high-resolution timer.
In certain embodiments, the embedded Hypervisor13 in above-described embodiment is additionally operable to select a core,
In this operation of core embedded Hypervisor high-resolution timer module 14.
In certain embodiments, the embedded Hypervisor13 in above-described embodiment is additionally operable in software layer structure
Build the high speed communication passage between each partitioned virtual machine and high-resolution timer module 14.
In certain embodiments, the hardware Core timer 15 in above-described embodiment is additionally operable to hardware Core
Timer, when timing reaches, sends interrupt notification to high accuracy timer module 14；High-resolution timer mould
Block 14 is additionally operable to write high-resolution timer interrupt identification to subregion PI descriptor, sends to subregion core
PI physically interrupts.
In certain embodiments, the high-resolution timer module when there is multiple subregion, in above-described embodiment
14 are additionally operable to obtain the core id of VCPU and the void of the virtual machine being timed to from virtual machine timer model
Plan machine PI descriptor address information, according to the virtual machine PI descriptor address obtaining to corresponding PI descriptor
Write high-resolution timer interrupt identification, sends to corresponding core according to the core id of the VCPU obtaining
PI physically interrupts.
In certain embodiments, the high-resolution timer module 14 in above-described embodiment is additionally operable to determine from virtual machine
When device model in delete the subregion timer data that completion timing interrupts injection, and from virtual machine timer
Data model reads next minimum timing value, by the virtual machine reading next one minimum timing value write hardware
Core timer.
Second embodiment：
The flow chart of the high-performance timer implementation method that Fig. 2 provides for second embodiment of the invention, by Fig. 2
Understand, in the present embodiment, the high-performance timer implementation method that the present invention provides comprises the following steps：
S201：Subregion GuestOS produces timing demands, and it is fixed to write to high-resolution timer register 0x380
Duration；
S202：0x380 register privileged instruction operation is write in subregion CPU capture, produces VM_Exit and arrives
Hypervisor process；
S203：Embedded Hypervisor writes register offset by CPU acquisition and write value is added to calmly
When device configuration message, send to high speed communication queue；
S204：High-resolution timer module obtains timer configuration message from high speed communication queue, and writes
Hardware core register.
In certain embodiments, when there is multiple subregion, the method in above-described embodiment also includes：Embedded
Formula Hypervisor will initiate the core id at the subregion VCPU place of register writes, corresponding hardware
Posted Interrupt descriptor address is integrated, and adds to timer configuration message.
In certain embodiments, the method in above-described embodiment timer configuration message is sent logical to high speed
After news queue, also include:Notify high-resolution timer module to write register manipulation to complete；High-resolution timer
Module upon receipt of a notification, obtains timer configuration message from high speed communication queue.
In certain embodiments, timer configuration message is write by the high-resolution timer module in above-described embodiment
Enter hardware core register to include：High-resolution timer module parses timer configuration message, obtains to write and deposits
Device skew and write value, determine timer offsetting and timing value, write hardware Core timer.
In certain embodiments, when there is multiple subregion, the method in above-described embodiment also includes：High-precision
Degree timer module parsing timer configuration message, obtains and writes register offset and write value, initiates register
The core id at subregion VCPU place of write operation, corresponding hardware Posted Interrupt descriptor address,
The core id that is located for VCPU with timer offsetting and timing value, hardware Posted Interrupt descriptor
Address stores virtual machine timer model；The minimum timing value write hardware Core timer found out.
In certain embodiments, the method in above-described embodiment also includes：Whether judge hardware Core timer
It is in non-timed state；If hardware Core timer is in non-timed state, high-resolution timer module
Search virtual machine timer data model, the minimum timing found out value is write hardware Core timer；If
Hardware Core timer is in definition status, does not carry out the write operation of hardware Core timer.
In certain embodiments, the method in above-described embodiment also includes：The core of deployment partitioned virtual machine leads to
Cross Hypervisor and close high-resolution timer.
In certain embodiments, the method in above-described embodiment also includes：Select a core, in this fortune of core
The embedded Hypervisor high-resolution timer module of row.
In certain embodiments, the method in above-described embodiment also includes：In embedded Hypervisor software
High speed communication passage between each partitioned virtual machine of layer building and high-resolution timer module.
In certain embodiments, the method in above-described embodiment also includes：Hardware Core timer is being timed to
When reaching, send interrupt notification to high accuracy timer module, high-resolution timer module is to subregion PI descriptor
Write high-resolution timer interrupt identification, sends PI physical discontinuity to subregion core.
In certain embodiments, when there is multiple subregion, the method in above-described embodiment also includes：High-precision
Degree timer module obtain from virtual machine timer model the virtual machine being timed to the core id of VCPU and
Virtual machine PI descriptor address information, the virtual machine PI descriptor address according to obtaining describes to corresponding PI
Symbol write high-resolution timer interrupt identification, sends out to corresponding core according to the core id of the VCPU obtaining
PI is sent to physically interrupt.
In certain embodiments, the method in above-described embodiment also includes：High-resolution timer module is from virtual
The subregion timer data that completion timing interrupts injection is deleted in machine timer model, and fixed from virtual machine
When device data model read next minimum timing value, by the virtual machine reading next one minimum timing value write
Hardware Core timer.
In conjunction with concrete application scene, the present invention is done with further annotation explanation.
3rd embodiment：
The flow chart of the high-performance timer implementation method that Fig. 3 provides for third embodiment of the invention, by Fig. 3
Understand, in the present embodiment, the high-performance timer implementation method that the present invention provides comprises the following steps：
S301：Virtual machine initializes.
Initialization comprises the following steps：
The core of deployment partitioned virtual machine closes high-resolution timer by Hypervisor, and preventing need not
The external interrupt impact wanted；
It is separately separated out a core and runs embedded Hypervisor high-resolution timer module, starting should
Core high-resolution timer hardware capability, this module provides clock source for different subregions high-resolution timer；
Between embedded Hypervisor each partitioned virtual machine of software layer building and high-resolution timer module
High speed communication passage, different subregions 0x380 register timing value writing to high-resolution timer module is provided
Enter mechanism；
Embedded Hypervisor configures partitioned virtual machine hardware APIC Register Virtualization function,
Purpose is to allow GuestOS write 0x380 register not need software to carry out instruction decoding, and hardware can be instructed
Decoding simultaneously directly passes to register offset address and write value at Hypervisor in VM_Exit event
Reason, inherently eliminates the time bottleneck that software instruction decoding produces；
S302：Subregion generates timer configuration message.
Embedded Hypervisor capture GuestOS processes operation to 0x380 register write and does not directly write
Enter the hardware register of current core, but by high speed communication passage by timing value, current core id and
Corresponding Posted Interrupt descriptor address writes high-resolution timer module.
Specifically, this step includes：
High-precision GuestOS produces timing demands to high-resolution timer register 0x380 write timing value；
CPU hardware capture is write 0x380 register privileged instruction operation and is produced VM_Exit to Hypervisor
Process；
Embedded Hypervisor is obtained by CPU hardware and writes register offset and write value and will initiate to deposit
Core id and corresponding hardware Posted Interrupt descriptor ground that the subregion VCPU of device write operation is located
After location is integrated, high speed communication queue is transmitted by timer configuration message；
Embedded Hypervisor transmission event notice high-resolution timer module is write register manipulation and is completed；
High-resolution timer module obtains timer configuration message from high speed communication queue.
S303：Timing value is write hardware core timer.
High-resolution timer module is derived from the high accuracy of each partitioned virtual machine configuration from high speed communication channel reception
Timer message, update internal data model, and carry out calculate with analysis finally complete high-resolution timer mould
The configuration of block place core hardware high-resolution timer.
Specifically, this step includes：
High-resolution timer module receives Hypervisor message event passage and notifies it was demonstrated that now there being void
Plan machine subregion writes high-resolution timer timing message, prepares to read timing message content from communication queue；
High-resolution timer module parses message event acquisition of information high speed communication queue number, and reads from queue
Take the high-resolution timer timing message of virtual machine partitions write；
The virtual machine configuration timer message that high-resolution timer module analysis read, with timer offsetting and calmly
Duration is to index the coreid of the VCPU operation in message, hardware Posted Interrupt descriptor address
Store virtual machine timer data model；
If Current hardware Core timer is in non-timed state, high-resolution timer module searches virtual machine
Timer data model, the minimum timing found out value is write hardware Core timer；If Current hardware
Core timer is in definition status, does not carry out the write operation of hardware Core timer.
S304：The timing of hardware core timer reaches, and produces and interrupts.
The core hardware high-resolution timer that high-resolution timer module is located triggers high precision timing after being timed to
Device module is run, and being searched by internal data model needs partitioned virtual machine Posted of Timing Processing
Interrupt descriptor address and core id, find after data first to Posted Interrupt descriptor
Write high-resolution timer interrupt identification, then sends Posted Interrupt to corresponding core id internuclear
Interrupt, Intel Posted Interrupt hardware virtualization mechanism can configure different points in pairs automatically according to above-mentioned
Area's virtual machine high-resolution timer interruption injection, will not produce during this any VM_Exit also without
Hypervisor intervenes interrupt processing, and therefore performance can reach the level consistent with physical machine
Specifically, this step includes：
Hardware Core timer is timed to sends out interrupt notification high-resolution timer module；
High-resolution timer module obtains, from virtual machine timer data model, the associated virtual machine being timed to
Coreid and PI descriptor address information；
Write high-precision to corresponding PI descriptor according to the virtual machine PI descriptor address obtaining from data model
Degree timer interruption mark；
Coreid according to the VCPU obtaining from data model sends PI physical discontinuity to this core；
After software Hypervisor completes this step, hardware can read high-precision fixed automatically from PI descriptor
When device interrupt identification automatically generate high-resolution timer and interrupt and jump to GuestOS interrupt handling program holding
OK, whole process will not produce VM_Exit, and therefore performance is completely the same with physical machine.
S305：Write next timing information in hardware core timer.
High-resolution timer module deletes dividing of completion timing interruption injection from virtual machine timer model
Area's timer data, and from virtual machine timer data model read next one minimum timing value；High-precision fixed
When device module by read virtual machine the next one minimum timing value write hardware Core high-resolution timer.
In summary, by the enforcement of the present invention, at least there is following beneficial effect：
Generating timer configuration message and during writing timer it is not necessary to hard as prior art
Part is write write real hardware after 0x380 register generation VM_Exit to Hypervisor carries out instruction decoding and is posted
Storage, so, GuestOS writes 0x380 register does not need software to carry out instruction decoding, and hardware can be carried out
Register offset address and write value are simultaneously directly passed in VM_Exit event by instruction decoding
Hypervisor process, inherently eliminates the time bottleneck that software instruction decoding produces；
Further, after timer arrival, high-resolution timer module is first to Posted Interrupt
Descriptor writes high-resolution timer interrupt identification, then sends Posted to corresponding core id
The internuclear interruption of Interrupt, Intel Posted Interrupt hardware virtualization mechanism can be automatically according to above-mentioned configuration
Complete the interruption injection to different subregions virtual machine high-resolution timer, will not produce any during this
VM_Exit also without Hypervisor intervene interrupt processing, therefore performance can reach consistent with physical machine
Level；
Further, the core of deployment partitioned virtual machine closes high-resolution timer by Hypervisor, prevents
Only produce unnecessary external interrupt impact；
Further, it is separately separated out a core and run embedded Hypervisor high-resolution timer module,
Start this core high-resolution timer hardware capability, this module provides clock for different subregions high-resolution timer
Source；
Further, in embedded Hypervisor each partitioned virtual machine of software layer building and high precision timing
High speed communication passage between device module, provides different subregions 0x380 register timing value to high precision timing
The writing mechanism of device module.
The above is only the specific embodiment of the present invention, not the present invention done with any pro forma restriction,
Every technical spirit according to the present invention embodiment of above is made arbitrarily simply modification, equivalent variations,
In conjunction with or modify, all still fall within the protection domain of technical solution of the present invention.
Claims (24)
1. a kind of high-performance timer implementation method for virtual machine is it is characterised in that include：
Subregion GuestOS produces timing demands, to high-resolution timer register 0x380 write timing value；
0x380 register privileged instruction operation is write in subregion CPU capture, produces VM_Exit to Hypervisor
Process；
Embedded Hypervisor writes register offset by CPU acquisition and write value is added to timer configuration
Message, sends to high speed communication queue；
High-resolution timer module obtains described timer configuration message from described high speed communication queue, and writes
Enter hardware core register.
2. high-performance timer implementation method as claimed in claim 1 is it is characterised in that ought exist many
During individual subregion, also include：The subregion VCPU initiating register writes is located by embedded Hypervisor
Core id, corresponding hardware Posted Interrupt descriptor address integrates, and adds to timer configuration report
Literary composition.
3. high-performance timer implementation method as claimed in claim 1 is it is characterised in that inciting somebody to action timing
Device configuration message sends to after high speed communication queue, also includes:Notify described high-resolution timer module to write to post
Storage operation completes；Described high-resolution timer module upon receipt of a notification, from described high speed communication queue
Obtain described timer configuration message.
4. high-performance timer implementation method as claimed in claim 1 is it is characterised in that described high-precision
Described timer configuration message write hardware core register is included by degree timer module：Described high-precision fixed
When device module parse described timer configuration message, write register offset and write value described in acquisition, it is fixed to determine
When device skew and timing value, write described hardware Core timer.
5. high-performance timer implementation method as claimed in claim 4 is it is characterised in that ought exist many
During individual subregion, also include：Described high-resolution timer module parses described timer configuration message, obtains institute
State and write register offset and write value, initiate core id that the subregion VCPU of register writes is located, right
Answer hardware Posted Interrupt descriptor address, be located for described VCPU with timer offsetting and timing value
Core id, hardware Posted Interrupt descriptor address store virtual machine timer model；Find out
Minimum timing value writes described hardware Core timer.
6. high-performance timer implementation method as claimed in claim 5 is it is characterised in that also include：
Judge whether described hardware Core timer is in non-timed state；If at described hardware Core timer
In non-timed state, then described high-resolution timer module searches virtual machine timer data model, will find out
Minimum timing value write hardware Core timer；If described hardware Core timer is in definition status,
Do not carry out the write operation of described hardware Core timer.
7. high-performance timer implementation method as claimed in claim 1 is it is characterised in that also include：
The core of deployment partitioned virtual machine closes high-resolution timer by Hypervisor.
8. high-performance timer implementation method as claimed in claim 1 is it is characterised in that also include：
Select a core, in this operation of core embedded Hypervisor high-resolution timer module.
9. high-performance timer implementation method as claimed in claim 1 is it is characterised in that also include：
Height between embedded Hypervisor each partitioned virtual machine of software layer building and high-resolution timer module
Fast communication channel.
10. the high-performance timer implementation method as described in any one of claim 1 to 9 it is characterised in that
Also include：Described hardware Core timer, when timing reaches, sends interrupt notification to described high precision timing
Device module, described high-resolution timer module writes high-resolution timer interrupt identification to subregion PI descriptor,
Send PI physical discontinuity to subregion core.
11. high-performance timer implementation methods as claimed in claim 10 exist it is characterised in that working as
During multiple subregion, also include：Described high-resolution timer module obtains timing from virtual machine timer model
The core id of the VCPU of the virtual machine arriving and virtual machine PI descriptor address information, virtual according to obtain
Machine PI descriptor address writes high-resolution timer interrupt identification to corresponding PI descriptor, according to obtain
The core id of VCPU sends PI physical discontinuity to corresponding core.
12. high-performance timer implementation methods as claimed in claim 11 are it is characterised in that also include：
Described high-resolution timer module deletes completion timing interruption injection from described virtual machine timer model
Subregion timer data, and from virtual machine timer data model read the next one minimum timing value, will read
The virtual machine next one minimum timing value taking writes described hardware Core timer.
A kind of 13. virtual machines are it is characterised in that include：
Subregion GuestOS, for producing timing demands, to high-resolution timer register 0x380 write timing
Value；
Subregion CPU, writes 0x380 register privileged instruction operation for capture, produces VM_Exit and arrives
Hypervisor process；
Embedded Hypervisor, writes register offset and write value is added to timing for obtaining by CPU
Device configuration message, sends to high speed communication queue；
High-resolution timer module, for obtaining described timer configuration message from described high speed communication queue,
And write hardware core register.
14. virtual machines as claimed in claim 13 it is characterised in that when there is multiple subregion, institute
State embedded Hypervisor be additionally operable to by initiate register writes subregion VCPU be located core id,
Corresponding hardware Posted Interrupt descriptor address is integrated, and adds to timer configuration message.
15. virtual machines as claimed in claim 13 are it is characterised in that described embedded Hypervisor
After sending timer configuration message to high speed communication queue, it is additionally operable to notify described high-resolution timer
Module is write register manipulation and is completed；Described high-resolution timer module is additionally operable to upon receipt of a notification, from described
Described timer configuration message is obtained in high speed communication queue.
16. virtual machines as claimed in claim 13 are it is characterised in that described high-resolution timer module
For parsing described timer configuration message, write register offset and write value described in acquisition, determine timer
Skew and timing value, write described hardware Core timer.
17. virtual machines as claimed in claim 16 it is characterised in that when there is multiple subregion, institute
State high-resolution timer module to be additionally operable to parse described timer configuration message, described in acquisition, write register offset
With write value, the core id at the subregion VCPU place initiating register writes, corresponding hardware Posted
Interrupt descriptor address, is the core id, hard that described VCPU is located with timer offsetting and timing value
Part Posted Interrupt descriptor address stores virtual machine timer model；The minimum timing value found out is write
Enter described hardware Core timer.
18. virtual machines as claimed in claim 17 are it is characterised in that described high-resolution timer module
It is additionally operable to judge whether described hardware Core timer is in non-timed state；If described hardware Core is fixed
When device be in non-timed state, then search virtual machine timer data model, the minimum timing found out value is write
Enter hardware Core timer；If described hardware Core timer is in definition status, do not carry out described hard
The write operation of part Core timer.
19. virtual machines as claimed in claim 13 are it is characterised in that dispose the core of partitioned virtual machine
It is additionally operable to close high-resolution timer by Hypervisor.
20. virtual machines as claimed in claim 13 are it is characterised in that described embedded Hypervisor
It is additionally operable to select a core, in this operation of core embedded Hypervisor high-resolution timer module.
21. virtual machines as claimed in claim 13 are it is characterised in that described embedded Hypervisor
The high speed communication being additionally operable between each partitioned virtual machine of software layer building and high-resolution timer module leads to
Road.
22. virtual machines as described in any one of claim 13 to 21 are it is characterised in that described hardware
Core timer is additionally operable to described hardware Core timer when timing reaches, and sends interrupt notification extremely described
High-resolution timer module；Described high-resolution timer module is additionally operable to write high accuracy to subregion PI descriptor
Timer interruption mark, sends PI physical discontinuity to subregion core.
23. virtual machines as claimed in claim 22 it is characterised in that when there is multiple subregion, institute
State high-resolution timer module to be additionally operable to obtain, from virtual machine timer model, the virtual machine being timed to
The core id of VCPU and virtual machine PI descriptor address information, according to the virtual machine PI descriptor ground obtaining
Location writes high-resolution timer interrupt identification to corresponding PI descriptor, according to the core id of the VCPU obtaining
Send PI physical discontinuity to corresponding core.
24. virtual machines as claimed in claim 23 are it is characterised in that described high-resolution timer module
It is additionally operable to delete the subregion timer number that completion timing interrupts injection from described virtual machine timer model
According to, and from virtual machine timer data model read the next one minimum timing value, by read virtual machine next
Individual minimum timing value writes described hardware Core timer.
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| CN201510458635.0A CN106406974B (en) | 2015-07-30 | 2015-07-30 | High-performance timer implementation method for virtual machine and virtual machine |
| PCT/CN2015/089282 WO2016131247A1 (en) | 2015-07-30 | 2015-09-09 | Method for realizing high-performance timer using virtual machine and virtual machine |
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| CN201510458635.0A CN106406974B (en) | 2015-07-30 | 2015-07-30 | High-performance timer implementation method for virtual machine and virtual machine |
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| CN112817701A (en) * | 2021-02-25 | 2021-05-18 | 北京字节跳动网络技术有限公司 | Timer processing method and device, electronic equipment and computer readable medium |
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Also Published As
| Publication number | Publication date |
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| WO2016131247A1 (en) | 2016-08-25 |
| CN106406974B (en) | 2020-07-17 |
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