CN106406972A - Program compiling method and compiler - Google Patents
Program compiling method and compiler Download PDFInfo
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- CN106406972A CN106406972A CN201610974546.6A CN201610974546A CN106406972A CN 106406972 A CN106406972 A CN 106406972A CN 201610974546 A CN201610974546 A CN 201610974546A CN 106406972 A CN106406972 A CN 106406972A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/42—Syntactic analysis
- G06F8/427—Parsing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/441—Register allocation; Assignment of physical memory space to logical memory space
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/443—Optimisation
- G06F8/4434—Reducing the memory space required by the program code
Abstract
The invention relates to a program compiling method and a compiler. The method comprises the following steps: reading a program to be compiled, and recording the base address and offset address of each memory access command; dividing the memory access commands with same base address into a large class; taking the memory addresses of commands with minimum offset address in each large class as new base addresses of all commands in the large class; calculating whether the new base addresses in the large class can enable the total code length of the memory access commands of the large class to become smaller according to the new base addresses of each large class; if yes, amending the code of the program to be compiled, and amending the base address and the offset address of each command in the large class into new base address and new offset address so as to generate a target program. After the commands with same base address are classified into one set, the base addresses of the commands in the set are selected again, so that the offset of the memory access command is reduced, the size of the memory access command is decreased, and then the total program size is reduced.
Description
Technical field
The present invention relates to computer realm, more particularly to a kind of program compiling method and compiler.
Background technology
At present, according to statistics display, it is exactly the instruction of internal storage access using most class instructions in program.To be compiled
Program, in such as C source code, the access for a structure would generally be compiled device and is translated as corresponding internal storage access and refers to
Order.The internal storage access instruction of different framework instruction set typically broadly falls into following two types：The first is to be posted by one
Storage (that is, base address register) adds that a constant offset address accesses the content of one piece of memory address, and second is to pass through
In one depositor (that is, base address register) adds that the address of another one depositor (that is, offset register) accesses one piece
Deposit the content of address.For example, in AArch64 framework instruction set, ldr w8, [x1, #4], the internal storage access belonging to the first kind refers to
Order, represents and the content of depositor x1 is added constant 4, using the result obtaining as memory address, and the content of this address is read
Enter in depositor w8；And ldr w8, [x1, x2], then belong to the internal storage access instruction of Equations of The Second Kind, represent in depositor x1
Hold the content plus depositor x2, the result obtaining is as memory address, and the content of this address is read in depositor w8.
In PI32-V2 framework instruction set, also there is the similar first kind to instruct, such as r8=[r1+4], represent that the depositor of r8 is base
Location r1 adds 4 content；Equations of The Second Kind instructs, such as r8=[r1+r2], represents that the depositor of r8 is that base address r1 adds shift register
Device r2.
Because every instruction needs the coding of certain length, and this coding is limited, so typically, the first kind
The constant offset scope of internal storage access instruction is conditional, such as, in AArch64, the deviation range of first kind instruction is -128
× 4 to 128 × 4.If we need the offset address accessing bigger than the scope limiting, we can only move first with one
The instruction of dynamic constant, moves to skew in one depositor, then instructs to access by Article 2 again.This unnecessary step
Suddenly code size can be made to become big.Still further aspect, in some instruction set, in such as PI32-V2, first kind instruction has two kinds not
Same coding form, one kind is short coding form, can only encode shorter deviation range, and another is long codes form, can
To encode longer deviation range.If generating the first kind instruction of more long codes forms in a program,
Final code size can be made to become big.
In traditional technique of compiling, structure is accessed it will usually generate above-mentioned internal storage access instruction, for example, right
F.a=10 in C source code；F.b=10；Assume that the address of f is stored in r0, the skew of domain a is 80, and the skew of domain b is 84,
Then for PI32-V2 instruction set, this assignment can be translated three assembly instructions and be：R1=10；[r0+80]=r1；[r0+84]=
r1；Here the instruction generating is the instruction of the long codes form in the first kind.In practical programs, such assignment statement is often
Relatively more, and can compare concentration, so traditional method can generate the instruction of more long codes forms so that code size
Larger.
Content of the invention
Based on this it is necessary to provide a kind of program compiling method and compiler, it is possible to reduce the coding of internal storage access instruction
Size.
A kind of program compiling method, methods described includes：
Read program to be compiled, and record base address and the offset address that every internal storage access instructs, described internal memory
The memory address of access instruction is equal to the offset address plus this instruction for the base address of this instruction；
Internal storage access instruction described in the identical of base address is divided into a big class；
The memory address of the minimum instruction of each big apoplexy due to endogenous wind offset address is new as all described instructions of this big apoplexy due to endogenous wind
Base address；
Calculate each big class according to the new base address of each big class to visit using the internal memory whether new base address can make this big class
Ask that the total code length of instruction diminishes；If there is the big class that total code length diminishes, change the generation of described program to be compiled
Code, the base address of every of these big apoplexy due to endogenous wind described instruction is modified as new base address, offset address is revised as new skew
Address, to generate target program.
Wherein in an embodiment, internal storage access instruction described in the described identical by base address is divided into the step of a big class
Suddenly, also include being ranked up the described internal storage access instruction of each big apoplexy due to endogenous wind from small to large by offset address.
Wherein in an embodiment, the described memory address using instruction minimum for each big apoplexy due to endogenous wind offset address is big as this
After the step of new base address of all described instructions of apoplexy due to endogenous wind, also include being grouped the described instruction of each big apoplexy due to endogenous wind further
Step；
The step that the described instruction of one big apoplexy due to endogenous wind is grouped further includes：
Step A, checks the described instruction of this big apoplexy due to endogenous wind from small to large according to offset address, and by with described new base address
For base address when, instruction code length be that the described instruction of the shortest code length is added to described new base address as base
In the group of location；
Step B, when viewing with described new base address for base address, instruction code length be not the shortest coding length
The internal storage access instruction of degree, then create a new group using the memory address of this instruction as new base address；
Repeat step A, B is until finishing all instruction packets of this big apoplexy due to endogenous wind.
Wherein in an embodiment, described step B is：
When viewing with described new base address for base address, in the not short code length of code length of instruction
Deposit access instruction, then
Attempt ensure the code length of instruction of current group constant on the premise of, the base address of current group increased so that
The offset address of the internal storage access instruction currently viewing reaches the shortest code length, and using the base address after increasing as current
The new base address of group；
If attempting unsuccessful, a new group is created as new base address using the memory address of this instruction.
Wherein in an embodiment, the described code changing described program to be compiled, by every of these big apoplexy due to endogenous wind
The base address of described instruction is modified as new base address, offset address is revised as new offset address, to generate target program
Step, specially：
The instruction of the modification base address of each big class is inserted into the target location of described target program；Wherein, described
Target location is so that the position that was performed before all described instructions of this big apoplexy due to endogenous wind of the instruction of the modification base address of each big class
Put；
The base address of every of these big apoplexy due to endogenous wind described instruction is modified as new base address, offset address be revised as new
Offset address.
Wherein in an embodiment, described reading program to be compiled, and record the base of every internal storage access instruction
Location and the step of offset address, specially：
Read program to be compiled, and described procedure division to be compiled is become some functions；
Record the base address of every internal storage access instruction and offset address in each function.
A kind of compiler, described compiler includes：
Program load-on module, this program load-on module is used for reading program to be compiled, and records every internal storage access and refer to
The base address of order and offset address；The base address that the memory address of described internal storage access instruction is equal to this instruction adds this instruction
Offset address；
Base address conversion module, the input of this base address conversion module is connected with the outfan of described program load-on module
Connect, this base address conversion module is used for for internal storage access instruction described in the identical of base address being divided into a big class, and by each big class
The memory address of the minimum instruction of middle offset address is as the new base address of all described instructions of this big apoplexy due to endogenous wind；
Code length computing module, the outfan phase of the input of this code length computing module and base address conversion module
Connect, this code length computing module is used for using behind new base address according to the new base address each big class of calculating of each big class,
The total code length of the internal storage access instruction of this big class；
Cost judge module, the input of this cost judge module is connected with the outfan of described code length computing module
Connect, this cost judge module is used for calculating whether each big class can make this using new base address according to the new base address of each big class
The total code length of the internal storage access instruction of big class diminishes；
The outfan of target program generation module, the input of this target program generation module and described cost judge module
It is connected, this target program generation module is used for there is the big class that total code length diminishes, then change described journey to be compiled
The code of sequence, the base address of every of these big apoplexy due to endogenous wind described instruction is modified as new base address, offset address is revised as newly
Offset address, to generate target program.
Wherein in an embodiment, also include：
Order module, the input of this order module is connected with the outfan of described base address conversion module, this sequence
The outfan of module is connected with the input of described code length computing module, and this order module is used for the institute of each big apoplexy due to endogenous wind
State internal storage access instruction to be ranked up from small to large by offset address.
Wherein in an embodiment, described base address conversion module includes：
Packet control unit, the input of this packet control unit is connected with the outfan of described order module, this point
Group control unit finishes for whether all instructions judging this big apoplexy due to endogenous wind are grouped；
First grouped element, the input of this first grouped element is connected with the outfan of packet control unit, and this
One grouped element is used for, when all instructions of this big apoplexy due to endogenous wind are not grouped and finish, checking this big class from small to large according to offset address
In described instruction, and by with described new base address for base address when, instruction code length be the shortest code length institute
State instruction to be added in the group with described new base address as base address；
Second packet unit, the input of this second packet unit is connected with the outfan of described first grouped element,
This second packet unit is used for when viewing with described new base address for base address, the code length of instruction is not the shortest volume
The internal storage access instruction of code length, then create a new group using the memory address of this instruction as new base address.
Wherein in an embodiment, described second packet unit includes：
Code length judgment sub-unit, the input of this code length judgment sub-unit is defeated with described first grouped element
Go out end to be connected, this code length judging unit be used for check whether exist with described new base address for base address when, instruction
Code length be not the shortest code length internal storage access instruction；
Packet subelement, the input of this packet subelement is connected with the outfan of this code length judgment sub-unit,
This packet subelement is used for when viewing with described new base address for base address, the code length of instruction is not the shortest coding
The internal storage access of length instructs, it tries on the premise of the code length ensureing the current offset address organized is constant, by currently
The base address of group increases so that the offset address of the internal storage access instruction currently viewing reaches the shortest code length, and will increase
Base address afterwards is as the new base address of current group, if attempting unsuccessful, using the memory address of this instruction as new base
One new group of address creation.
Wherein in an embodiment, described target program generation module is additionally operable to the modification base address of each big class
Instruction is inserted into the target location of described target program；Wherein, described target location is the modification base making each big class
The position that the instruction of location was performed before all described instructions of this big apoplexy due to endogenous wind.
Wherein in an embodiment, described program load-on module includes：
Program reading unit, for reading program to be compiled；
Procedure division unit, the input of this procedure division unit is connected with the outfan of this program reading unit, should
Procedure division unit is used for for described procedure division to be compiled becoming some functions；
Recording unit, the input of this recording unit is connected with the outfan of described program division unit, this label
Unit is for recording the base address of every internal storage access instruction and offset address in each function.
Above-mentioned program compiling method and compiler, by being classified as after a set instruction of base address identical, again
Select the base address of the instruction in this set so that the skew of internal storage access instruction reduces, thus reducing internal storage access instruction
Size, and then decrease the size of total program, range of application is relatively broad.
Brief description
Fig. 1 is the compiling flow process of an embodiment Computer program；
Fig. 2 is the flow chart of an embodiment Program Compilation Method；
Fig. 3 is the structural representation of an embodiment Program compiler.
Wherein,
100 program load-on modules
110 program reading unit
120 procedure division units
130 recording units
200 base address conversion modules
210 first grouped elements
220 second packet units
230 packet control units
221 code length judgment sub-unit
222 packet subelements
300 code length computing modules
400 cost judge modules
500 target program generation modules
600 order module
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is used only for explaining the present invention, and
It is not used in the restriction present invention.
Describe in detail according to embodiments of the invention before it should be noted that, described embodiment essentially consist in
The program compiling method step related with compiler and the combination of system component.Therefore, said system assembly and method and step be
Through being showed in position by ordinary symbol, and merely illustrate in the accompanying drawings and understand embodiments of the invention
Relevant details, in order to avoid because of those details moulds obvious for the those of ordinary skill in the art having benefited from the present invention
Paste the disclosure.
Herein, such as left and right, upper and lower, front and rear, and first and second etc relational terms are used merely to area
Divide an entity or action and another entity or action, and not necessarily require or imply any between this entity or action
Actual this relation or order.Term " inclusion ", "comprising" or any other variant are intended to comprising of nonexcludability, by
This makes a series of process including key elements, method, article or equipment not only comprise these key elements, but also comprises not bright
Other key elements really listed, or for this process, method, article or the intrinsic key element of equipment.
Refer to shown in Fig. 1, Fig. 1 is the compiling flow process of an embodiment Computer program, in this embodiment, to be compiled
Program obtain intermediate representation through frontal chromatography, intermediate representation through several times middle-end optimize after, obtain final centre
Represent, finally code building is carried out to this intermediate representation, obtain last target program.Compilation Method in the present invention can be
Compiling flow process shown in whole Fig. 1 is it is also possible to be only wherein an intermediate representation to be converted into another intermediate representation
Process.The present embodiment and hereinafter with one section of C source code as an example so that this embodiment and this invention to be described.Hypothesis source
Program is：
After above-mentioned frontal chromatography and middle-end optimization several times it is assumed that before carrying out the method for the present invention, above-mentioned
Source program is translated into the intermediate representation after PI32-V2 instructs：
foobar:
V1=r1
V0=r0
V2=[v0+256]
V3=[v1+256]
V4=v3+v2
V5=[v0+260]
V6=v4+v5
V7=[v1+260]
V8=v6+v7
V9=[v0+264]
V10=v8+v9
V11=[v1+264]
V12=v10+v11
V13=[v1+268]
V14=v13<<1
V15=v12+v14
R0=v15
Rts
Now also do not carry out the distribution of depositor, wherein r0, r1 represents physical register, r0 is first parameter, r1 is
Second parameter, v0, v1 ... ..., v15 is virtual register, now only one of which foobar function, program therefore to be compiled
Only this foobar function.Compilation Method in the present invention is mainly passed through to collect one section of program (for example, in a function body)
Internal storage access instruction, then select appropriate base address, and in the new base address computations of appropriate position insertion so that
The skew of internal storage access instruction can reduce, and is finally reached the purpose of the total code size of reduction.
Refer to shown in Fig. 2, Fig. 2 is the flow chart of an embodiment Program Compilation Method, in this embodiment, the method
Can include：
S202：Read program to be compiled, and record base address and the offset address of every internal storage access instruction.Permissible
Find out that the memory address of internal storage access instruction is equal to the offset address plus this instruction for the base address of this instruction, in this embodiment
In, first have to check the instruction of function body one by one, then can obtain internal storage access instruction and its substantially situation.For example above-mentioned
Embodiment in, internal storage access instruction have：
V2=[v0+256]
V3=[v1+256]
V5=[v0+260]
V7=[v1+260]
V9=[v0+264]
V11=[v1+264]
V13=[v1+268]
Wherein in an embodiment, read program to be compiled, and record the base address of every internal storage access instruction with
And the step of offset address, can include reading program to be compiled, and procedure division to be compiled is become some functions.Record
The base address of every internal storage access instruction and offset address in each function.In the present embodiment, can be basic with function
Unit, only considers the internal storage access instruction in a range of function every time in the method, and the method is divided in execution depositor
Carry out before joining.Typically inside compiler, a function is identified as the set of some basic blocks, and a basic block is represented as
A series of instruction.
S204：Identical internal storage access instruction in base address is divided into a big class.In this embodiment, deposited with base address
Identical internal storage access instruction in base address, as the partitioning standards of big class, is therefore divided into a big class by device.For example in above-mentioned reality
Apply example and include two big class：
First big class, with v0 for original base address：
V2=[v0+256]
V5=[v0+260]
V9=[v0+264]
Second big class, with v1 for original base address：
V3=[v1+256]
V7=[v1+260]
V11=[v1+264]
V13=[v1+268]
S206：The memory address of the minimum instruction of each big apoplexy due to endogenous wind offset address is new as all instructions of this big apoplexy due to endogenous wind
Base address.For example in above-described embodiment, offset address minimum 256, therefore with the internal memory ground of the minimum instruction of this offset address
Location is the new base address of all instructions in this group, i.e. the first big apoplexy due to endogenous wind, the instruction being new base address with v2=[v0+256]
Comprise：
The new offset address of v2=[v0+256] this instruction is+0.
The new offset address of v5=[v0+260] this instruction is+4.
The new offset address of v9=[v0+264] this instruction is+8.
Second largest apoplexy due to endogenous wind, is comprised with the instruction that v3=[v1+256] is new base address：
The new offset address of v3=[v1+256] this instruction is 0.
The new offset address of v7=[v1+260] this instruction is+4.
The new offset address of v11=[v1+264] this instruction is+8.
The new offset address of v13=[v1+268] this instruction is+12.
S208：Calculate whether each big class can make in this big class using new base address according to the new base address of each big class
The total code length depositing access instruction diminishes.
S210：If there is the big class that total code length diminishes, change the code of described program to be compiled, these are big
The base address of the described instruction of every of apoplexy due to endogenous wind is modified as new base address, offset address is revised as new offset address, to generate
Target program.
Specifically, in above-mentioned example, the instruction of the first big apoplexy due to endogenous wind, need to increase the instruction of a modification base address：
V16=v0+256 increased this addition instruction, to change the base address of all instructions of this first big apoplexy due to endogenous wind, should
Instruct and instruct for long codes, cost is 4 bytes.
And in this example embodiment, the internal storage access instruction of the first big apoplexy due to endogenous wind is correspondingly revised as：
This instruction of v2=[v16+0] reduces by 2 bytes compared to original instruction v2=[v0+256].
This instruction of v5=[v16+4] reduces by 2 bytes compared to original instruction v5=[v0+260].
This instruction of v9=[v16+8] reduces by 2 bytes compared to original instruction v9=[v0+264].
Therefore to sum up analyze, the code space of 2 bytes can be reduced in the instruction of the first big apoplexy due to endogenous wind after compiling.
Will be revised as at v0+256 needing an addition instruction from v0 in base address in above-described embodiment, or need volume
The cost of 4 outer bytes, but the cost every of three instructions of other in this first big group can be reduced by 2 bytes simultaneously,
So this is profitable.
Can show that the instruction of second largest apoplexy due to endogenous wind can reduce the code space of 4 bytes in the same manner：
V17=v1+256 increased this addition instruction, to change the base address of all instructions of this first big apoplexy due to endogenous wind, should
Instruct and instruct for long codes, cost is 4 bytes.
And in this example embodiment, the instruction of second largest apoplexy due to endogenous wind：
This instruction of v3=[v17+0] reduces by 2 bytes compared to original instruction v3=[v1+256].
This instruction of v7=[v17+4] reduces by 2 bytes compared to original instruction v7=[v1+260].
This instruction of v11=[v17+8] reduces by 2 bytes compared to original instruction v11=[v1+264].
This instruction of v13=[v17+12] reduces by 2 bytes compared to original instruction v13=[v1+268].
Above-mentioned program compiling method, by being classified as, after a set, reselecting this collection the instruction of base address identical
The base address of the instruction in conjunction so that the skew of internal storage access instruction reduces, thus reducing the size of internal storage access instruction, and then
Decrease the size of total program, range of application is relatively broad.
Wherein in an embodiment, base address identical internal storage access is instructed the step being divided into a big class, that is, goes up
State step S204, can also include being ranked up the internal storage access instruction of each big apoplexy due to endogenous wind from small to large according to offset address.Example
Three instructions as the above-mentioned first big apoplexy due to endogenous wind can be ranked up according to the order of its offset address 256,260,264, i.e. v2=
[v0+256], v5=[v0+260], v9=[v0+264].The instruction of second largest apoplexy due to endogenous wind can also be ranked up in the same manner, and arrange
The mode of sequence can be arranged from small to large according to offset address or arranged from big to small according to offset address,
Will not be described here.
Wherein in an embodiment using the memory address of the minimum instruction of each big apoplexy due to endogenous wind offset address as this big apoplexy due to endogenous wind
After the step of new base address of all described instructions, can also include after step S206 entering the instruction of each big apoplexy due to endogenous wind
The step of one step packet.
Wherein in an embodiment, step according to being grouped the instruction of each big apoplexy due to endogenous wind further, specially：
Step A, checks the instruction of this big apoplexy due to endogenous wind from small to large according to offset address, and by with new base address as base address
When, the code length of instruction be that the instruction of the shortest code length is added in the group with new base address as base address.
For example, it is possible to refer to above-described embodiment, for the first big apoplexy due to endogenous wind, it is first according to offset address and is ranked up, choose
The address of the instruction corresponding to smallest offset address is new base address, that is, offset as at 256, for this first big apoplexy due to endogenous wind, wrapping
The instruction containing has：
The new offset address of v2=[v0+256] this instruction is+0.
The new offset address of v5=[v0+260] this instruction is+4.
The new offset address of v9=[v0+264] this instruction is+8.
It can be seen that the instruction that above-mentioned instruction only needs to short coding form can achieve, therefore do not need to be further continued for being grouped.
Step B, when viewing with new base address for base address, instruction code length be not the shortest code length
Internal storage access instructs, then create a new group using the memory address of this instruction as new base address.
For example, it is assumed that the first big apoplexy due to endogenous wind exist one when adopting new base address, need to carry out with long codes form
The internal storage access instruction of coding, then create a new group using the memory address of this instruction as new base address.
Repeat step A, B is until finishing all instruction packets of this big apoplexy due to endogenous wind.
Wherein in an embodiment, above-mentioned step B can include：
When viewing with new base address for base address, instruction code length be not the shortest code length internal memory visit
Ask instruction, it tries ensure the code length of instruction of current group constant on the premise of, by the base address of current group increase with
So that the internal storage access currently viewing is instructed and reach the shortest code length, and the base address after increasing is new as current group
Base address.If attempting unsuccessful, a new group is created as new base address using the memory address of this instruction.For example, false
Be located at the first big apoplexy due to endogenous wind exist one when adopting new base address, need the internal storage access being encoded with long codes form to refer to
Make A, then first attempt to change this new base address, in the first big apoplexy due to endogenous wind, new base address is v2=[v0+256], can attempt
Change this new base address be v5=[v0+260], then instruction v2=[v0+256] in base address the situation for v5=[v0+260]
Under new offset address be -4, instruction v9=[v0+264] be the new skew in the case of v5=[v0+260] in base address
Address be+4, the new offset address of computations A in the same manner, if this instruction A in base address the situation for v5=[v0+260]
Under code length be the shortest code length, then modification base address v2=[v0+256] be v5=[v0+260], if there is no
Such a base address, then can create a new group using the memory address of this instruction as new base address, such as to refer to
The memory address making A is new base address, or continues to attempt to other base address, such as with v9=[v0+264] as base address
Deng.
Wherein in an embodiment, change the code of program to be compiled, by the base of every instruction of these big apoplexy due to endogenous wind
Address is modified as new base address, offset address is revised as new offset address, the step to generate target program, specifically permissible
For：The instruction of the modification base address of each big class is inserted into the target location of target program；Wherein, target location is to make
The position that the instruction of the modification base address of each big class was performed before all instructions of this big apoplexy due to endogenous wind.These big apoplexy due to endogenous wind are every
Described in bar, the base address of instruction is modified as new base address, offset address is revised as new offset address.For example, from above-mentioned enforcement
In example, the execution of function foobar can be seen that during the new target location of the instruction of base address of insertion after v0=r0,
This position ensure that the instruction of conversion base address is performed before in the instruction of other internal storage access and is performed, and therefore passes through
After above-mentioned compiling, program to be compiled is ultimately converted to：
foobar:
V1=r1
V0=r0
V16=v0+256
V17=v1+256
V2=[v16+0]
V3=[v17+0]
V4=v3+v2
V5=[v16+4]
V6=v4+v5
V7=[v17+4]
V8=v6+v7
V9=[v16+8]
V10=v8+v9
V11=[v17+8]
V12=v10+v11
V13=[v17+12]
V14=v13<<1
V15=v12+v14
R0=v15
rts
Can be seen that the generation that this target program decreases 6 bytes compared to former program to be compiled through above-mentioned analysis
Code dimensional space, and through overtesting, by compile Linux 3.10 kernel to PI32-V2 instruction set as a example, using in the present invention
Method can reduce by general 2% code size compared with traditional Compilation Method.
Refer to shown in Fig. 3, Fig. 3 is the structural representation of an embodiment Program compiler, in this embodiment, compiling
Device can include program load-on module 100, base address conversion module 200, code length computing module 300, cost judge module
400 and target program generation module 500, the output of the input of this base address conversion module 200 and program load-on module 100
End is connected, and the input of this code length computing module 300 is connected with the outfan of base address conversion module 200, this generation
The input of valency judge module 400 is connected with the outfan of code length computing module 300, this target program generation module
500 input is connected with the outfan of cost judge module 400.
Wherein, this program load-on module 100 is used for reading program to be compiled, and records the base of every internal storage access instruction
Address and offset address；The memory address of this internal storage access instruction is equal to the skew ground plus this instruction for the base address of this instruction
Location.
This base address conversion module 200 is used for for identical internal storage access instruction in base address being divided into a big class, and will be each
The memory address of the minimum instruction of big apoplexy due to endogenous wind offset address is as the new base address of all described instructions of this big apoplexy due to endogenous wind.
This code length computing module 300 is used for calculating each big class using new base according to the new base address of each big class
Behind location, the total code length of the internal storage access instruction of this big class.
This cost judge module 400 is used for calculating each big class according to the new base address of each big class
The total code length that the no internal storage access that can make this big class instructs diminishes.
This target program generation module 500 is used for there is the big class that total code length diminishes, then change journey to be compiled
The code of sequence, the base address of every of these big apoplexy due to endogenous wind described instruction is modified as new base address, offset address is revised as newly
Offset address, to generate target program.
Wherein in an embodiment, this compiler can also include order module 600, the input of this order module 600
End is connected with the outfan of base address conversion module 200, the outfan of this order module 600 and code length computing module
300 input is connected, this order module 600 be used for by the instruction of the internal storage access of each big apoplexy due to endogenous wind according to offset address from little to
It is ranked up greatly.
Wherein in an embodiment, base address conversion module 200 can include the first grouped element 210, second packet
Unit 220 and packet control unit 230, the input of this packet control unit 230 is connected with the outfan of order module 600
Connect, the input of this first grouped element 210 is connected with the outfan of packet control unit 230, this second packet unit 220
Input be connected with the outfan of the first grouped element 210.
Wherein, this packet control unit 230 finishes for whether all instructions judging this big apoplexy due to endogenous wind are grouped.
This first grouped element 210 is used for checking the instruction of this big apoplexy due to endogenous wind from small to large according to offset address, and will be with new
Base address when being base address, the code length of instruction be that the instruction of the shortest code length is added to new base address as base
In the group of location.
This second packet unit 220 be used for when viewing with new base address for base address, instruction code length not
The internal storage access instruction of the shortest code length, then using the memory address of this instruction as new base address create one new
Group.
Wherein in an embodiment, this second packet unit 220 can include code length judgment sub-unit 221 and
Packet subelement 222, the input of this code length judgment sub-unit 221 is connected with the outfan of the first grouped element 210,
The input of this packet subelement 222 is connected with the outfan of this code length judgment sub-unit 221.
Wherein, this code length judgment sub-unit 221 be used for check whether exist with new base address for base address when, refer to
The code length of order is not the internal storage access instruction of the shortest code length.
This packet subelement 222 is used for when viewing with new base address for base address, the code length of instruction is not
The internal storage access instruction of the shortest code length, it tries in the premise that the code length of the offset address ensureing current group is constant
Under, the base address of current group is increased so that the offset address of the internal storage access instruction currently viewing reaches the shortest coding length
Degree, and using the base address after increasing as the current new base address organized, if attempting unsuccessful, with the memory address of this instruction
Create a new group as new base address.
Wherein in an embodiment, this target program generation module 500 is additionally operable to the modification base address of each big class
Instruction be inserted into the target location of target program；Wherein, target location is the finger of the modification base address making each big class
The position that order was performed before all instructions of this big apoplexy due to endogenous wind.
Wherein in an embodiment, this program load-on module 100 can include program reading unit 110, procedure division
Unit 120 and recording unit 130, the input of this procedure division unit 120 is connected with the outfan of program reading unit 110
Connect, the input of this recording unit 130 is connected with the outfan of procedure division unit 120.
Wherein, this program reading unit 110 is used for reading program to be compiled.This procedure division unit 120 is used for treating
The procedure division of compiling becomes some functions.This recording unit 130 is used for recording the base of every internal storage access instruction in each function
Address and offset address.
Here is omitted with regard to compiler embodiment, specifically may refer to described in above-mentioned Compilation Method.
Each technical characteristic of embodiment described above can arbitrarily be combined, for making description succinct, not to above-mentioned reality
The all possible combination of each technical characteristic applied in example is all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all it is considered to be the scope of this specification record.
Embodiment described above only have expressed the several embodiments of the present invention, and its description is more concrete and detailed, but simultaneously
Can not therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
Say, without departing from the inventive concept of the premise, some deformation can also be made and improve, these broadly fall into the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be defined by claims.
Claims (12)
1. a kind of program compiling method is it is characterised in that methods described includes：
Read program to be compiled, and record base address and the offset address that every internal storage access instructs, described internal storage access
The memory address of instruction is equal to the offset address plus this instruction for the base address of this instruction；
Internal storage access instruction described in the identical of base address is divided into a big class；
Using the memory address of the minimum instruction of each big apoplexy due to endogenous wind offset address as all described instructions of this big apoplexy due to endogenous wind new base
Location；
Calculate whether each big class can make the internal storage access of this big class refer to using new base address according to the new base address of each big class
The total code length of order diminishes；If there is the big class that total code length diminishes, change the code of described program to be compiled, will
The base address of every described instruction of these big apoplexy due to endogenous wind is modified as new base address, offset address is revised as new offset address,
To generate target program.
2. program compiling method according to claim 1 is it is characterised in that internal memory described in the described identical by base address is visited
Ask the step that instruction is divided into a big class, also include instructing by offset address from small to large the described internal storage access of each big apoplexy due to endogenous wind
It is ranked up.
3. program compiling method according to claim 2 is it is characterised in that described minimum by each big apoplexy due to endogenous wind offset address
After the step of the new base address as all described instructions of this big apoplexy due to endogenous wind for the memory address of instruction, also include each big apoplexy due to endogenous wind
The step that is grouped further of described instruction；
The step that the described instruction of one big apoplexy due to endogenous wind is grouped further includes：
Step A, checks the described instruction of this big apoplexy due to endogenous wind from small to large according to offset address, and by with described new base address as base
During address, the code length of instruction be that the described instruction of the shortest code length is added to described new base address as base address
In group；
Step B, when viewing with described new base address for base address, instruction code length be not the shortest code length
Internal storage access instructs, then create a new group using the memory address of this instruction as new base address；
Repeat step A, B is until finishing all instruction packets of this big apoplexy due to endogenous wind.
4. program compiling method according to claim 3 is it is characterised in that described step B is：
When viewing with described new base address for base address, instruction code length be not the shortest code length internal memory visit
Ask instruction, then
Attempt ensure the code length of instruction of current group constant on the premise of, the base address of current group increased so that current
The offset address of the internal storage access instruction viewing reaches the shortest code length, and using the base address after increasing as current group
New base address；
If attempting unsuccessful, a new group is created as new base address using the memory address of this instruction.
5. program compiling method according to claim 1 is it is characterised in that the generation of the described program to be compiled of described modification
Code, the base address of every of these big apoplexy due to endogenous wind described instruction is modified as new base address, offset address is revised as new skew
Address, the step to generate target program, specially：
The instruction of the modification base address of each big class is inserted into the target location of described target program；Wherein, described target
Position is so that the position that was performed before all described instructions of this big apoplexy due to endogenous wind of the instruction of the modification base address of each big class；
The base address of every of these big apoplexy due to endogenous wind described instruction is modified as new base address, offset address is revised as new skew
Address.
6. program compiling method according to claim 1, its feature for fear of, described read program to be compiled, and remember
The base address of every internal storage access instruction of record and the step of offset address, specially：
Read program to be compiled, and described procedure division to be compiled is become some functions；
Record the base address of every internal storage access instruction and offset address in each function.
7. a kind of compiler is it is characterised in that described compiler includes：
Program load-on module, this program load-on module is used for reading program to be compiled, and records every internal storage access instruction
Base address and offset address；The base address that the memory address of described internal storage access instruction is equal to this instruction adds the inclined of this instruction
Move address；
Base address conversion module, the input of this base address conversion module is connected with the outfan of described program load-on module,
This base address conversion module is used for for internal storage access instruction described in the identical of base address being divided into a big class, and will be inclined for each big apoplexy due to endogenous wind
Move the memory address of the minimum instruction in address as the new base address of all described instructions of this big apoplexy due to endogenous wind；
Code length computing module, the input of this code length computing module is connected with the outfan of base address conversion module
Connect, this code length computing module is used for using behind new base address according to the new base address each big class of calculating of each big class, should
The total code length of the internal storage access instruction of big class；
Cost judge module, the input of this cost judge module is connected with the outfan of described code length computing module,
This cost judge module is used for calculating whether each big class can make this big using new base address according to the new base address of each big class
The total code length of the internal storage access instruction of class diminishes；
Target program generation module, the input of this target program generation module is connected with the outfan of described cost judge module
Connect, this target program generation module is used for there is the big class that total code length diminishes, then change described program to be compiled
Code, the base address of every of these big apoplexy due to endogenous wind described instruction is modified as new base address, offset address be revised as new inclined
Move address, to generate target program.
8. compiler according to claim 7 is it is characterised in that also include：
Order module, the input of this order module is connected with the outfan of described base address conversion module, this order module
Outfan be connected with the input of described code length computing module, this order module be used for each big apoplexy due to endogenous wind is described interior
Deposit access instruction to be ranked up from small to large by offset address.
9. compiler according to claim 8 is it is characterised in that described base address conversion module includes：
Packet control unit, the input of this packet control unit is connected with the outfan of described order module, this packet control
Unit processed finishes for whether all instructions judging this big apoplexy due to endogenous wind are grouped；
First grouped element, the input of this first grouped element is connected with the outfan of packet control unit, this first point
Group unit is used for, when all instructions of this big apoplexy due to endogenous wind are not grouped and finish, checking this big apoplexy due to endogenous wind from small to large according to offset address
Described instruction, and by with described new base address for base address when, instruction code length be the shortest code length described finger
Order is added in the group with described new base address as base address；
Second packet unit, the input of this second packet unit is connected with the outfan of described first grouped element, and this
Two grouped elements are used for when viewing with described new base address for base address, the code length of instruction is not the shortest coding length
The internal storage access instruction of degree, then create a new group using the memory address of this instruction as new base address.
10. compiler according to claim 8 is it is characterised in that described second packet unit includes：
The outfan of code length judgment sub-unit, the input of this code length judgment sub-unit and described first grouped element
Be connected, this code length judging unit be used for check whether exist with described new base address for base address when, instruction volume
Code length is not the internal storage access instruction of the shortest code length；
Packet subelement, the input of this packet subelement is connected with the outfan of this code length judgment sub-unit, this point
Group subelement is used for when viewing with described new base address for base address, the code length of instruction is not the shortest code length
Internal storage access instruction, it tries ensure the code length of offset address of current group constant on the premise of, by current group
Base address increase so that currently view internal storage access instruction offset address reach the shortest code length, and will increase after
Base address is as the new base address of current group, if attempting unsuccessful, using the memory address of this instruction as new base address
Create a new group.
11. compilers according to claim 7 it is characterised in that described target program generation module be additionally operable to by
The instruction of the modification base address of each big class is inserted into the target location of described target program；Wherein, described target location is
Make the position that the instruction of the modification base address of each big class was performed before all described instructions of this big apoplexy due to endogenous wind.
12. compilers according to claim 7 are it is characterised in that described program load-on module includes：
Program reading unit, for reading program to be compiled；
Procedure division unit, the input of this procedure division unit is connected with the outfan of this program reading unit, this program
Division unit is used for for described procedure division to be compiled becoming some functions；
Recording unit, the input of this recording unit is connected with the outfan of described program division unit, and this recording unit is used
In the base address recording in each function every internal storage access instruction and offset address.
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| CN113656330A (en) * | 2021-10-20 | 2021-11-16 | 北京微核芯科技有限公司 | Method and device for determining access address |
| WO2022242291A1 (en) * | 2021-05-20 | 2022-11-24 | Huawei Technologies Co., Ltd. | Method and system for optimizing address calculations |
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