CN106373965B - A kind of manufacturing method of integrated 5 volts of devices and SONOS memory - Google Patents
A kind of manufacturing method of integrated 5 volts of devices and SONOS memory Download PDFInfo
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- CN106373965B CN106373965B CN201610985902.4A CN201610985902A CN106373965B CN 106373965 B CN106373965 B CN 106373965B CN 201610985902 A CN201610985902 A CN 201610985902A CN 106373965 B CN106373965 B CN 106373965B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
A kind of manufacturing method of integrated 5 volts of devices and SONOS memory, it include: to form 5 volts of devices regions formation, 5 volts of device grids structures, storage unit grid structure is formed in SONOS memory area, 5 volts of device grids structures include grid oxic horizon, gate polysilicon layer and the first silicon nitride layer sequentially formed on substrate；Storage unit grid structure includes ONO lamination, polysilicon layer and the second silicon nitride layer sequentially formed on substrate；Etch the upper layer oxide layer and nitration case of ONO lamination；In 5 volts of devices regions and SONOS memory area deposited oxide layer；Etching oxidation nitride layer forms the second side wall to form the first side wall in 5 volts of device grids structure side walls, in storage unit grid structure side wall；Sidewall section of the first time wet etching removal packet on the first silicon nitride layer and the second silicon nitride layer side wall is executed, the first diminution side wall and second is respectively formed and reduces side wall；It executes second of wet etching and removes the first and second silicon nitride layers.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of integrated 5 volts of devices and SONOS
The manufacturing method of memory.
Background technique
It since 5 volts of device Implantation Energies are big, needs to make the hard mask layer of polysilicon gate of silicon nitride, prevents 5 volts of injections from wearing
Saturating polysilicon.But this layer of hard mask layer finally needs to remove, and otherwise the hole etching on polysilicon gate can be blocked.
5 volts of SONOS of existing .13um (silicon-oxide-nitride-oxide-silicon) process choice increases by one of light shield
It removes the silicon nitride on polysilicon gate, but increases cost and process complexity.But if wet with 55nmHV (high pressure) technique
The method of method etching since SONOS device also has silicon nitride layer is easy that the silicon nitride layer of SONOS storage charge is made also to be corroded.
As a result, in this field, it is desirable to when 5 volts of devices and SONOS integrated, on the basis of not increasing mask
It realizes the removal hard silicon nitride mask layer of polysilicon gate, and the silicon nitride layer of SONOS storage charge is not had an impact.
Summary of the invention
The technical problem to be solved by the present invention is to for drawbacks described above exists in the prior art, providing one kind can be integrated
The manufacturing method thereof of 5 volts of devices and SONOS, wherein can not increased using the method for increasing the protection of one of thin silicon oxide side wall
Polysilicon gate silicon nitride hard mask layer is removed in the case where mask, and the silicon nitride layer of SONOS storage charge is not generated
It influences.
In order to achieve the above technical purposes, according to the present invention, a kind of integrated 5 volts of devices and SONOS memory are provided
Manufacturing method, comprising:
First step: 5 volts of device grids structures are formed forming 5 volts of devices regions, in SONOS memory area shape
At storage unit grid structure；Wherein, 5 volts of device grids structures include grid oxic horizon, the grid sequentially formed on substrate
Polysilicon layer and the first silicon nitride layer；Storage unit grid structure includes ONO lamination, the polysilicon layer sequentially formed on substrate
With the second silicon nitride layer；
Second step: the upper layer oxide layer and nitration case of etching ONO lamination；
Third step: in 5 volts of devices regions and SONOS memory area deposited oxide layer；
Four steps: etching oxidation nitride layer is to form the first side wall in 5 volts of device grids structure side walls, in storage unit
Gate structure sidewall forms the second side wall；
5th step: first time wet etching removal packet is executed on the first silicon nitride layer and the second silicon nitride layer side wall
Sidewall section, so that being respectively formed the first diminution side wall and second reduces side wall；
6th step: it executes second of wet etching and removes the first silicon nitride layer and the second silicon nitride layer.
Preferably, in the manufacturing method of integrated 5 volts of devices and SONOS memory, in the 6th step, second
Wet etching further etches the first diminution side wall and second and reduces side wall, to form the first final side wall and the second final side
Wall.
Preferably, in the manufacturing method of integrated 5 volts of devices and SONOS memory, the first silicon nitride layer and second
Silicon nitride layer is the same silicon nitride layer that same technique is formed.
Preferably, in the manufacturing method of integrated 5 volts of devices and SONOS memory, ONO lamination includes under upper
Upper layer oxide layer, nitration case and the tunnel oxide silicon of stacking.
Preferably, in the manufacturing method of integrated 5 volts of devices and SONOS memory, in the first step, formation is deposited
The etch step of storage unit gate structure is parked in the upper layer ONO oxide layer.
Preferably, in the manufacturing method of integrated 5 volts of devices and SONOS memory, after first step execution,
ONO is stacked in the size in substrate plane greater than polysilicon layer and the second silicon nitride layer.
Preferably, in the manufacturing method of integrated 5 volts of devices and SONOS memory, after second step execution,
ONO is stacked in the size in substrate plane equal to polysilicon layer and the second silicon nitride layer.
Preferably, it in the manufacturing method of integrated 5 volts of devices and SONOS memory, in the second step, does not etch
5 volts of device grids structures in 5 volts of devices regions.
Preferably, in the manufacturing method of integrated 5 volts of devices and SONOS memory, substrate is silicon substrate.
The present invention provides the manufacturing method thereofs that a kind of 5 volts of devices and SONOS are integrated, using one of thin silicon oxide side wall of increase
The method of protection can remove polysilicon gate silicon nitride hard mask layer in the case where not increasing mask, and not to SONOS
The silicon nitride layer of storage charge has an impact.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 schematically shows the manufacture of integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
The first step of method.
Fig. 2 schematically shows the manufactures of integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
The second step of method.
Fig. 3 schematically shows the manufacture of integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
The third step of method.
Fig. 4 schematically shows the manufactures of integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
The four steps of method.
Fig. 5 schematically shows the manufacture of integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
5th step of method.
Fig. 6 schematically shows the manufacture of integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
6th step of method.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that indicating that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to keep the contents of the present invention more clear and understandable, combined with specific embodiments below with attached drawing in of the invention
Appearance is described in detail.
Fig. 1 to Fig. 6 schematically shows integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
Manufacturing method each step.
As shown in Figures 1 to 6, the manufacturer of integrated 5 volts of devices and SONOS memory according to the preferred embodiment of the invention
Method includes:
First step: 5 volts of device grids structures are formed forming 5 volts of devices regions 100, in the memory areas SONOS
Domain 200 forms storage unit grid structure；
Wherein, 5 volts of device grids structures include grid oxic horizon 11, the gate polysilicon layer 12 sequentially formed on substrate
With the first silicon nitride layer 13；Storage unit grid structure includes the ONO (oxide-nitride-oxidation sequentially formed on substrate
Object) lamination 21, polysilicon layer 22 and the second silicon nitride layer 23；At this point, size of the ONO lamination 21 in substrate plane is greater than polycrystalline
Silicon layer 22 and the second silicon nitride layer 23；
For instance, it is preferred that the first silicon nitride layer 13 and the second silicon nitride layer 23 are the same silicon nitride that same technique is formed
Layer.
Generally, substrate is silicon substrate.
Specifically, ONO lamination 21 includes upper layer oxide layer, nitration case and the tunnel oxide silicon being laminated under upper.
Moreover, in the first step, the etch step for forming storage unit grid structure is parked in the upper layer ONO oxide layer.
Second step: the upper layer oxide layer and nitration case of etching ONO lamination 21；At this point, ONO lamination 21 is in substrate plane
Size be equal to polysilicon layer 22 and the second silicon nitride layer 23；
In the second step, 5 volts of device grids structures in 5 volts of devices regions 100 are not etched.
Third step: in 200 deposited oxide layer 30 of 5 volts of devices regions 100 and SONOS memory area；
Four steps: etching oxidation nitride layer 30 is storing to form the first side wall 31 in 5 volts of device grids structure side walls
Cell gate structure side wall forms the second side wall 32；
5th step: first time wet etching removal packet is executed in 23 side wall of the first silicon nitride layer 13 and the second silicon nitride layer
On sidewall section, so that being respectively formed the first diminution side wall 33 and second reduces side wall 34；
6th step: it executes second of wet etching and removes the first silicon nitride layer 13 and the second silicon nitride layer 23.At this point,
In 6th step, second of wet etching can further etch the first diminution side wall 33 and second and reduce side wall 34, to be formed
First final side wall 35 and the second final side wall 36.
The manufacturing method thereof integrated the present invention provides a kind of 5 volts of devices and SONOS as a result, using increase thin oxidation together
The method of sidewall silicon protection, can remove polysilicon gate hard mask layer, and not will cause in the case where not increasing mask
Silicon face damage.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two ", the descriptions such as " third " are used only for distinguishing various components, element, the step etc. in specification, each without being intended to indicate that
Component, element, the logical relation between step or ordinal relation etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
And it should also be understood that the present invention is not limited thereto and locate the specific method described, compound, material, system
Technology, usage and application are made, they can change.It should also be understood that term described herein be used merely to describe it is specific
Embodiment, rather than be used to limit the scope of the invention.Must be noted that herein and appended claims used in
Singular "one", "an" and "the" include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
The citation of multiple steps or device, and may include secondary step and second unit.It should be managed with broadest meaning
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as the function of also quoting from the structure
Equivalent.It can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Claims (7)
1. a kind of manufacturing method of integrated 5 volts of devices and SONOS memory, characterized by comprising:
First step: forming 5 volts of device grids structures forming 5 volts of devices regions, deposits in the formation of SONOS memory area
Storage unit gate structure；Wherein, 5 volts of device grids structures include grid oxic horizon, the gate polycrystalline sequentially formed on substrate
Silicon layer and the first silicon nitride layer；Storage unit grid structure includes ONO lamination, the polysilicon layer and sequentially formed on substrate
Nitride silicon layer, and ONO is stacked in the size in substrate plane greater than polysilicon layer and the second silicon nitride layer；
Second step: the size that the upper layer oxide layer and nitration case of etching ONO lamination are stacked in ONO in substrate plane is equal to
Polysilicon layer and the second silicon nitride layer；
Third step: in 5 volts of devices regions and SONOS memory area deposited oxide layer；
Four steps: etching oxidation nitride layer is to form the first side wall in 5 volts of device grids structure side walls, in storage unit grid
Structure side wall forms the second side wall；
5th step: side wall of the first time wet etching removal packet on the first silicon nitride layer and the second silicon nitride layer side wall is executed
Part, so that being respectively formed the first diminution side wall and second reduces side wall；
6th step: it executes second of wet etching and removes the first silicon nitride layer and the second silicon nitride layer.
2. the manufacturing method of integrated 5 volts of devices and SONOS memory according to claim 1, which is characterized in that the 6th
In step, second of wet etching further etches the first diminution side wall and second and reduces side wall, to form the first final side
Wall and the second final side wall.
3. the manufacturing method of integrated 5 volts of devices and SONOS memory according to claim 1 or 2, which is characterized in that the
One silicon nitride layer and the second silicon nitride layer are the same silicon nitride layer that same technique is formed.
4. the manufacturing method of integrated 5 volts of devices and SONOS memory according to claim 1 or 2, which is characterized in that ONO
Lamination includes upper layer oxide layer, nitration case and the tunnel oxide silicon being laminated under upper.
5. the manufacturing method of integrated 5 volts of devices and SONOS memory according to claim 4, which is characterized in that first
In step, the etch step for forming storage unit grid structure is parked in the upper layer ONO oxide layer.
6. the manufacturing method of integrated 5 volts of devices and SONOS memory according to claim 1 or 2, which is characterized in that
In second step, 5 volts of device grids structures in 5 volts of devices regions are not etched.
7. the manufacturing method of integrated 5 volts of devices and SONOS memory according to claim 1 or 2, which is characterized in that lining
Bottom is silicon substrate.
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| CN201610985902.4A CN106373965B (en) | 2016-11-09 | 2016-11-09 | A kind of manufacturing method of integrated 5 volts of devices and SONOS memory |
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