CN106373876A - Method of improving edge defect of etching chamber of asymmetric electrostatic chuck - Google Patents
Method of improving edge defect of etching chamber of asymmetric electrostatic chuck Download PDFInfo
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- CN106373876A CN106373876A CN201611028534.0A CN201611028534A CN106373876A CN 106373876 A CN106373876 A CN 106373876A CN 201611028534 A CN201611028534 A CN 201611028534A CN 106373876 A CN106373876 A CN 106373876A
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- etching
- electrostatic chuck
- etch
- edge defect
- asymmetry
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- 238000005530 etching Methods 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 82
- 230000007547 defect Effects 0.000 title claims abstract description 25
- 230000008569 process Effects 0.000 claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 239000006227 byproduct Substances 0.000 claims abstract description 32
- 238000006243 chemical reaction Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 229910052756 noble gas Inorganic materials 0.000 claims description 13
- 150000002835 noble gases Chemical class 0.000 claims description 13
- 239000012895 dilution Substances 0.000 claims description 10
- 238000010790 dilution Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 230000003628 erosive effect Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 abstract 1
- 239000000047 product Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a method of improving the edge defect of an etching chamber of an asymmetric electrostatic chuck, comprising the following steps: S1, providing a plasma reaction chamber for implementing a polycrystalline silicon gate etching process and a semiconductor structure needing to be processed through a polycrystalline silicon gate etching process; S2, fixing an electrostatic chuck in an asymmetric way in the plasma reaction chamber; and S3, placing the semiconductor structure in the reaction chamber to implement a polycrystalline silicon gate etching process, wherein an additional cleaning step for reducing residual etching by-products in the etching chamber is implemented one or more steps before or after a predetermined step of polycrystalline silicon etching.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to one kind improves asymmetry electrostatic inhale
The method of disk etching cavity edge defect.
Background technology
Enter the super large-scale integration epoch with integrated circuit technique, the process of integrated circuit towards 65nm with
And smaller size of structural development, wafer manufacturing process is proposed with higher finer technical requirements simultaneously.Wherein, in etching
The etching defect producing becomes more and more sensitive to the yield of wafer.In order to tackle integrated circuit to deep-submicron down to nanometer chi
Degree development, the plasma dry etch process technology occupying critical role in semiconductor fabrication has also obtained constantly
Development, wherein mainly has the film layer structure designing technique of the chip that is etched and the exploitation of etching technics optimisation technique itself.Due to
Be etched pattern line miniaturization development, etch process parameters optimization also seems particularly significant.
Polycrystalline in large scale integrated circuit crosses using plasma etching in technical process at present, and also referred to as dry method is carved
Erosion, is to carry out thin film lithographic technique using plasma.In the presence of gas is with plasma form, it possesses two features:
One to be that aerochemistry activity ratio in plasma is eager to excel under normality a lot, and according to the difference of the material that is etched, it is suitable to select
Gas, it is possible to quickly be reacted with material, realizes the purpose that etching removes；Two are available with electric field plasma
Guide and accelerate so as to possess certain energy, when it bombards the surface of the thing that is etched, can be by the former of thing material that be etched
Son hits, thus reaching the purpose realizing etching using energy transfer physically.Therefore, dry etching is wafer surface
Physics and the result of chemical two kinds of process balances.
Dry etching is divided into three kinds again: physical property etching, and chemical etches, and physical chemistry etches.Wherein physical property is carved
Erosion is also called physical sputter etch.It is obvious that this ise leans on the bombardment of energy to get process and the sputtering very phase of atom
Seemingly.Chemical etching is with the material that is etched, chemical reaction to occur using the chemism atomic group in plasma, thus realizing
Etching purpose.Due to core or the chemical reaction of etching, the therefore effect of etching and wet etching is a bit close, has preferably
Selectivity, but anisotropy is poor.
Accordingly, it is desirable to a kind of asymmetry electrostatic chuck etching cavity edge defect of can improving can be provided
Method.
Content of the invention
The technical problem to be solved is that there is drawbacks described above in prior art, provides one kind can improve
The method of asymmetry electrostatic chuck etching cavity edge defect.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided one kind improves asymmetry electrostatic chuck etch chamber
The method of body edge defect, comprising:
First step: provide for the plasma reaction chamber of polycrystalline silicon gate grid etching process and need to execute polysilicon
The semiconductor structure of grid etch PROCESS FOR TREATMENT；
Second step: fixing quiet in the way of making electrostatic chuck have asymmetry in described plasma reaction chamber
Electric sucker；
Third step: described semiconductor structure is placed in reaction cavity and carries out polycrystalline silicon gate grid etching process；Wherein, exist
Before or after the one or multi-step of the predetermined process of etching polysilicon, execution reduces the etch by-products of residual in etching cavity
Additional removing step.
Preferably, in second step, using the fixing electrostatic chuck of single-cantilever so that electrostatic chuck has asymmetry.
Preferably, in third step, described additional step of removing reduces the etching remaining in etching cavity using gas
By-product.
Preferably, the described additional gas that used of step of removing includes: noble gases and/or do not produce etch by-products
Etching gas.
Preferably, in third step, in additional removing step, reduce etching by increasing in etching polysilicon formula
The step of by-product is reducing the etch by-products of residual in etching cavity.
Preferably, described predetermined process includes: ARC etch step, hard mask etching step, etching polysilicon
Step and etch step.
Preferably, described additional removing step includes: in the ARC etch step of polycrystalline silicon etching process process
The step that the noble gases increasing afterwards dilute etch by-products.
Preferably, described additional removing step includes: increases after the hard mask etching step of polycrystalline silicon etching process process
Plus noble gases dilute etch by-products step.
Preferably, described additional step of removing includes: increases after the etch step of polycrystalline silicon etching process process
The step that noble gases dilute etch by-products.
Preferably, described additional removing step includes: after polycrystalline silicon etching process process terminates using noble gases or
The step that non-reactive gas carry out gas dilution to etching cavity.
Using technical scheme, specific by adding before or after the committed step of etching polysilicon formula
Gas dilution step and for this step carry out evacuation (pump down) to detach dilution etching process in produce by-product
Thing gas, reduces deposition above cantilever for the polymer, effectively eliminates cantilever top edges etching defect, improves etching reaction
The service efficiency of cavity, the electric property of wafer and the yield of product, reduce product rejection rate.
Brief description
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features are more easily understood, wherein:
Fig. 1 schematically shows and according to the preferred embodiment of the invention improves asymmetry electrostatic chuck etching cavity side
The flow chart of the method for edge defect.
It should be noted that accompanying drawing is used for the present invention is described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.And, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
The invention discloses a kind of method improving asymmetry etching cavity etching edge defect, by carving in polysilicon
The step that one or multi-step special gas reduce etch by-products residual is added to carry out the polymerization of minimizing electrostatic sucker edge in erosion formula
The deposit of thing, thus solving the problems, such as the etching defect producing during etching polysilicon, improves the yield of product.The method is real
Now simple, with low cost.
Fig. 1 schematically shows and according to the preferred embodiment of the invention improves asymmetry electrostatic chuck etching cavity side
The flow chart of the method for edge defect.
As shown in figure 1, according to the preferred embodiment of the invention improve asymmetry electrostatic chuck etching cavity edge defect
Method include:
First step s1: provide for the plasma reaction chamber of polycrystalline silicon gate grid etching process and need to execute polycrystalline
The semiconductor structure that silicon gate etching technics is processed；
Second step s2: being fixed in the way of making electrostatic chuck have asymmetry in described plasma reaction chamber
Electrostatic chuck；
Preferably, in second step s2, using the fixing electrostatic chuck of single-cantilever so that electrostatic chuck has asymmetry.
Third step s3: described semiconductor structure is placed in reaction cavity and carries out polycrystalline silicon gate grid etching process；Wherein,
Before or after the one or multi-step of the predetermined process of etching polysilicon, execution reduces the etching by-product of residual in etching cavity
The additional removing step of thing.
Preferably, in third step s3, in additional removing step, described additional removing step reduces quarter using gas
The etch by-products of residual in erosion cavity.And preferably, the gas that described additional removing step is used includes but not only limits
In: noble gases (as he, ar etc.) and/or the etching gas (n not producing etch by-products2Deng co etc.).
Or, in third step s3, in additional removing step, reduce etching by increasing in etching polysilicon formula
The step of by-product is reducing the etch by-products of residual in etching cavity.
Specifically, described predetermined process refers to some key steps, for example, include: ARC (barc) etching step
Suddenly, hard mask etching step, etching polysilicon step, etch step etc..Specifically, additional removing step can include as
Under:
A) noble gases increasing after ARC (c-o) etch step of existing polycrystalline silicon etching process process are dilute
The step releasing etch by-products；This process can dilute the organic by-products gas producing in ARC etching process, reduces
Byproducts accumulation above cantilever；
B) in the hard mask (sio of existing polycrystalline silicon etching process process2/ sin) noble gases that increase after etch step
The step of dilution etch by-products；This process can dilute hard mask (sio2/ sin) the organic by-products gas that produces in etching process
Body, reduces the byproducts accumulation above cantilever；
C) the noble gases dilution etching increasing after silicon (si) etch step of existing polycrystalline silicon etching process process is secondary
The step of product；This process can dilute the organic by-products gas producing in silicon (si) etching process, reduces the pair above cantilever
Product accumulation；
D) after existing polycrystalline silicon etching process process terminates, using noble gases or non-reactive gas to etching cavity
The step carrying out gas dilution, reduces remaining bi-products gas.
Using technical scheme, specific by adding before or after the committed step of etching polysilicon formula
Gas dilution step and for this step carry out evacuation (pump down) to detach dilution etching process in produce by-product
Thing gas, reduces deposition above cantilever for the polymer, effectively eliminates cantilever top edges etching defect, improves etching reaction
The service efficiency of cavity, the electric property of wafer and the yield of product, reduce product rejection rate.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " 3rd " etc. describes each assembly being used only in differentiation description, element, step etc., rather than is used for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
The technology contents that the disclosure above all can be utilized are made many possible variations and modification, or are revised as to technical solution of the present invention
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
Interior.
And it should also be understood that the present invention is not limited to specific method described herein, compound, material, system
Make technology, usage and application, they can change.It should also be understood that term described herein be used merely to describe specific
Embodiment, rather than be used for limiting the scope of the present invention.Must be noted that herein and claims used in
Singulative " one ", " a kind of " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example
As the citation of " element " meaned with the citation to one or more elements, and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
Multiple steps or the citation of device, and potentially include secondary step and second unit.Should be managed with broadest implication
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of this structure
Equivalent.Can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Claims (10)
1. a kind of method improving asymmetry electrostatic chuck etching cavity edge defect is it is characterised in that include:
First step: provide for the plasma reaction chamber of polycrystalline silicon gate grid etching process and need to execute polysilicon gate
The semiconductor structure that etching technics is processed；
Second step: in fixing electrostatic suction in the way of making electrostatic chuck have asymmetry in described plasma reaction chamber
Disk；
Third step: described semiconductor structure is placed in reaction cavity and carries out polycrystalline silicon gate grid etching process；Wherein, in polycrystalline
Before or after the one or multi-step of the predetermined process of silicon etching, execution reduces the attached of the etch by-products remaining in etching cavity
Plus removing step.
2. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1, its feature exists
In in second step, using the fixing electrostatic chuck of single-cantilever so that electrostatic chuck has asymmetry.
3. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1 and 2, its feature
It is, in third step, described additional step of removing reduces the etch by-products remaining in etching cavity using gas.
4. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 3, its feature exists
In the gas that described additional removing step is used includes: noble gases and/or the etching gas not producing etch by-products.
5. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1 and 2, its feature
It is, in third step, in additional removing step, by increasing the step reducing etch by-products in etching polysilicon formula
Suddenly the etch by-products of residual in etching cavity are reduced.
6. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1 and 2, its feature
It is, described predetermined process includes: ARC etch step, hard mask etching step, etching polysilicon step and silicon are carved
Erosion step.
7. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1 and 2, its feature
It is, described additional step of removing includes: increase after the ARC etch step of polycrystalline silicon etching process process is lazy
The step of property gas dilution etch by-products.
8. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1 and 2, its feature
It is, described additional step of removing includes: the indifferent gas increasing after the hard mask etching step of polycrystalline silicon etching process process
The step that body dilutes etch by-products.
9. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1 and 2, its feature
It is, described additional step of removing includes: the noble gases increasing after the etch step of polycrystalline silicon etching process process are dilute
The step releasing etch by-products.
10. the method improving asymmetry electrostatic chuck etching cavity edge defect according to claim 1 and 2, it is special
Levy and be, described additional removing step includes: using noble gases or non-reacted after polycrystalline silicon etching process process terminates
The step that gas carries out gas dilution to etching cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611028534.0A CN106373876B (en) | 2016-11-18 | 2016-11-18 | A method of improving asymmetry electrostatic chuck etching cavity edge defect |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611028534.0A CN106373876B (en) | 2016-11-18 | 2016-11-18 | A method of improving asymmetry electrostatic chuck etching cavity edge defect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106373876A true CN106373876A (en) | 2017-02-01 |
| CN106373876B CN106373876B (en) | 2019-03-26 |
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| CN201611028534.0A Active CN106373876B (en) | 2016-11-18 | 2016-11-18 | A method of improving asymmetry electrostatic chuck etching cavity edge defect |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030181027A1 (en) * | 2002-03-25 | 2003-09-25 | Chao-Hu Liang | Method of forming a polysilicon layer |
| CN101290865A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing generating surface blemish in etching process |
| CN105140115A (en) * | 2015-07-22 | 2015-12-09 | 上海华力微电子有限公司 | Method for improving spherical defect by optimizing charge releasing step process condition |
-
2016
- 2016-11-18 CN CN201611028534.0A patent/CN106373876B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030181027A1 (en) * | 2002-03-25 | 2003-09-25 | Chao-Hu Liang | Method of forming a polysilicon layer |
| CN101290865A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing generating surface blemish in etching process |
| CN105140115A (en) * | 2015-07-22 | 2015-12-09 | 上海华力微电子有限公司 | Method for improving spherical defect by optimizing charge releasing step process condition |
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| Publication number | Publication date |
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| CN106373876B (en) | 2019-03-26 |
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