CN106373615A - Design of OTP memory with characteristic of regulation of readout speed with bit line load - Google Patents
Design of OTP memory with characteristic of regulation of readout speed with bit line load Download PDFInfo
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- CN106373615A CN106373615A CN201510424870.6A CN201510424870A CN106373615A CN 106373615 A CN106373615 A CN 106373615A CN 201510424870 A CN201510424870 A CN 201510424870A CN 106373615 A CN106373615 A CN 106373615A
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Abstract
In the OTP memory design, the bit line load is correspondingly increased along with the continuously increasing memory capacity, such that the reading mechanism failure can be caused. In order to prevent the failure, the charging time of the sensitive amplifier is must increased while the prolonging of the charging time can affect the key parameter reading speed. According to the present invention, on the basis of the analysis of the OTP memory sense amplifier working principle, the influence of the bit line load on the OTP memory readout speed is researched, and through the emulation, the readout circuit parameter of the OTP memory is optimized, such that the design of the OTP memory with the characteristic of the regulation of the readout time with the bit line load is provided.
Description
Technical field
The invention belongs to digital integrated electronic circuit technical field, it is related to the otp storage electricity that a kind of reading speed can be adjusted by bit-line load
Road, specifically, by substantial amounts of theory analysis and emulation, this patent elaborates the reading speed of otp memorizer is how to lead to
Cross bit-line load regulation.
Background technology
Otp (one time programmable) memorizer has integrated level as the nonvolatile memory that may only program once
The features such as height, access speed are fast, in Aero-Space, military project etc. in Flouride-resistani acid phesphatase, the exigent field of confidential nature, plays
Irreplaceable effect.After one-time programming, it is internal and at any time can be accurate that the data that stored is saved in storage chip forever
Read.Otp memorizer in this invention is a static memory, and readout sequence passes through the saltus step of address end address and produces, for protecting
Card is quick and accurately reads storage value, and reading mechanism must take into rational clock signal.
The species of otp memorizer is a lot, is much based on fuse and antifuse, and the otp memorizer introduced herein is based on antifuse
Structure.In antifuse otp memorizer, by the structure within memory element is changed to the programming of selected cell.Preferably
Under reading mechanism, do not have the memory element programming that ' 0 ' when reading, can be read, and the memory element passing through to program can read when reading
‘1’.With the requirement more and more higher to memory size, area is consequently increased, and rational memory topography is impact
The key factor of reading speed.
Sense amplifier is discharged to the memory element needing to read after charging, and electric discharge passes through residual voltage after a period of time
Judge storage information.However, due to there is electric capacity or big resistance, memory element in practice is not construed as ideally
Conducting and disconnection, electric discharge can be caused during bit line discharges slow and then lead to reading mechanism to malfunction；More likely due to bit-line load mistake
Greatly, in charging process, voltage is difficult to reach default voltage request in the short time, eventually the speed of restriction reading mechanism and accurately
Degree.
Content of the invention
It is an object of the invention to provide adjust the scheme of otp memorizer reading speed by bit-line load.
It is a further object to provide eliminating the scheme leading to the elongated factor of otp memorizer reading speed.
It is a further object to provide a kind of otp memory circuitry with faster reading speed.
It is a further object to provide a kind of method of raising otp memory operation frequencies.
The technical scheme is that, for a bit line, the parasitic capacitance of bit line is parasitic capacitance c being read a littlerWith
Parasitic capacitance c a little is not read on bit lineblSummation ct, size is: ct=cbl+cr.If it is single to connect storage on a bit line
Unit, the load that bit line connects is more, and the electric capacity on bit line is also just bigger accordingly.Due to parallel connection, the parasitic capacitance of generation is by public affairs
FormulaObtain.Due to the presence of bulky capacitor parasitic on bit line, bulky capacitor can be charged during charging,
Reaching identical voltage needs the more charging interval.Accordingly, in discharge regime, due to the presence of parasitic bulky capacitor, greatly electricity
Hold the electric charge of storage and memory element also form loop it is also desirable to discharge to memory element.It is difficult from the charging of charging stage,
Difficult to electric discharge during electric discharge, voltage declines identical amplitude situation and the charging and discharging time can be caused to lengthen.Further, since quilt
The discordance of the resistive memory cell size of programming, can guiding discharge size of current differ, if process choice is incorrect, very
Possible memory element assumes a big resistance value after programming, leads to the little velocity of discharge of leakage current excessively slow.Because both sides is former
Cause, ultimately results in read access time and lengthens.
Data read with program after the conductive characteristic of memory element and chip manufacturing process closely bound up.Manufacturing process is not
With after leading to memory element programming, distribution of resistance is uneven.And if the memory element connecting on bit line is excessive, due to being simultaneously
It is associated on bit line, not programmed memory element has electric capacity, be programmed that memory element has the junction capacity of gate tube,
In any case, parasitic capacitance superposition becomes big.Advanced line precharge is needed, in order to reach identical voltage, because parasitic during read operation
The presence of bulky capacitor, has got a lot of electric charges.Charging interval is extended, because the time of precharge is the crucial portion of read access time
Point, so total read access time is greatly affected.
Brief description
Fig. 1 is otp memory readout system Organization Chart.
Fig. 2 is the sensitive amplifier structure schematic diagram in the present invention.
Fig. 3 is the array extension figure of the memory element in the present invention.
Fig. 4 is the memory cell structure figure before the programming in the present invention.
Fig. 5 is the memory cell structure figure after the programming in the present invention.
Specific embodiment
Describe the present invention with example below in conjunction with the accompanying drawings.
As shown in figure 1, read-out system includes address pad input, address detected, pulse expansion, sense amplifier, the first order
Dice latch, second level dice latch, bidirectional data port, the output of data pad.Wherein, sense amplifier is
The core of whole reading circuit, the rough schematic of sense amplifier as shown in Fig. 2 wherein p1 is preliminary filling fulgurite, during unlatching pair
Bit line is charged, and discharge tube n1 closes around here, and bit line passes through the memory element electric discharge chosen, and p1 pipe is operated in full when initial
And area.In figure phase inverter is critical inverters, and its turn threshold is to ensure that the key factor of correct reading.Bl is bit line, this
Bright neutrality line hangs with 256 loads altogether, including the memory element to be read out that is chosen also have 255 not selected
As the memory element of load, so total load capacitance on a bit line is the electric capacity of selected cell upper 255 load units
Electric capacity.
The size of storage array is the main determining factor of the area of this chip, how memory element appropriate design to be well therefore
Save the key of area.Because each memory element is required for reading and programmed circuit, but each unit individually has one
Reading and programmed circuit are unreasonable and there is no need.Same line storage unit is therefore taken to share one group of reading circuit and volume
The scheme that journey circuit operates to bit line, is then operated to every string by address column selection.When arranging storage array,
Must take into the regular uniform noting layout distribution.In each memory block, laterally longitudinally staggered form memory cell.As Fig. 3
Shown.Wherein bl is bit line, total n row, each line position line on x direction is connected with some memory element, every bit line connects
Connect one group of programming and reading circuit, and the memory element of every a line by column selection address line traffic control it is ensured that selecting in a line bit line every time
Select string to be written and read operating, each unit is likely to be chosen by bit line and is written and read.Because reading out structure is by bit line
Choose, again to bit line discharges after being first charged to charging valve.In pre-charging stage, charging valve is electrically charged and all parasitic capacitances
Will be electrically charged.Charging interval can artificially arrange length by sp control signal, charges after finishing, and proceeds immediately to storage single
First discharge regime.Electric capacity after charged discharges to memory element, if the unit chosen by column selection bit line of address by
Programming, forms a discharge loop between memory element and charging capacitor, and the voltage of bl bit line declines, quilt after decline
Critical inverters upset below is realized reading.
It is equivalent to an electric capacity before antifuse programming, after programming, be equivalent to electric capacity a upper resistance, as shown in Figure 4, Figure 5,
Bit line is discharged by selected cell after charging, and respectively unprogrammed and programmed both of these case is emulated, draws bit line discharges
Situation, further relate to the operation principle of sense amplifier.Whole read-out system is operated in when under reading mechanism bit line through unprogrammed
Memory element discharge into level a, discharge into level b through the memory element of programming.The turn threshold of critical inverters is
Guarantee correctly to read the key factor of data, if sense amplifier to be guaranteed can accurately read ' 0 ' and ' 1 ',
The turn threshold of phase inverter necessarily be between level a and b.Turn threshold is preferably able to be in the average of two level a and b
About value, so there are enough surpluses for programming and unprogrammed memory element, various techniques could be guaranteed to greatest extent
Angle and at a temperature of read data accuracy.
Yet with the presence of bulky capacitor parasitic on bit line, bulky capacitor can be charged during charging, reach identical voltage needs
The more charging interval.Accordingly, in discharge regime, due to the presence of parasitic bulky capacitor, the electric charge of bulky capacitor storage and storage
Unit also form loop it is also desirable to discharge to memory element.Difficult from the charging of charging stage, difficult to electric discharge during electric discharge,
Voltage declines identical amplitude situation and the charging and discharging time can be caused to lengthen.Further, since being programmed that resistive memory cell is big
Little discordance, can guiding discharge size of current differ, if process choice incorrect it is likely that memory element after programming
Assume a big resistance value, lead to the little velocity of discharge of leakage current excessively slow.Due to both sides reason, ultimately result in read access time
Lengthen.
For a bit line, the parasitic capacitance of bit line is to be read the parasitic electricity not read on parasitic capacitance a little and bit line a little
Hold summation, if connecting memory element on a bit line, the load that bit line connects is more, and the electric capacity on bit line is also just corresponding
Bigger.Because load is to be connected in parallel on bit line, there is electric capacity in not programmed memory element, be programmed that memory element
There is the junction capacity of gate tube, in any case, parasitic capacitance superposition becomes big.Advanced line precharge is needed, in order to reach during read operation
To identical voltage, because the presence of parasitic bulky capacitor, a lot of electric charges are got.Charging interval is extended, due to precharge when
Between be read access time key component, so total read access time is greatly affected.Want that reducing readout time can pass through to reduce position
Linear load, but, if every bit line only connects a small amount of unit, under conditions of identical capacity, the sum of bit line can increase accordingly
Plus, the quantity of programming and reading mechanism also can increase, and the total area of memorizer also can increase therewith.Therefore reasonable arrangement bit line
On memory element it is ensured that on the premise of correct read-write, reducing chip area is final goal as far as possible.
First the situation of different bit-line loads is emulated in this invention, observe the impact to readout time for the bit-line load, and then
The otp reservoir designs that a kind of readout time can adjust by bit-line load are proposed.This invention is found by emulation, and bit line hangs 256
Readout time in the case of individual load will be considerably longer than the readout time in the case that bit line hangs 128 loads.This absolutely proves
Bit-line load unit is excessively the restraining factors very big to read access time.Due to the impact of parasitic capacitance, the load on bit line is got over
Many, the time of precharge is also more, eventually affects the reading speed of this chip.Reasonable arrangement bit-line load, it is to avoid mistake
The generation of big parasitic capacitance makes great sense.It can be seen that, bit-line load less otp memorizer readout time is shorter, can be by subtracting
Little bit-line load is obtaining shorter readout time.
Pass through theory analysis in the present invention and emulation shows, the readout time of otp memorizer can be got over by bit-line load control, load
Greatly, readout time is longer, and load is less, and readout time is shorter.The reading of otp memorizer can be greatly increased when bit-line load is excessive
Going out the time, thus reducing reading efficiency, making troubles to chip user, so bit line excessive load will be eliminated to storage as far as possible
The impact of device readout time.The impact to readout time for the bit-line load is analyzed, there is provided a kind of readout time can be by the present invention
The otp memory circuitry design that bit-line load is adjusted.
Claims (2)
1. the otp reservoir designs that a kind of reading speed can be adjusted by bit-line load are read it is characterised in that including otp memorizer
Go out system, sense amplifier, bit line signal, critical inverters；
Described sense amplifier is the part of most critical in otp memory readout system, and described bit line signal is described sensitive puts
Preliminary filling fulgurite, discharge tube, the memory element that will be programmed or read chosen and not selected conduct load is connected in big device
Memory element signal；
The input of described critical inverters is connected on described bit line signal, and critical inverters are to ensure that whether reading mechanism is normal
Key factor, for unprogrammed memory element, current potential after selected cell electric discharge for the bit line signal must be higher than closing
The turn threshold of key phase inverter；For the memory element of programming, current potential after selected cell electric discharge for the bit line signal must
Less than the turn threshold of critical inverters, so just can guarantee to read as ' 0 ' by unprogrammed memory element, by depositing of programming
Storage unit is read as ' 1 '.
2. a kind of bit-line load designs it is characterised in that including the memory element as bit-line load；
Described memory element is connected on described bit line signal, and described memory element is based on anti-fuse structures, is equivalent to before programming
One electric capacity, is equivalent to a resistance a upper electric capacity after programming.Under normal reading mechanism, the memory element of programming can be read
Go out ' 1 ', unprogrammed memory element can read ' 0 ', the definition of read threshold is exactly to make reading result be changed into ' 0 ' from ' 1 '
Programming after resistance value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510424870.6A CN106373615A (en) | 2015-07-20 | 2015-07-20 | Design of OTP memory with characteristic of regulation of readout speed with bit line load |
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| CN201510424870.6A CN106373615A (en) | 2015-07-20 | 2015-07-20 | Design of OTP memory with characteristic of regulation of readout speed with bit line load |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112133340A (en) * | 2020-09-16 | 2020-12-25 | 中国电子科技集团公司第五十八研究所 | Dual-mode input single event effect resistant SRAM (static random Access memory) quick reading circuit structure |
| CN112397126A (en) * | 2019-08-16 | 2021-02-23 | 爱思开海力士有限公司 | Memory device and method of operating memory device |
| TWI800880B (en) * | 2021-08-03 | 2023-05-01 | 円星科技股份有限公司 | Circuit module with improved line load |
-
2015
- 2015-07-20 CN CN201510424870.6A patent/CN106373615A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112397126A (en) * | 2019-08-16 | 2021-02-23 | 爱思开海力士有限公司 | Memory device and method of operating memory device |
| CN112397126B (en) * | 2019-08-16 | 2024-04-23 | 爱思开海力士有限公司 | Memory device and method of operating the same |
| CN112133340A (en) * | 2020-09-16 | 2020-12-25 | 中国电子科技集团公司第五十八研究所 | Dual-mode input single event effect resistant SRAM (static random Access memory) quick reading circuit structure |
| TWI800880B (en) * | 2021-08-03 | 2023-05-01 | 円星科技股份有限公司 | Circuit module with improved line load |
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