CN106372542B

CN106372542B - Data protection self-destruction system

Info

Publication number: CN106372542B
Application number: CN201610966747.1A
Authority: CN
Inventors: 王凯
Original assignee: Shanghai Controleasy Electronics Inc
Current assignee: Shanghai Controleasy Electronics Inc
Priority date: 2016-11-04
Filing date: 2016-11-04
Publication date: 2024-02-20
Anticipated expiration: 2036-11-04
Also published as: CN106372542A

Abstract

The invention relates to the technical field of data protection, in particular to a data protection self-destruction system, which comprises an SSD hard disk, a hard disk power supply loop, a self-destruction starting circuit, a self-destruction negative-pressure constant-current circuit and a power supply selection loop, wherein the hard disk power supply loop rectifies and filters an input hard disk power supply to be used as a normal power supply loop of the SSD hard disk, the output end of the hard disk power supply loop is connected to the power supply selection loop, the input end of the self-destruction negative-pressure constant-current circuit is connected with an external power supply, the self-destruction negative-pressure constant-current circuit limits the current of the input external power supply and then is connected to the power supply selection loop, the output end of the power supply selection loop is connected to the SSD hard disk, and the self-destruction starting circuit is additionally connected to the power supply selection loop. The system is powered by the hard disk during normal use, and the self-destruction negative-pressure constant-current circuit generates negative voltage during self-destruction starting to directly burn out storage particles in the SSD, so that data in the SSD can be rapidly destroyed under emergency conditions.

Description

Data protection self-destruction system

[ technical field ]

The invention relates to the technical field of data protection, in particular to a data protection self-destruction system.

[ background Art ]

With the development of semiconductor technology, high-capacity high-speed SSDs are becoming more and more popular, the continuous read-write speed of SSDs is up to 1.1GB/s and 1GB/s at present, which is completely incomparable with traditional magnetic disks, SSD solid state disks have a plurality of advantages compared with HDD hard disks, SSDs are being more and more widely applied to national defense, aviation, industry and personal computers, and SSD data security is becoming a great concern. Existing known data cleaning techniques include: 1. using the drive built-in "erase unit" command, which is an ATA era erase command, it was tested that only 4 devices of the 12 SSD devices completed erasing, but virtually all data was still accessible; 2. overwriting the entire disk, which is to overwrite all data with 1 or 0 or any number-it takes a long time to repeat this process, and the overwrite takes longer as the hard disk capacity increases; 3. demagnetizing, which works on HHD but not on SSD at all; while for single file cleanup: if the SSD device always writes and re-writes on the same block, the SSD device will be damaged quickly, so the FTL will balance all available memory space, the writing load becomes balanced, so many fragments will remain in the hard disk after the file is rewritten, when a single file is erased, the FTL cannot find all fragments before the file, so the SSD has failed to clear all single file coverage because it can only cover the current fragment, and the file fragments in the load balancing process cannot be deleted. In summary, SSD data is quickly erased, which is not possible with existing software or commands.

In order to protect privacy, confidentiality and achievements from leakage, a method for quickly and reliably destroying data is needed, so that the data can be quickly destroyed in an emergency, and technical achievements or confidential data are protected from leakage.

[ summary of the invention ]

According to the problem that the conventional erasing or rewriting of the SSD cannot meet the requirement at all, the invention designs a data protection self-destruction system, and a self-destruction circuit is added before the SSD is connected with a computer or other equipment, so that storage particles in the SSD are directly burned out, and special data in the SSD are protected.

In order to solve the problems, a data protection self-destruction system is designed, the data protection self-destruction system comprises an SSD hard disk, a hard disk power supply loop, a self-destruction starting circuit, a self-destruction negative-pressure constant-current circuit and a power supply selection loop, the hard disk power supply loop rectifies and filters an input hard disk power supply to be used as a normal power supply loop of the SSD hard disk, the output end of the hard disk power supply loop is connected to the power supply selection loop, the input end of the self-destruction negative-pressure constant-current circuit is connected to the power supply selection loop after limiting the input external power supply, the input end of the power supply selection loop is respectively provided with different power supplies by the hard disk power supply loop and the self-destruction negative-pressure constant-current circuit, the output end of the power supply selection loop is connected to the hard disk, the self-destruction starting circuit is additionally connected to the power supply selection loop, an MOS tube in the power supply loop is driven by the self-destruction starting circuit during normal use, the self-destruction starting circuit generates SSD, the power supply of the SSD hard disk is changed from +5V to-6V, and therefore stored particles in the SSD hard disk are directly burned.

The SSD hard disk comprises a power supply, a controller, a data interface and a plurality of storage particles, wherein the power supply is respectively connected with and supplies power to the controller and each storage particle, the data port of each storage particle is connected to the controller through a data bus, the controller is connected to the data interface, and data transmission is carried out through the data interface by an external hard disk data line.

The self-destruction starting circuit is provided with a self-destruction switch, and the self-destruction starting is controlled by adopting a double mirror circuit, the double mirror circuit is provided with a MOS tube for preventing power-down triggering, and a triode is further arranged for preventing power-up triggering, so that the initial state of the self-destruction starting circuit is limited, and the data protection self-destruction system is ensured to be stable in a non-self-destruction state when power-up and power-off are carried out.

The self-destruction starting circuit is internally provided with a chip U1 as a power management chip, the model of the chip U1 is LTC4352IMS, the number 1 pin of the chip U1 is connected with the number 3 pin and then connected to +5V power supply, a capacitor C2 is connected between the number 2 pin and the number 7 pin of the chip U1, the number 4 pin of the chip U1 is connected with the number 7 pin and the number 9 pin of the chip U1 respectively after being connected with a resistor R7, the number 5 pin of the chip U1 is connected with the +5V power supply and then connected to a power selection loop, the number 10 pin and the number 12 pin of the chip U1 are respectively connected with two ends of the capacitor C1, the number 11 pin of the chip U1 is respectively connected with the number 4 pin of the MOS tube Q3 and the number 4 pin of the MOS tube Q4, the number 1, the number 2 pin and the number 3 pin of the MOS tube Q3 are connected and then connected with the number 1, the number 2 pin and the number 3 pin of the MOS tube Q4 respectively, the MOS tube Q3 has pins 5, 6, 7, 8 and 9 connected to +5V power supply, the MOS tube Q4 has pins 5, 6, 7, 8 and 9 connected to +5V power supply, the +5V power supply has one end connected to the pin 5 of the MOS tube Q5, the MOS tube has pins 5, 6, 7, 8 and 9 connected in parallel, the MOS tube Q5 has pins 1, 2 and 3 connected to pins 1, 2 and 3 of the MOS tube Q6, the MOS tube Q6 has pins 5, 6, 7, 8 and 9 connected to-6V power supply, the MOS tube Q5 has pins 4 connected to the MOS tube Q6 and connected to-6V power supply in series with resistor R5, the MOS tube Q7 has pins 4 connected to the MOS tube Q7, the MOS tube Q7 has pins 3 connected to resistor R10 in series with the other end, the MOS tube Q7 has pins 1 and connected to GND resistor R8 in series with the MOS tube Q7, the base electrode of the triode Q11 is connected with the resistor R17 and then connected with the burn_1 end, the emitter electrode of the triode Q11 is connected with the power supply-6V, a resistor R18 is connected in series between the emitter electrode and the base electrode of the triode Q11, the collector electrode of the triode Q12 is connected with the pin 1 of the MOS Q7, the base electrode of the triode Q12 is connected with the resistor R19 and then connected with the burn_2 end, the emitter electrode of the triode Q12 is grounded, a resistor R20 is connected in series between the emitter electrode and the base electrode of the triode Q11, the double mirror circuit is driven by a self-destruction switch SW6, the No. 4 end of the self-destruction switch SW6 is connected with the DIS_SIG1 signal end, the No. 2 end of the self-destruction switch SW6 is connected with the resistor R14 after the DIS_SIG1 signal end is connected with the resistor R24, the other end of the resistor R14 is connected with the pin 1 of the MOS Q8, the base serial resistor R12 of the triode Q9 is connected with the No. 3 pin of the MOS tube Q8, the collector of the triode Q9 is connected with the collector of the triode Q10, the emitter of the triode Q9 is connected with the-6V power supply, the base serial resistor R13 of the triode Q10 and the resistor R16 are connected with the-6V power supply, the emitter of the triode Q10 is connected with the-6V power supply, the collector serial capacitor C5 of the triode Q10 is connected with the-6V power supply, the DIS_SIG2 signal end is sequentially connected with the resistor R28 and the resistor R25 and then connected with the No. 1 pin of the MOS tube Q13, the No. 1 pin of the MOS tube Q13 is connected with the-6V power supply after the other end serial resistor R27 is extracted, the No. 2 pin of the MOS transistor Q13 is connected with a power supply-6V, the No. 3 pin of the MOS transistor Q13 is connected with a resistor R22 in series and then is connected with the base electrode of a triode Q14, the No. 3 pin of the MOS transistor Q13 is additionally led out of one end of the No. 3 pin and is connected with a capacitor C7 in series and then is connected with a power supply-6V, the collector electrode of the triode Q14 is connected with the collector electrode of a triode Q15, the emitter electrode of the triode Q14 is connected with the power supply-6V, the two ends of the resistor R22 and the emitter electrode of the triode Q14 are connected with a resistor R21, a capacitor C6 and a resistor R26 in parallel, the base electrode of the triode Q15 is connected with the connecting point between the capacitor C6 and the resistor R26 in series, the emitter electrode of the triode Q15 is connected with the power supply-6V, the No. 3 pin of the MOS transistor Q13 is extracted out of one end of the MOS transistor Q13 and is connected with the base electrode of the triode Q24 in series, the emitter electrode of the triode Q24 is connected with the power supply-6V, the collector of the triode Q24 is connected with a power supply +5V after being connected with a resistor R51 and a resistor R52 in series, one end of the resistor R53 is extracted between the resistor R51 and the resistor R52 and then connected to a No. 1 pin of the MOS tube Q25, a No. 2 pin of the MOS tube Q25 is grounded, a No. 3 pin serial resistor R54 of the MOS tube Q25 is connected with the power supply +5V, a No. 1 pin of the MOS tube Q23 is connected with a signal end of the sburn_star after being connected with a resistor R49, a No. 2 pin of the MOS tube Q23 is connected with a base of the triode Q22, a power supply +5V is connected after being connected with a No. 3 pin serial resistor R55 of the MOS tube Q23, a power supply-6V is connected to a base serial resistor R48 of the triode Q22, and a collector of the triode Q22 and a collector of the triode Q15 are connected to one end of the resistor R5 after being connected in parallel.

The self-destruction negative-voltage constant-current circuit is controlled by a chip U3 as voltage regulation, the model of the chip U3 is LT8710, a No. 1 pin of the chip U3 is connected with a-6V power supply after being connected with a resistor R38 in series, a No. 2 pin of the chip U3 is grounded through a capacitor C42, two ends of the capacitor C42 are connected with a resistor R42 and a capacitor C43 in parallel, a No. 3 pin of the chip U3 is connected with a capacitor C45 in series and grounded after being connected with a No. 5 pin of the chip U3 is connected with a capacitor C44 in series, a No. 7 pin of the chip U3 is connected with a resistor R33 and then is connected with a grid of a MOS tube Q18, two ends of the resistor R33 are connected with a zener diode D1 in parallel, a No. 8 pin of the chip U3 is connected with a capacitor C40 in series and then is connected with a grid of the Q18, a source electrode of the MOS tube Q18 is connected with a resistor R34 in series and then is grounded, a drain electrode of the MOS tube Q18 is connected with a power supply in series L1 of the-6V, the MOS tube Q18 is connected with a capacitor C33 in series, the capacitor C33 is connected with the ground, and the capacitor C33 is connected with the capacitor C33 in parallel, the 11 number pin of the chip U3 is connected with the 4 number pin of the MOS tube Q17, the 12 number pin of the chip U3 is connected with the capacitor C41 and then grounded, and is connected with the 17 number pin and the 8 number pin, the 13 number pin of the chip U3 is connected with the +12V power supply, and is sequentially connected with the resistor R37 and the resistor R39 in series and then grounded, the 14 number pin of the chip U3 is connected with the 1 number, the 2 number and the 3 number pin of the MOS tube Q17 after being connected with the resistor R32, the 5 number, the 6 number, the 7 number, the 8 number and the 9 number pins of the MOS tube Q17 are connected with the capacitor C29 respectively in series, the two ends of the capacitor C29 are connected with the capacitor C28 in parallel, the capacitor C28 is connected with the +12V power supply after being connected with the inductor L1, the 15 number pin of the chip U3 is connected with the 1 number, the 2 number and the 3 number pin of the MOS tube Q17 in sequence, the 16 number pin of the chip U3 is connected with the 3 number pin of the MOS tube Q19 and is grounded after being connected with the resistor R39 in series, the 1 number pin of the MOS tube Q19 is connected with the resistor R40 in series, and the 1 number pin of the MOS tube Q19 is connected with the resistor R40 The resistor R35 is connected with +12V power supply at the rear, the No. 2 pin of the MOS tube Q19 is grounded, the No. 3 pin of the MOS tube is connected with the No. 16 pin of the chip U3, the No. 18 pin of the chip U3 is connected with the resistor in series and then the R41 is grounded, the +12V power supply is connected with the ground in parallel, the polar capacitor CT2, the capacitor C36, the capacitor C37, the capacitor C38 and the capacitor C39 are respectively connected in parallel, the No. 3 pin of the MOS tube Q19 is connected with the No. 8 pin of the chip U2 after being extracted from one end of the serial resistor R36, the No. 1 pin of the chip U2 is grounded after being connected with the resistor R31, the No. 1 pin of the chip U2 is additionally extracted from one end of the serial resistor R29 and then connected with +12V power supply, the No. 2 pin of the chip U2 is connected with +12V power supply, the No. 3 pin of the chip U2 is connected with the No. 1 pin of the MOS tube Q16, the No. 3 pin of the MOS tube Q16 is connected with +12V power supply, the No. 4 pin of the MOS tube Q16 is connected with the serial resistor R30 and then connected with the No. 8 pin of the chip U2, the chip U2 is connected with the chip 4, the chip is connected with the serial resistor C9, and the No. 2 is connected with the chip 7 is connected with the chip.

The power supply selection loop is characterized in that a power supply is switched by a MOS tube Q21, a No. 1 pin of the MOS tube Q21 is connected with a resistor R46 in series and then is connected with a +5V power supply, a No. 2 pin of the MOS tube Q21 is grounded, a No. 3 pin of the MOS tube Q21 is connected with a +12V power supply, a No. 3 pin of the MOS tube Q21 is connected to a base electrode of a triode Q20, an emitter electrode of the triode Q20 is grounded, a resistor R45 is connected in series between the emitter electrode and a collector electrode of the triode Q20 and then is grounded, and a collector electrode of the triode Q20 is connected with the resistor R43 and then is connected with the +5V power supply.

Compared with the prior art, the invention has the advantages that:

1. the system is provided with the power supply selection loop, so that the hard disk is used for supplying power in normal use, the self-destruction negative-pressure constant-current circuit generates negative voltage in self-destruction starting, a voltage difference is formed between the SSD hard disk and the power supply, storage particles in the SSD are directly burned out by utilizing the negative voltage, data in the SSD hard disk SSD can be rapidly destroyed in emergency, and the limit of the read-write speed of the hard disk SSD is avoided;

2. the self-destruction starting circuit is provided with a physical self-destruction switch, is simple to operate, does not need professional software and hardware knowledge, and can be started by pushing the switch, so that data self-destruction is realized;

3. the self-destruction starting circuit adopts the double mirror image circuit to control the self-destruction starting, avoids the damage of the hard disk caused by misoperation of the circuit, uses the MOS tube to limit the initial state to ensure the power-on and the power-off, ensures the circuit to be stable in the non-self-destruction state when the power-on and the power-off are carried out, is safe and reliable in the use process, has the self-destruction function and does not influence the normal use of a user.

[ description of the drawings ]

FIG. 1 is a schematic diagram of the system principle of the present invention;

FIG. 2 is a schematic circuit diagram of a self-destruct starting circuit in accordance with the present invention;

FIG. 3 is a schematic circuit diagram of the self-destroying negative voltage constant current circuit in the invention;

fig. 4 is a schematic circuit diagram of a power supply selection circuit in accordance with the present invention.

Detailed description of the preferred embodiments

The construction and principles of such a device will be apparent to those skilled in the art from the following description of the invention taken in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Example 1

Fig. 1 is a schematic diagram of the principle composition of the system, referring to fig. 1 for describing the technical scheme in detail, the data protection self-destruction system includes an SSD hard disk, a hard disk power supply circuit, a self-destruction starting circuit, a self-destruction negative voltage constant current circuit and a power supply selection circuit, the hard disk power supply circuit rectifies and filters an input hard disk power supply to be used as a normal power supply circuit of the SSD hard disk, and the hard disk power supply circuit adopts the prior art and is not described herein. The output end of the hard disk power supply loop is connected to the power supply selection loop, the input end of the self-destroying negative pressure constant current circuit is connected with an external power supply, the self-destroying negative pressure constant current circuit is used for limiting the input external power supply and then is connected to the power supply selection loop, the input end of the power supply selection loop is respectively provided with different power supplies by the hard disk power supply loop and the self-destroying negative pressure constant current circuit, the output end of the power supply selection loop is connected to an SSD hard disk, the SSD hard disk comprises a power supply, a controller, a data interface and a plurality of storage particles, the power supply is respectively connected and powered to the controller and each storage particle, the data port of each storage particle is connected to the controller through a data bus, the controller is connected to the data interface, and the data transmission is carried out through the data interface by an external hard disk data line. The power supply selection circuit is connected with a self-destruction starting circuit. The self-destruction starting circuit is provided with a self-destruction switch, and the self-destruction starting is controlled by adopting a double mirror circuit, the double mirror circuit is provided with a MOS tube for preventing power-down triggering, and a triode is also arranged for preventing power-up triggering, so that the initial state of the self-destruction starting circuit is limited, and the data protection self-destruction system is ensured to be stabilized in a non-self-destruction state when power-up and power-off are carried out. When the power supply selection loop is normally used, the hard disk is used for supplying power, and when the self-destruction starting circuit is used for starting, the MOS tube in the self-destruction starting circuit is driven to be on-off, so that the self-destruction negative-voltage constant-current circuit generates negative voltage, the power supply of the SSD hard disk is changed from original +5V to-6V, and therefore storage particles in the SSD hard disk are directly burned.

The circuit schematic diagram of the self-destruction starting circuit is shown in fig. 2, a chip U1 is arranged in the self-destruction starting circuit and is used as a power management chip, the model of the chip U1 is LTC4352IMS, the number 1 pin of the chip U1 is connected with the number 3 pin and then is connected with a +5V power supply, a capacitor C2 is connected between the number 2 pin and the number 7 pin of the chip U1, the number 4 pin of the chip U1 is connected with the number 7 pin and the number 9 pin of the chip U1 respectively after being connected with a resistor R7, the number 5 pin of the chip U1 is connected with the +5V power supply and then is connected with a power selection loop, the number 10 pin and the number 12 pin of the chip U1 are respectively connected with the two ends of the capacitor C1, the number 11 pin of the chip U1 is respectively connected with the number 4 pin of a MOS tube Q3 and the number 4 pin of the MOS tube Q4, the number 1, the number 2 pin and the number 3 pin of the MOS tube Q3 are connected with the number 1, the number 2 pin and the number 3 pin of the MOS tube Q4 are connected with the number 1, the number 2 and the number 3 pin of the MOS tube Q4 respectively, the pins 5, 6, 7, 8 and 9 of the MOS tube Q3 are connected with +5V power supply, the pins 5, 6, 7, 8 and 9 of the MOS tube Q4 are connected with +5V power supply, the +5V power supply is additionally extracted and connected with the pin 5 of the MOS tube Q5, the pins 5, 6, 7, 8 and 9 of the MOS tube are connected in parallel, the pins 1, 2 and 3 of the MOS tube Q5 are connected with the pins 1, 2 and 3 of the MOS tube Q6, the pins 5, 6, 7, 8 and 9 of the MOS tube Q6 are connected with-6V power supply, the pin 4 of the MOS tube Q5 is connected with the pin 4 of the MOS tube Q6 in series with a resistor R5 and then connected with-6V power supply, the pin 4 of the chip U1 is additionally extracted and connected with the pin 3 of the MOS tube Q7, the pin 3 of the MOS tube Q7 is connected with GND after the pin 3 of the MOS tube Q7 is connected with the resistor R10, the base of the triode Q11 is connected with a resistor R17 and then connected with a burn_1 end, the emitter of the triode Q11 is connected with a power supply-6V, a resistor R18 is connected in series between the emitter and the base of the triode Q11, the collector of the triode Q12 is connected with the pin 1 of the MOS Q7, the base of the triode Q12 is connected with a burn_2 end after being connected with the resistor R19, the emitter of the triode Q12 is grounded, a resistor R20 is connected in series between the emitter and the base of the triode Q11, the double mirror circuit is driven by a self-destruction switch SW6, the No. 4 end of the self-destruction switch SW6 is connected with a DIS_SIG1 signal end, the No. 2 end of the self-destruction switch SW6 is connected with a DIS_SIG2 signal end, the DIS_SIG1 signal end is connected with a resistor R24 and then connected with a resistor R14, the other end of the resistor R14 is connected to a No. 1 pin of the MOS tube Q8, one end of the No. 1 pin of the MOS tube Q8 is additionally extracted and connected with a resistor R15 in series and then connected with a-6V power supply, the No. 2 pin of the MOS tube Q8 is connected with a-6V power supply, the No. 3 pin of the MOS tube Q8 is connected with a capacitor C4 in series and then connected with a-6V power supply, one end of the resistor R11 is extracted and then connected with a capacitor C3, a base electrode serial resistor R12 of the triode Q9 is connected with the No. 3 pin of the MOS tube Q8, a collector electrode of the triode Q9 is connected with a collector electrode of the triode Q10, an emitter electrode of the triode Q9 is connected with a-6V power supply, a base electrode serial resistor R13 of the triode Q10 is connected with a-6V power supply, a collector electrode of the triode Q10 is connected with a capacitor C5 in series and then connected with a-6V power supply, a DIS_SIG2 signal end is sequentially connected with a resistor R28 and a resistor R25 and then connected with a No. 1 pin of the MOS tube Q13, the base of the MOS transistor Q13 is connected with the base of the triode Q14 after the end of the No. 1 pin of the MOS transistor Q13 is additionally extracted and connected with a power supply-6V after the resistor R27 is connected in series, the No. 2 pin of the MOS transistor Q13 is connected with the power supply-6V after the resistor R22 is connected in series, the other end of the No. 3 pin of the MOS transistor Q13 is extracted and connected with the power supply-6V after the capacitor C7 is connected in series, the collector of the triode Q14 is connected with the collector of the triode Q15, the emitter of the triode Q14 is connected with the power supply-6V, the resistor R21, the capacitor C6 and the resistor R26 are connected at both ends of the resistor R22 and the emitter of the triode Q14 in parallel, the base of the triode Q15 is connected with the connecting point between the capacitor C6 and the resistor R26 after the emitter of the triode Q15 is connected with the power supply-6V, the base of the No. 3 pin of the MOS transistor Q13 is extracted and connected with the base of the triode Q24 after the end of the triode Q50 in series, the emitter of the triode Q24 is connected with a-6V power supply, the collector of the triode Q24 is connected with a resistor R51 and a resistor R52 in series, then the power supply is connected with +5V, one end of the resistor R53 is extracted between the resistor R51 and the resistor R52 in series and then connected to a No. 1 pin of the MOS tube Q25, a No. 2 pin of the MOS tube Q25 is grounded, a No. 3 pin of the MOS tube Q25 is connected with a power supply +5V, a No. 1 pin of the MOS tube Q23 is connected with a sburn_star signal end after a No. 1 pin of the MOS tube Q23 is connected with a base of the triode Q22, a No. 3 pin of the MOS tube Q23 is connected with a power supply +5V after a No. 3 pin of the resistor R55 is connected with a power supply-6V, the emitter of the triode Q22 is connected with a power supply-6V after a base of the resistor R48 is connected with a collector of the triode Q22 in parallel, and then the collector of the triode Q15 is connected with one end of the resistor R5. The MOS tube Q8 and the MOS tube Q13 are used for preventing power-down triggering, the MOS tube Q10 and the MOS tube Q15 are used for preventing power-up triggering, and the circuit is ensured to be stable in a non-self-destruction state when power-up and power-off, so that the use process is safe and reliable. When the DIS_SIG1 end and the DIS_SIG2 end from the switch are connected to the ground, a signal for closing the MOS transistor Q3 and the MOS transistor Q4 is generated on the No. 4 pin of the chip U1, and meanwhile, a signal for enabling the MOS transistor Q5 and the MOS transistor Q6 to be conducted is output on the No. 5 pin of the chip U1, so that the power supply of an SSD interface is changed from the original +5V to-6V, and the damage effect on data in the SSD is achieved.

The self-destruction negative-voltage constant-current circuit is controlled by a chip U3 as voltage regulation, referring to FIG. 3, the model of the chip U3 is LT8710, the serial resistor R38 of the No. 1 pin of the chip U3 is connected with the grid of the MOS tube Q18, the serial resistor C35 of the chip U3 is connected with the grid of the Q18, the serial resistor R34 of the source electrode of the MOS tube Q18 is connected with the ground, the serial resistor R42 and the capacitor C43 are connected in parallel at two ends of the capacitor C42, the serial capacitor C45 of the No. 3 pin of the chip U3 is connected with the ground, the serial capacitor C44 of the No. 5 pin of the chip U3 is connected with the ground, the serial resistor R33 of the No. 7 pin of the chip U3 is connected with the grid of the MOS tube Q18, the serial capacitor C40 of the serial resistor C33 of the No. 10 pin of the chip U3 is connected with the grid of the Q18, the serial resistor R34 of the source electrode of the MOS tube Q18 is connected with the ground, the serial resistor L1 of the drain electrode of the MOS tube Q18 is connected with the power of the grid of the MOS tube, the serial resistor C1 is connected with the grid of the grid, the grid of the MOS tube C33 is connected with the grid, the grid of the MOS tube C33, the 11 number pin of the chip U3 is connected with the 4 number pin of the MOS tube Q17, the 12 number pin of the chip U3 is connected with the capacitor C41 and then grounded, and is connected with the 17 number pin and the 8 number pin, the 13 number pin of the chip U3 is connected with the +12V power supply, and is sequentially connected with the resistor R37 and the resistor R39 in series and then grounded, the 14 number pin of the chip U3 is connected with the 1 number, the 2 number and the 3 number pin of the MOS tube Q17 after being connected with the resistor R32, the 5 number, the 6 number, the 7 number, the 8 number and the 9 number pins of the MOS tube Q17 are connected with the capacitor C29 respectively in series, the two ends of the capacitor C29 are connected with the capacitor C28 in parallel, the capacitor C28 is connected with the +12V power supply after being connected with the inductor L1, the 15 number pin of the chip U3 is connected with the 1 number, the 2 number and the 3 number pin of the MOS tube Q17 in sequence, the 16 number pin of the chip U3 is connected with the 3 number pin of the MOS tube Q19 and is grounded after being connected with the resistor R39 in series, the 1 number pin of the MOS tube Q19 is connected with the resistor R40 in series, and the 1 number pin of the MOS tube Q19 is connected with the resistor R40 The resistor R35 is connected with +12V power supply at the rear, the No. 2 pin of the MOS tube Q19 is grounded, the No. 3 pin of the MOS tube is connected with the No. 16 pin of the chip U3, the No. 18 pin of the chip U3 is connected with the resistor in series and then the R41 is grounded, the +12V power supply is connected with the ground in parallel, the polar capacitor CT2, the capacitor C36, the capacitor C37, the capacitor C38 and the capacitor C39 are respectively connected in parallel, the No. 3 pin of the MOS tube Q19 is connected with the No. 8 pin of the chip U2 after being extracted from one end of the serial resistor R36, the No. 1 pin of the chip U2 is grounded after being connected with the resistor R31, the No. 1 pin of the chip U2 is additionally extracted from one end of the serial resistor R29, the No. 2 pin of the chip U2 is connected with +12V power supply, the No. 3 pin of the chip U2 is connected with the MOS tube Q16, the No. 3 pin of the MOS tube Q16 is connected with +12V power supply, the No. 4 pin of the MOS tube Q16 is connected with the serial resistor R30, one end of the chip U2 is connected with the No. 4 is connected with the serial resistor C6, the chip U2 is connected with the serial power supply, the chip is connected with the No. 5V 6, the chip is connected with the chip C2, and the chip is connected with the power supply, the signal is connected with the power supply, and the signal is connected with the signal of the chip, and the chip is connected with the chip.

The power supply selection loop is switched by the MOS tube Q21, the circuit diagram is shown in fig. 4, the No. 1 pin of the MOS tube Q21 is connected with a +5V power supply after being connected with a resistor R46 in series, the No. 2 pin of the MOS tube Q21 is grounded, the No. 3 pin of the MOS tube Q21 is connected with a +12V power supply after being connected with a resistor R44 in series, the No. 3 pin of the MOS tube Q21 is connected to the base electrode of the triode Q20, the emitter electrode of the triode Q20 is grounded, a resistor R45 is connected between the emitter electrode and the collector electrode of the triode Q20 in series and then grounded, and the collector electrode of the triode Q20 is connected with a +5V power supply after being connected with a resistor R43.

Claims

1. The data protection self-destruction system is characterized by comprising an SSD hard disk, a hard disk power supply loop, a self-destruction starting circuit, a self-destruction negative-pressure constant-current circuit and a power supply selection loop, wherein the SSD hard disk comprises a power supply, a controller, a data interface and a plurality of storage particles, the power supply is respectively connected and supplies power to the controller and each storage particle, the data port of each storage particle is connected to the controller through a data bus, the controller is connected to the data interface, an external hard disk data line carries out data transmission through the data interface, the hard disk power supply loop rectifies and filters an input hard disk power supply to be used as a normal power supply loop of the SSD hard disk, the output end of the hard disk power supply loop is connected to the power supply selection loop, the input end of the self-destruction negative-pressure constant-current circuit is connected with an external power supply, the self-destroying negative pressure constant current circuit is used for limiting the current of an input external power supply and then connecting the current to a power supply selection loop, the input end of the power supply selection loop is respectively provided with different power supplies by a hard disk power supply loop and a self-destroying negative pressure constant current circuit, the output end of the power supply selection loop is connected to an SSD hard disk, a self-destroying starting circuit is additionally connected to the power supply selection loop, the power supply selection loop is powered by the hard disk when in normal use, an MOS tube in the self-destroying starting circuit is driven to be switched on and off when in self-destroying starting, the self-destroying negative pressure constant current circuit generates negative voltage, the power supply of the SSD hard disk is changed from original +5V to-6V, thereby directly burning storage particles in the SSD hard disk, the self-destroying starting circuit is provided with a self-destroying switch, the self-destroying starting is controlled by adopting a double mirror circuit, the double mirror circuit is provided with an MOS tube to prevent power down triggering, the double mirror circuit is also provided with a triode to prevent power up triggering, therefore, the initial state of the self-destruction starting circuit is limited, the data protection self-destruction system is ensured to be stabilized in a non-self-destruction state when the power is turned on and off, a chip U1 is arranged in the self-destruction starting circuit and is used as a power management chip, the model of the chip U1 is LTC4352IMS, the number 1 pin and the number 3 pin of the chip U1 are connected and then are connected to a +5V power supply, a capacitor C2 is connected between the number 2 pin and the number 7 pin of the chip U1, the number 4 pin of the chip U1 is connected with a resistor R9 in series and then is respectively connected to the number 7 pin and the number 9 pin of the chip U1, the number 5 pin of the chip U1 is connected with a resistor R7 and then is used as an enabling end of the self-destruction circuit, the number 8 pin of the chip U1 is connected with a +5V power supply and then is connected with a power supply selection circuit, the number 10 pin and the number 12 pin of the chip U1 is respectively connected with two ends of the capacitor C1, the number 11 pin of the chip U1 is respectively connected with the number 4 pin of the MOS tube Q3 and the number 4 pin of the MOS tube Q4, the MOS tube Q3 has pins 1, 2 and 3 connected to pins 1, 2 and 3 of the MOS tube Q4, the MOS tube Q3 has pins 5, 6, 7, 8 and 9 connected to +5V power supply, the MOS tube Q4 has pins 5, 6, 7, 8 and 9 connected to +5V power supply, the +5V power supply has one end connected to the MOS tube Q5 pin, the MOS tube has pins 5, 6, 7, 8 and 9 connected in parallel, the MOS tube Q5 has pins 1, 2 and 3 connected to pins 1, 2 and 3 of the MOS tube Q6, the MOS tube Q6 has pins 5, 6, 7, 8 and 9 connected to-6V power supply, the MOS tube Q5 has pins 4 connected to the MOS tube Q6 and serial resistor R5, the chip U1 has the No. 4 pin with one end connected to the No. 3 pin of the MOS transistor Q7, the No. 3 pin of the MOS transistor Q7 connected serially to the resistor R10 and then to GND, the No. 1 pin of the MOS transistor Q7 connected serially to the resistor R8 and then to GND, the No. 2 pin of the MOS transistor Q7 connected to-6V power source, the collector of the transistor Q11 connected to the No. 1 pin of the MOS transistor Q7, the base of the transistor Q11 connected to the resistor R17 and then to the burn_1 end, the emitter of the transistor Q11 connected to the power source-6V, the resistor R18 connected in series between the emitter and the base of the transistor Q11, the collector of the transistor Q12 connected to the No. 1 pin of the MOS transistor Q7, the base of the transistor Q12 connected to the resistor R19 and then to the burn_2 end, the emitter of the transistor Q12 connected to the ground, the resistor R20 connected in series between the emitter and the base of the transistor Q11, the double mirror circuit driven by the self-destruction switch SW6 and the No. 4 signal end DIS_1 end of the self-destruction switch SW6, the No. 2 end of the self-destruction switch SW6 is connected with the DIS_SIG2 signal end, the DIS_SIG1 signal end is connected with a resistor R24 and then connected to a resistor R14, the other end of the resistor R14 is connected with the No. 1 pin of the MOS tube Q8, the No. 1 pin of the MOS tube Q8 is additionally extracted and connected with a-6V power supply after being connected with a resistor R15 in series, the No. 2 pin of the MOS tube Q8 is connected with a-6V power supply after being connected with a capacitor C4 in series, one end of the MOS tube Q8 is extracted and connected with a capacitor C3 after being connected with a resistor R11, the base electrode serial resistor R12 of the triode Q9 is connected with the No. 3 pin of the MOS tube Q8, the collector electrode of the triode Q9 is connected with the collector electrode of the triode Q10, the emitter electrode serial resistor R13 of the triode Q10 is connected with the-6V power supply, the base electrode serial resistor R16 of the triode Q10 is connected with the-6V power supply, the collector electrode of the triode Q10 is connected with the-6V power supply after being connected with the serial capacitor C5, the DIS_SIG2 signal end is sequentially connected with a resistor R28 and a resistor R25 in series and then is connected to a No. 1 pin of a MOS transistor Q13, one end of the No. 1 pin of the MOS transistor Q13 is additionally extracted and connected with a power supply-6V after being connected with a resistor R27 in series, the No. 2 pin of the MOS transistor Q13 is connected with a power supply-6V after being connected with a resistor R22 in series, the No. 3 pin of the MOS transistor Q13 is additionally extracted and connected with a capacitor C7 in series and then is connected with a-6V power supply, the collector of the transistor Q14 is connected with the collector of a transistor Q15, the emitters of the transistor Q14 are connected with a power supply-6V, a resistor R26 is connected at both ends of the resistor R22 and the emitter of the transistor Q14 in parallel, the base of the transistor Q15 is connected with a connecting point between the capacitor C6 and the resistor R26 after being connected with the base of the resistor R23, the emitter of the transistor Q15 is connected with the power supply-6V after being extracted and the base of the No. 3 pin of the MOS transistor Q13 is connected with the base of the transistor Q24 after being extracted and connected with the base of the transistor Q50, the emitter of the triode Q24 is connected with a-6V power supply, the collector of the triode Q24 is connected with a resistor R51 and a resistor R52 in series, then is connected with a power supply +5V, one end of the resistor R53 is extracted between the resistor R51 and the resistor R52 in series and then is connected with a No. 1 pin of the MOS tube Q25, a No. 2 pin of the MOS tube Q25 is grounded, a No. 3 pin of the MOS tube Q25 is connected with a power supply +5V, a No. 1 pin of the MOS tube Q23 is connected with a sburn_star signal end after a No. 1 pin of the MOS tube Q23 is connected with a base of the triode Q22, a No. 3 pin of the MOS tube Q23 is connected with a power supply +5V after a No. 3 pin of the resistor R55 is connected with a power supply-6V, the emitter of the triode Q22 is connected with a power supply-6V after a base of the triode Q48 is connected with a collector of the triode Q22, and a collector of the triode Q15 is connected with one end of the resistor R5 in parallel, MOS tube Q8 and MOS tube Q13 are used for preventing the power down trigger, MOS tube Q10 and MOS tube Q15 are used for preventing the power up trigger, when DIS_SIG1 end and DIS_SIG2 end from the switch are connected to the ground, a signal for closing MOS tube Q3 and MOS tube Q4 is generated for pin No. 4 of chip U1, and meanwhile, a signal for enabling MOS tube Q5 and MOS tube Q6 to be conducted is output by pin No. 5 of chip U1.

2. The data protection self-destruction system as claimed in claim 1, wherein the self-destruction negative-voltage constant-current circuit is controlled by a chip U3 as voltage regulation, the type of the chip U3 is LT8710, a No. 1 pin of the chip U3 is serially connected with a resistor R38 and then connected with a power supply of-6V, a No. 2 pin of the chip U3 is grounded through a capacitor C42, a resistor R42 and a capacitor C43 are parallelly connected at two ends of the capacitor C42, a No. 3 pin of the chip U3 is serially connected with a capacitor C45 and then grounded, a No. 5 pin of the chip U3 is serially connected with a capacitor C44 and then grounded, a No. 7 pin of the chip U3 is serially connected with a resistor R33 and then connected with a gate of a MOS tube Q18, a voltage stabilizing diode D1 is parallelly connected at two ends of the resistor R33 and then grounded, a No. 10 pin of the chip U3 is serially connected with a gate of the Q18 and then grounded after a source serial resistor R34 of the MOS tube Q18, a drain L1 of the MOS tube Q18 is serially connected with a power supply of-6V, the capacitor C30, the capacitor C31, the polar capacitor CT1, the capacitor C32 and the capacitor C33 are respectively connected in parallel between the 6V power supply and the ground, the 11-number pin of the chip U3 is connected with the 4-number pin of the MOS tube Q17, the 12-number pin of the chip U3 is connected with the capacitor C41 and then grounded and connected with the 17-number pin and the 8-number pin, the 13-number pin of the chip U3 is connected with the +12V power supply and sequentially connected with the resistor R37 and the resistor R39 in series and then grounded, the 14-number pin of the chip U3 is connected with the 1-number pin, the 2-number pin and the 3-number pin of the MOS tube Q17 in series, the 5-number pin, the 6-number pin, the 7-number pin and the 8-number pin of the MOS tube Q17 are respectively connected with the capacitor C29 in series, the two ends of the capacitor C29 are connected with the capacitor C28, the 12-number pin of the capacitor C28 is connected with the +12V power supply, the 15-number pin of the chip U3 is connected with the 1-number pin of the MOS tube Q17, the 2-number pin of the 3 is connected with the 3-number pin of the MOS tube Q19, and the resistor R39 is connected in series and then grounded, the number 1 pin of the MOS tube Q19 is sequentially connected with the resistor R40 and the resistor R35 in series and then is connected with +12V power supply, the number 2 pin of the MOS tube Q19 is grounded, the number 3 pin of the MOS tube is connected with the number 16 pin of the chip U3, the number 18 pin of the chip U3 is connected with the resistor R41 in series and then grounded, the +12V power supply is respectively connected in parallel between the +1V power supply pair ground, the capacitor C36, the capacitor C37, the capacitor C38 and the capacitor C39, the number 3 pin of the MOS tube Q19 is connected with the number 8 pin of the chip U2 in series after one end is extracted from the resistor R36, the chip U2 adopts a chip with the model number 4356, the number 1 pin of the chip U2 is connected with the resistor R31 and then grounded, the number 2 pin of the chip U2 is additionally extracted from one end of the resistor R29 and then is connected with +12V power supply, the number 2 pin of the chip U2 is connected with the +12V power supply, the number 3 pin of the chip U16 is connected with the number 1 pin of the MOS tube Q16, the number 3 pin of the MOS tube Q16 is connected with the +12V power supply, the number 4 of the chip Q16 is connected with the number 4, the chip is connected with the number 4 of the chip 12V 6, the chip is connected with the chip 2, the number 4 is connected with the chip 2, the chip is connected with the number 4, and the chip is connected with the chip 2, and the chip is connected with the chip, and the chip.

3. The self-destruction system for data protection as claimed in claim 1, wherein the power supply selection circuit is switched by a MOS transistor Q21, a No. 1 pin of the MOS transistor Q21 is connected with a +5V power supply after being connected with a resistor R46 in series, a No. 2 pin of the MOS transistor Q21 is grounded, a No. 3 pin of the MOS transistor Q21 is connected with a +12V power supply after being connected with a resistor R44 in series, a No. 3 pin of the MOS transistor Q21 is connected with a base electrode of a triode Q20, an emitter electrode of the triode Q20 is grounded, a resistor R45 is connected between the emitter electrode and a collector electrode of the triode Q20 in series and then grounded, and a collector electrode of the triode Q20 is connected with a resistor R43 and then connected with a +5V power supply.