CN106357577A - Circuit and method for demodulating binary frequency shift keying signals - Google Patents
Circuit and method for demodulating binary frequency shift keying signals Download PDFInfo
- Publication number
- CN106357577A CN106357577A CN201510415316.1A CN201510415316A CN106357577A CN 106357577 A CN106357577 A CN 106357577A CN 201510415316 A CN201510415316 A CN 201510415316A CN 106357577 A CN106357577 A CN 106357577A
- Authority
- CN
- China
- Prior art keywords
- road
- signal
- channel
- frequency shift
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/12—Modulator circuits; Transmitter circuits
Abstract
The invention discloses a circuit for demodulating binary frequency shift keying signals. The circuit comprises an I-channel delay circuit, a Q-channel delay circuit, an I-channel multiplier, a Q-channel multiplier, a subtracter and a decision circuit. Inputted I-channel signals and Q-channel signals are respectively delayed by the identical time T by the I-channel delay circuit and the Q-channel delay circuit to obtain I-channel delayed signals and Q-channel delayed signals; the T is larger than 0; the I-channel delayed signals are multiplied by the Q-channel signals by the I-channel multiplier to obtain I-channel multiplication results; the Q-channel delayed signals are multiplied by the I-channel signals by the corresponding multiplier to obtain Q-channel multiplication results; the I-channel multiplication results are subtracted from Q-channel multiplication results by the subtracter to obtain subtraction results; whether the subtraction results are larger than 0 or not is judged by the decision circuit to obtain demodulation results. The invention further discloses a method for demodulating the binary frequency shift keying signals. The circuit and the method have the advantages of simple structure and easiness in implementation.
Description
Technical field
The present invention relates to the demodulator circuit in a kind of communication system, more particularly to a kind of binary frequency shift
The demodulator circuit of keying signal.The invention still further relates to a kind of demodulation method of binary frequency shift keying signal.
Background technology
Binary frequency shift keying signal (2-fsk), is widely used in bluetooth, hyperfrequency rfid (radio frequency
Identification) etc. in field.
Binary frequency shift keying modulated signal can be expressed as orthogonal signalling:
I=cos [2*pi* ∑ (s*fs*t)] and q=sin [2*pi* ∑ (s*fs*t)].
Wherein: pi is pi, fs is modulating frequency, and t is the sampling interval, and s is data message,
Typically take ± 1, " * " represents multiplication sign.2*pi* ∑ (s*fs*t) represents current phase theta.Existing
The method that 2-fsk decoding adopts is the phase place first obtaining modulated signal, then recovers data again from phase place
Information.
Content of the invention
The technical problem to be solved in the present invention is to provide a kind of demodulation electricity of binary frequency shift keying signal
Road, its structure is simple, it is easy to accomplish；For this reason, the present invention also provides a kind of binary frequency shift keying
The demodulation method of signal.
For solving above-mentioned technical problem, the demodulator circuit of the binary frequency shift keying signal of the present invention, bag
Include: an i road delay circuit, a q road delay circuit, an i road multiplier, a q road multiplier,
One subtractor and a decision circuit；
Described i road delay circuit and the q road delay circuit i road signal to input and q road signal respectively
Postpone identical time t, obtain i road postpones signal and q road postpones signal；T is more than 0；
Described i road multiplier, by i road postpones signal and q road signal multiplication, obtains i road multiplication result；
Described multiplier, by q road postpones signal and i road signal multiplication, obtains q road multiplication result；
Described subtractor subtracts q road multiplication result with i road multiplication result, obtains subtraction result；
Described decision circuit passes through to judge whether subtraction result obtains demodulation result more than 0；
Wherein, i road signal is that the two-way orthogonal signalling that the binary frequency shift keying in base band is modulated are corresponding remaining
The signal of string phase place, q road signal is the signal of the corresponding sinusoidal phase of two-way orthogonal signalling.
The demodulation method of described binary frequency shift keying signal, adopts the following technical scheme that realization:
The two-way orthogonal signalling of the binary frequency shift keying modulation in the base band of input are sampled, its
In, in two-way orthogonal signalling, the signal of corresponding cosine phase is referred to as i road signal, corresponding sinusoidal phase
Signal is referred to as q road signal；
With the current sample values of i road and q road two paths of signals respective with this two paths of signals caching before
One sampled value enters row operation, is then compared with threshold value, obtains demodulation result.
The invention has the beneficial effects as follows: the demodulation method of existing binary frequency shift keying signal, typically
It is by amplitude-phase change-over circuit, first i, the baseband signal of q two-way transforms to phase field, then
Phase signal calculus of differences is realized demodulate.This demodulation method implements more complicated.
Demodulator circuit structure using the present invention is simpler, the demodulation method control process letter of the present invention
Just, it is easy to accomplish, it is more beneficial for reduces cost, improve efficiency.
Brief description
The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings:
Accompanying drawing is the demodulator circuit theory diagram of described binary frequency shift keying signal.
Specific embodiment
In conjunction with shown in accompanying drawing, the demodulator circuit of described binary frequency shift keying signal, comprising: an i road
Delay circuit, a q road delay circuit, an i road multiplier, a q road multiplier, a subtractor and
One decision circuit.
The demodulator circuit of described binary frequency shift keying signal, it inputs as the binary frequency shift in base band
The two-way orthogonal signalling of keying modulation, it is output as demodulation result.Corresponding cosine in two-way orthogonal signalling
The signal of phase place is i road signal, and in two-way orthogonal signalling, the signal of corresponding sinusoidal phase is q road signal.
The input of described i road delay circuit is i road signal, its output i road postpones signal.Described q
The input of road delay circuit is q road signal, its output q road postpones signal.Described i road delay circuit
With q road delay circuit to the i road signal inputting and q road signal delay identical time t.
One input of described i road multiplier is connected with the outfan of described i road delay circuit, defeated
Enter i road postpones signal, another input input q road signal, by i road postpones signal and q road signal
It is multiplied, obtain i road multiplication result.
One input of described q road multiplier is connected with the outfan of described q road delay circuit, defeated
Enter q road postpones signal, another input input i road signal, by q road postpones signal and i road signal
It is multiplied, obtain q road multiplication result.
Described subtractor is connected with i road multiplier and q road multiplier.Subtract q with i road multiplication result
Road multiplication result, obtains subtraction result.
Described decision circuit is connected with subtractor, by judging whether subtraction result is solved more than 0
Adjust result.
The demodulator circuit operation principle of described binary frequency shift keying signal is as follows:
In below describing, pi represents pi, and fs represents modulating frequency, and t represents sampling interval, s table
Show data message, typically take ± 1, θ to represent current phase place.
Then, current i road signal is expressed as i=cos θ, then the i road letter in a upper sampling period
Number can be expressed as i=cos (θ -2*pi*s*fs*t).
Equally, q road signal is expressed as q=sin θ, then the q road signal in a upper sampling period can
To be expressed as q=sin (θ -2*pi*s*fs*t).
So the signal after the delay of i road and q road signal multiplication, obtain cos (θ -2*pi*s*fs*t) *
sinθ；Q road postpones signal is multiplied with i road, obtains sin (θ -2*pi*s*fs*t) * cos θ.
Then subtract each other, according to triangle change formula obtain cos (θ -2*pi*s*fs*t) * sin θ -
Sin (θ -2*pi*s*fs*t) * cos θ=sin (2*pi*s*fs*t).
When fs*t is less than 1/2, the symbol of sin (2*pi*s*fs*t) is identical with s.
Then pass through whether decision circuit judged result obtains demodulation result s more than 0.
Above by specific embodiment, the present invention is described in detail, but these have not been constituted
Limitation of the present invention.Without departing from the principles of the present invention, those skilled in the art also may be used
Make many deformation and improve, these also should be regarded as protection scope of the present invention.
Claims (2)
1. a kind of demodulator circuit of binary frequency shift keying signal is it is characterised in that include: an i road
Delay circuit, a q road delay circuit, an i road multiplier, a q road multiplier, a subtractor and
One decision circuit；
Described i road delay circuit and the q road delay circuit i road signal to input and q road signal respectively
Postpone identical time t, obtain i road postpones signal and q road postpones signal；T is more than 0；
Described i road multiplier, by i road postpones signal and q road signal multiplication, obtains i road multiplication result；
Described multiplier, by q road postpones signal and i road signal multiplication, obtains q road multiplication result；
Described subtractor subtracts q road multiplication result with i road multiplication result, obtains subtraction result；
Described decision circuit passes through to judge whether subtraction result obtains demodulation result more than 0；
Wherein, i road signal is that the two-way orthogonal signalling that the binary frequency shift keying in base band is modulated are corresponding remaining
The signal of string phase place, q road signal is the signal of the corresponding sinusoidal phase of two-way orthogonal signalling.
2. a kind of demodulation method of binary frequency shift keying signal it is characterised in that:
The two-way orthogonal signalling of the binary frequency shift keying modulation in the base band of input are sampled, its
In, in two-way orthogonal signalling, the signal of corresponding cosine phase is referred to as i road signal, corresponding sinusoidal phase
Signal is referred to as q road signal；
With the current sample values of i road and q road two paths of signals respective with this two paths of signals caching before
One sampled value enters row operation, is then compared with threshold value, obtains demodulation result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510415316.1A CN106357577A (en) | 2015-07-15 | 2015-07-15 | Circuit and method for demodulating binary frequency shift keying signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510415316.1A CN106357577A (en) | 2015-07-15 | 2015-07-15 | Circuit and method for demodulating binary frequency shift keying signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106357577A true CN106357577A (en) | 2017-01-25 |
Family
ID=57842343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510415316.1A Pending CN106357577A (en) | 2015-07-15 | 2015-07-15 | Circuit and method for demodulating binary frequency shift keying signals |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106357577A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302508A (en) * | 2017-06-14 | 2017-10-27 | 上海电机学院 | A kind of 2FSK signals are produced and detection circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4423519A (en) * | 1982-01-20 | 1983-12-27 | Sperry Corporation | Apparatus and method for detecting the onset of a frequency shift keyed signal |
| JPH01222505A (en) * | 1988-03-01 | 1989-09-05 | Sharp Corp | Demodulation circuit |
| US6847255B2 (en) * | 2001-06-01 | 2005-01-25 | Broadband Innovations, Inc. | Zero IF complex quadrature frequency discriminator and FM demodulator |
| CN1866942A (en) * | 2005-05-16 | 2006-11-22 | 冲电气工业株式会社 | Demodulation method and demodulation circuit |
| CN102594404A (en) * | 2011-01-07 | 2012-07-18 | 上海海尔集成电路有限公司 | Demodulator circuit for carrier signal of power line and microcontroller |
-
2015
- 2015-07-15 CN CN201510415316.1A patent/CN106357577A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4423519A (en) * | 1982-01-20 | 1983-12-27 | Sperry Corporation | Apparatus and method for detecting the onset of a frequency shift keyed signal |
| JPH01222505A (en) * | 1988-03-01 | 1989-09-05 | Sharp Corp | Demodulation circuit |
| US6847255B2 (en) * | 2001-06-01 | 2005-01-25 | Broadband Innovations, Inc. | Zero IF complex quadrature frequency discriminator and FM demodulator |
| CN1866942A (en) * | 2005-05-16 | 2006-11-22 | 冲电气工业株式会社 | Demodulation method and demodulation circuit |
| CN102594404A (en) * | 2011-01-07 | 2012-07-18 | 上海海尔集成电路有限公司 | Demodulator circuit for carrier signal of power line and microcontroller |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302508A (en) * | 2017-06-14 | 2017-10-27 | 上海电机学院 | A kind of 2FSK signals are produced and detection circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111711589B (en) | Continuous phase modulation and demodulation method based on elliptical spherical wave signal | |
| CN106856463A (en) | MSK/GMSK coherent demodulation processing systems | |
| CN110300079B (en) | MSK signal coherent demodulation method and system | |
| US20170187562A1 (en) | Bluetooth low energy frequency offset and modulation index estimation | |
| CN106027432B (en) | A kind of CPFSK bit rate estimation method based on signal transient frequency-portions correlation function | |
| CN107493249B (en) | A kind of ASK demodulation circuit based on analog switch | |
| WO2016032191A2 (en) | Ultra low power wideband asynchronous binary phase shift keying demodulation circuit using first order sideband filters aligned at zero degree phase | |
| CN105306397A (en) | DQPSK intermediate frequency differential demodulation method | |
| CN105516036A (en) | CPFSK modulation identification method | |
| CN102014092B (en) | Cascade-mode-based quaternary minimum-shift keying ( MSK) modulation method and device | |
| KR20180081859A (en) | Low Power Wideband Pre-Emphasis Amplitude Shift Keying(PEASK) Comunication System | |
| CN106357577A (en) | Circuit and method for demodulating binary frequency shift keying signals | |
| US20150263873A1 (en) | Synchronous demodulator electronic circuit for phase modulation signals | |
| CN105811590B (en) | Amplitude-modulated signal demodulation and decoded method are realized in wireless charging device | |
| CN106487727A (en) | A kind of full duplex self-interference removing method and full duplex system | |
| CN103596260A (en) | Time slot synchronization method and system of multicarrier GSM system | |
| CN104333393A (en) | Receiving terminal and receiving terminal method for air-ground narrow-band communication system of unmanned aerial vehicle | |
| CN105099978B (en) | A method of for removing phase-modulated information | |
| Galvão et al. | Bandwidth efficient gaussian minimum frequency-shift keying approach for software defined radio | |
| CN104507106A (en) | Identification method for 8PSK (8 Phase Shift Keying) signal and PI/4-DQPSK (PI/4-Differential Quadrature Phase Shift Keying) signal | |
| CN105119855B (en) | A kind of modulation and demodulation method and device | |
| CN102037479B (en) | Rfid transponder | |
| CN103338173A (en) | A method and an apparatus for recovering code elements | |
| CN108199996A (en) | Independent sideband modulation signal demodulating method based on FPGA | |
| CN109067679B (en) | DSB demodulation method for offsetting frequency offset |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170125 |
|
| WD01 | Invention patent application deemed withdrawn after publication |