CN106356381A - Array substrate as well as preparation method and display panel thereof - Google Patents
Array substrate as well as preparation method and display panel thereof Download PDFInfo
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- CN106356381A CN106356381A CN201611015730.4A CN201611015730A CN106356381A CN 106356381 A CN106356381 A CN 106356381A CN 201611015730 A CN201611015730 A CN 201611015730A CN 106356381 A CN106356381 A CN 106356381A
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- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate as well as a preparation method and a display panel thereof and relates to the field of display technology, wherein the load on a data line in a display device can be reduced so as to lower the power consumption of the display device. The array substrate comprises a display area and a virtual display area arranged on the periphery of the display area, wherein the display area comprises a sub-pixel; the virtual display area comprises a virtual sub-pixel; the sub-pixel and the virtual sub-pixel both comprise a thin film transistor and a first transparent electrode electrically connected with the drain of the thin film transistor; the source of the thin film transistor in the sub-pixel is connected with the data line; and the source of the thin film transistor in the virtual sub-pixel is disconnected from the data line.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
At present, for example, a mobile phone or some other mobile devices occupy a large proportion of a display screen, so that standby time is too short, frequent charging is required, and certain trouble is brought, so that it is very important to reduce logic power consumption of the display screen.
In the display screen, because there are many data lines, taking an UHD display screen with a resolution of 3840 × 2160 as an example, the UHD display screen has 3840 × 3 data lines in total, and when the display screen normally works, the data lines are always in a scanning state, so that reducing the load on the data lines can greatly reduce the power consumption of the display screen.
Disclosure of Invention
Embodiments of the present invention provide an array substrate, a method for manufacturing the same, and a display panel, which can reduce a load on a data line in a display device, thereby reducing power consumption of the display device.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, an array substrate is provided, which includes a display area and a virtual display area disposed around the display area; the display area comprises sub-pixels, and the virtual display area comprises virtual sub-pixels; the sub-pixels and the dummy sub-pixels each include a thin film transistor, a first transparent electrode electrically connected to a drain of the thin film transistor; the source electrode of the thin film transistor in the sub-pixel is connected with a data line; the source electrode of the thin film transistor in the virtual sub-pixel is disconnected from the data line.
Preferably, the gate electrode of the thin film transistor in the sub-pixel is connected to the gate line; the grid electrode of the thin film transistor in the virtual sub-pixel is electrically connected with a first common electrode wire; wherein the first transparent electrode in the dummy sub-pixel is electrically connected to the first common electrode line.
Further preferably, the sub-pixels and the virtual sub-pixels further include second transparent electrodes, respectively; the second transparent electrode is electrically connected with a second common electrode wire; wherein the second common electrode line is electrically connected with the first common electrode line.
Preferably, the first transparent electrode in the virtual sub-pixel is connected to the first common electrode line through a via hole.
Preferably, the first transparent electrode in the virtual sub-pixel and the second transparent electrode in the virtual sub-pixel are connected through a via hole; or, the first transparent electrode in the virtual sub-pixel is connected with the second common electrode line through a via hole.
In a second aspect, a display panel is provided, which includes the array substrate.
Preferably, the display panel further comprises a pair of cell substrates; the second transparent electrode is disposed in the pair of cassette substrates or the array substrate.
In a third aspect, a method for manufacturing an array substrate is provided, including: synchronously forming sub-pixels in a display area, and forming virtual sub-pixels in a virtual display area at the periphery of the display area; the sub-pixels and the dummy sub-pixels each include a thin film transistor, a first transparent electrode electrically connected to a drain of the thin film transistor; the source electrode of the thin film transistor in the sub-pixel is connected with a data line; the source electrode of the thin film transistor in the virtual sub-pixel is disconnected from the data line.
Preferably, the gate electrode of the thin film transistor in the sub-pixel is connected to the gate line; the grid electrode of the thin film transistor in the virtual sub-pixel is electrically connected with a first common electrode wire; the first transparent electrode in the virtual sub-pixel is connected with the first common electrode line through a via hole.
Preferably, the sub-pixels and the virtual sub-pixels further include second transparent electrodes, respectively; the second transparent electrode is electrically connected with a second common electrode wire; the first transparent electrode in the virtual sub-pixel and the second transparent electrode in the virtual sub-pixel are connected through a through hole; or, the first transparent electrode in the virtual sub-pixel is connected with the second common electrode line through a via hole.
The embodiment of the invention provides an array substrate, a preparation method thereof and a display panel, wherein the problem of poor etching uniformity of the edge of the array substrate can be solved by arranging a virtual display area at the periphery of a display area of the array substrate. On the basis, the thin film transistor in the virtual sub-pixel is disconnected from the data line, so that the generation of coupling capacitance between the data line and the thin film transistor in the virtual sub-pixel can be avoided, the load of the data line is reduced, and further, when the array substrate is used for a display device, the power consumption of the display device can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a first schematic top view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic view of a load on a data line when the data line is connected to a thin film transistor in a dummy sub-pixel according to an embodiment of the present invention;
fig. 3 is a schematic view of a load on a data line when the data line is disconnected from a thin film transistor in a dummy sub-pixel according to an embodiment of the present invention;
fig. 4 is a second schematic top view of an array substrate according to an embodiment of the present invention;
fig. 5(a) is a schematic top view of an array substrate according to an embodiment of the present invention;
FIG. 5(b) is a schematic cross-sectional view along AA' in FIG. 5 (a);
fig. 6(a) is a first schematic top view of a virtual display area of an array substrate according to an embodiment of the present invention;
FIG. 6(b) is a schematic sectional view taken along direction BB' in FIG. 6 (a);
fig. 7(a) is a schematic top view illustrating a virtual display area of an array substrate according to an embodiment of the present invention;
FIG. 7(b) is a schematic sectional view taken along the direction CC' in FIG. 7 (a).
Description of the drawings:
01-a display area; 02-virtual display area; 10-sub-pixel; 20-virtual sub-pixels; 30-a thin film transistor; 31-source electrode; 32-a drain electrode; 41-a first transparent electrode; 42-a second transparent electrode; 50-a data line; 61-a gate line; 62-a first common electrode line; 63-a second common electrode line; 70-a substrate; 80-a gate insulating layer; 90-passivation layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an array substrate, as shown in fig. 1, including a display area 01 and a virtual display area 02 disposed around the display area 01; the display area 01 includes sub-pixels 10, and the virtual display area 02 includes virtual sub-pixels 20; each of the sub-pixels 10 and the dummy sub-pixel 20 includes a thin film transistor 30, a first transparent electrode 41 electrically connected to a drain electrode 32 of the thin film transistor 30; wherein, the source 31 of the thin film transistor 30 in the sub-pixel 10 is connected to the data line 50; the source electrode 31 of the thin film transistor 30 located in the dummy sub-pixel 20 is disconnected from the data line 50.
If the source 31 of the tft 30 in the dummy sub-pixel 20 is connected to the data line 50, the load on the data line 50 for any data line 50 is as shown in fig. 2. The source 31 of the thin film transistor 30 in the dummy sub-pixel 20 is disconnected from the data line 50 according to the embodiment of the present invention, and the load on the data line 50 is as shown in fig. 3. As can be seen from comparing fig. 2 and 3, the source 31 of the thin film transistor 30 in the dummy sub-pixel 20 is disconnected from the data line 50, so that there is no coupling capacitance Cdc between the data line 50 and the thin film transistor 30 in the dummy sub-pixel 20, thereby reducing the load on the data line 50.
First, the virtual display area 02 may be located at least on one side of one of the edges of the display area 01, and may be specifically set according to the actual situation.
Second, the source 31 and the drain 32 of the thin film transistor 30 are symmetrical, so there is no difference between the source 31 and the drain 32. In the embodiment of the present invention, to distinguish two electrodes of the thin film transistor 30 except for the gate electrode, one of the two electrodes is referred to as a source electrode 31, and the other electrode is referred to as a drain electrode 32.
In the present embodiment, the type of the thin film transistor is not limited, and the thin film transistor may be an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor, an oxide semiconductor thin film transistor, an organic thin film transistor, or the like.
Third, when the array substrate is an array substrate in a liquid crystal display, the first transparent electrode 41 is a pixel electrode. Further, the array substrate may further include a common electrode. Of course, the common electrode may be disposed on the array substrate, and may also be disposed on a counter substrate of the liquid crystal display.
When the array substrate is an array substrate in an organic electroluminescent diode display, the first transparent electrode 41 is an anode, and based on this, the array substrate further includes a cathode, and an organic material functional layer located between the anode and the cathode.
The embodiment of the invention provides an array substrate, and the problem of poor etching uniformity of the edge of the array substrate can be solved by arranging a virtual display area 02 at the periphery of a display area 01 of the array substrate. On this basis, by disconnecting the thin film transistor 30 in the dummy sub-pixel 20 from the data line 50, a coupling capacitance between the data line 50 and the thin film transistor 30 in the dummy sub-pixel 20 can be avoided, so that the load of the data line 50 is reduced, and further, when the array substrate is used for a display device, the power consumption of the display device can be reduced.
Preferably, the structure of the dummy sub-pixel 20 is identical to that of the sub-pixel 10, and only the source 31 of the thin film transistor 30 in the dummy sub-pixel 20 is disconnected from the data line 50. Thus, the problem of poor etching uniformity of the edge of the array substrate can be solved when each layer of the sub-pixel 10 is formed.
Preferably, as shown in fig. 4, the gate electrode of the thin film transistor 30 located in the sub-pixel 10 is connected to the gate line 61; the gate of the thin film transistor 30 located in the dummy sub-pixel 20 is electrically connected to the first common electrode line 62; wherein the first transparent electrode 41 positioned in the dummy sub-pixel 20 is electrically connected to the first common electrode line 62.
Here, the gate electrode of the thin film transistor 30 in the sub-pixel 10 is connected to the gate line 61, and when a driving signal is applied to the gate line 61, the thin film transistor 30 in the sub-pixel 10 can be controlled to be turned on, so that the array substrate normally operates.
The first common electrode line 62 corresponds to a gate line driving the thin film transistor 30 in the dummy sub-pixel 20. That is, when the voltage on the first common electrode line 62 is greater than the turn-on voltage of the thin film transistor 30, the thin film transistor 30 located in the dummy sub-pixel 20 is always in the on state.
First, as shown in fig. 4, the gate of the thin film transistor 30 in the sub-pixel 10 may be implemented by using a portion of the gate line 61; the gate of the thin film transistor 30 located in the dummy sub-pixel 20 may function as a portion using the first common electrode line 62.
Of course, the thin film transistor 30 may be provided with a gate electrode separately, the gate electrode of the thin film transistor 30 located in the sub-pixel 10 is connected to the gate line 61, and the gate electrode of the thin film transistor 30 located in the dummy sub-pixel 20 is connected to the first common electrode line 62.
Second, the connection manner of the first transparent electrode 41 and the first common electrode line 62 is not specifically limited, as long as the first transparent electrode 41 and the first common electrode line 62 have the same potential.
In the embodiment of the present invention, the gate of the thin film transistor 30 in the virtual sub-pixel 20 and the first transparent electrode 41 are both electrically connected to the first common electrode line 62, so that the gate and the first transparent electrode 41 have the same potential, and further, the source 31, the drain 32 and the gate of the thin film transistor 30 in the virtual sub-pixel 20 have the same potential, thereby avoiding the generation of static electricity.
Further preferably, as shown in fig. 5(a), the sub-pixel 10 and the dummy sub-pixel 20 further include a second transparent electrode 42; the second transparent electrode 42 is electrically connected to the second common electrode line 63; wherein the second common electrode line 63 is electrically connected to the first common electrode line 62. When the array substrate is an array substrate in a liquid crystal display, the second transparent electrodes 42 in the sub-pixels 10 and the dummy sub-pixels 20 are common electrodes, and the first transparent electrodes 41 are pixel electrodes. Among them, the second common electrode line 63 connected to the second transparent electrode 42 may reduce the resistance of the second transparent electrode 42.
In the embodiment of the present invention, the second common electrode line 63 (i.e., the common electrode) is disposed on the array substrate, so that the viewing angle of the display panel in the liquid crystal display can be increased, and the power consumption can be reduced. The second common electrode line 63 is electrically connected to the first common electrode line 62, so that the first transparent electrode 41 and the second transparent electrode 42 in the virtual sub-pixel 20 have the same potential, thereby avoiding light leakage of the virtual sub-pixel 20.
Further preferably, the first common electrode line 62, the second common electrode line 63, the gate line 61, and the second common electrode line 63 are formed by a single patterning process.
Based on the above, the first transparent electrode 41 in the dummy sub-pixel 20 and the first common electrode line 62 can be electrically connected in several ways:
first, as shown in fig. 4 and fig. 5(a) -5 (b), the first transparent electrode 41 located in the dummy sub-pixel 20 is connected to the first common electrode line 62 through a via hole.
That is, the first transparent electrode 41 in the dummy sub-pixel 20 is extended above the first common electrode line 62, so that the first transparent electrode 41 in the dummy sub-pixel 20 is connected to the first common electrode line 62 through the via hole.
Here, as shown in fig. 5(b), the first transparent electrode 41 may be connected to the first common electrode line 62 through a via hole disposed on the passivation layer 90 and the gate insulating layer 80.
In the second mode, as shown in fig. 6(a) and 6(b), the first transparent electrode 41 in the dummy sub-pixel 20 and the second transparent electrode 42 in the dummy sub-pixel 20 are connected through a via hole.
Since the second transparent electrode 42 is electrically connected to the second common electrode line 63, and the second common electrode line 63 is electrically connected to the first common electrode line 62, after the first transparent electrode 41 in the virtual sub-pixel 20 and the second transparent electrode 42 in the virtual sub-pixel 20 are connected through the via hole, the first transparent electrode 41 in the virtual sub-pixel 20 and the first common electrode line 62 can be electrically connected.
Here, as shown in fig. 6(b), when the second transparent electrode 42 is formed simultaneously with the first common electrode line 62, the second common electrode line 63, the gate line 61, and the like, and is disposed adjacent to the substrate 70, the first transparent electrode 41 may be connected to the second transparent electrode 42 through a via hole disposed on the passivation layer 90 and the gate insulating layer 80.
In a third mode, as shown in fig. 7(a) and 7(b), the first transparent electrode 41 located in the dummy sub-pixel 20 is connected to the second common electrode line 63 through a via hole.
Since the second common electrode line 63 is electrically connected to the first common electrode line 62, the first transparent electrode 41 in the virtual sub-pixel 20 is extended above the second common electrode line 63, so that the first transparent electrode 41 in the virtual sub-pixel 20 is connected to the second common electrode line 63 through the via hole, and the first transparent electrode 41 in the virtual sub-pixel 20 is electrically connected to the first common electrode line 62.
Here, as shown in fig. 6(b), when the second transparent electrode 42 is formed simultaneously with the first common electrode line 62, the second common electrode line 63, the gate line 61, and the like, and is disposed adjacent to the substrate 70, the first transparent electrode 41 may be connected to the second common electrode line 63 through a via hole disposed on the passivation layer 90 and the gate insulating layer 80.
Based on the above-described preference, the virtual display area 02 is disposed on both sides of the display area 01 in the direction of the data line 50; the data line 50 extends from the display area 01 to the virtual display area 02.
In order to improve the problem of poor etching uniformity at each edge of the display area 01, the dummy display areas 02 are further disposed at two sides of the display area 01 along the gate line 61, and the source electrode 31 in the dummy sub-pixel 20 can be electrically connected to the second common electrode line 63, so as to avoid increasing the load of the data line 50.
An embodiment of the invention provides a display panel, which includes the array substrate.
The embodiment of the invention provides a display panel, and the problem of poor etching uniformity of the edge of an array substrate can be solved by arranging a virtual display area 02 at the periphery of a display area 01 of the array substrate. On this basis, by disconnecting the thin film transistor 30 in the dummy sub-pixel 20 from the data line 50, a coupling capacitance between the data line 50 and the thin film transistor 30 in the dummy sub-pixel 20 can be avoided, so that the load of the data line 50 is reduced, and further, when the array substrate is used for a display device, the power consumption of the display device can be reduced.
Preferably, the display panel further comprises a pair of cell substrates; the second transparent electrode 42 is disposed in the pair of cell substrates or the array substrate.
Wherein the pair of cell substrates may further include a black matrix; the color filter layer can be arranged in the box aligning substrate and also can be arranged in the array substrate.
An embodiment of the present invention provides a method for manufacturing an array substrate, as shown in fig. 1, including: synchronously forming a sub-pixel 10 in a display area 01 and forming a virtual sub-pixel 20 in a virtual display area 02 around the display area 01; each of the sub-pixels 10 and the dummy sub-pixel 20 includes a thin film transistor 30, a first transparent electrode 41 electrically connected to a drain electrode 32 of the thin film transistor 30; wherein, the source 31 of the thin film transistor 30 in the sub-pixel 10 is connected to the data line 50; the source electrode 31 of the thin film transistor 30 located in the dummy sub-pixel 20 is disconnected from the data line 50.
Preferably, the structure of the dummy sub-pixel 20 is identical to that of the sub-pixel 10, and only the source 31 of the thin film transistor 30 in the dummy sub-pixel 20 is disconnected from the data line 50.
The embodiment of the invention provides a preparation method of an array substrate, which can solve the problem of poor etching uniformity of the edge of the array substrate and avoid the increase of a composition process by forming a sub-pixel 10 in a display area 01 and forming a virtual sub-pixel in a virtual display area 02 at the same time. On this basis, by disconnecting the thin film transistor 30 in the dummy sub-pixel 20 from the data line 50, a coupling capacitance between the data line 50 and the thin film transistor 30 in the dummy sub-pixel 20 can be avoided, so that the load of the data line 50 is reduced, and further, when the array substrate is used for a display device, the power consumption of the display device can be reduced.
Alternatively, as shown in fig. 4 and fig. 5(a) -5 (b), the gate electrode of the thin film transistor 30 located in the sub-pixel is connected to the gate line 61; the gate of the thin film transistor 30 located in the dummy sub-pixel 20 is electrically connected to the first common electrode line 62; wherein the first transparent electrode 41 in the dummy sub-pixel 20 is connected to the first common electrode line 62 through a via hole.
Optionally, the sub-pixel 10 and the dummy sub-pixel 20 further include a second transparent electrode 42; the second transparent electrode 42 is electrically connected to the second common electrode line 63; as shown in fig. 6(a) and 6(b), the first transparent electrode 41 in the dummy sub-pixel 20 and the second transparent electrode 42 in the dummy sub-pixel 20 are connected through a via hole. Alternatively, as shown in fig. 7(a) and 7(b), the first transparent electrode 41 located in the dummy sub-pixel 20 and the second common electrode line 63 are connected through a via hole.
As described above, the gate electrode of the thin film transistor 30 in the dummy sub-pixel 20 and the first transparent electrode 41 are electrically connected to the first common electrode line 62, so that the gate electrode and the first transparent electrode 41 have the same potential, and the source electrode 31, the drain electrode 32, and the gate electrode of the thin film transistor 30 in the dummy sub-pixel 20 have the same potential, thereby preventing static electricity from being generated.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. The array substrate is characterized by comprising a display area and a virtual display area arranged at the periphery of the display area; the display area comprises sub-pixels, and the virtual display area comprises virtual sub-pixels;
the sub-pixels and the dummy sub-pixels each include a thin film transistor, a first transparent electrode electrically connected to a drain of the thin film transistor;
the source electrode of the thin film transistor in the sub-pixel is connected with a data line; the source electrode of the thin film transistor in the virtual sub-pixel is disconnected from the data line.
2. The array substrate of claim 1, wherein the gate electrode of the thin film transistor in the sub-pixel is connected to a gate line;
the grid electrode of the thin film transistor in the virtual sub-pixel is electrically connected with a first common electrode wire;
wherein the first transparent electrode in the dummy sub-pixel is electrically connected to the first common electrode line.
3. The array substrate of claim 2, wherein the sub-pixels and the dummy sub-pixels further comprise a second transparent electrode, respectively;
the second transparent electrode is electrically connected with a second common electrode wire;
wherein the second common electrode line is electrically connected with the first common electrode line.
4. The array substrate of claim 2, wherein the first transparent electrode in the dummy sub-pixel is connected to the first common electrode line through a via hole.
5. The array substrate of claim 3, wherein the first transparent electrode in the virtual sub-pixel and the second transparent electrode in the virtual sub-pixel are connected by a via; or,
and the first transparent electrode in the virtual sub-pixel is connected with the second common electrode wire through a via hole.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. The display panel according to claim 6, further comprising a pair of cell substrates;
the second transparent electrode is disposed in the pair of cassette substrates or the array substrate.
8. A preparation method of an array substrate is characterized by comprising the following steps: synchronously forming sub-pixels in a display area, and forming virtual sub-pixels in a virtual display area at the periphery of the display area;
the sub-pixels and the dummy sub-pixels each include a thin film transistor, a first transparent electrode electrically connected to a drain of the thin film transistor;
the source electrode of the thin film transistor in the sub-pixel is connected with a data line; the source electrode of the thin film transistor in the virtual sub-pixel is disconnected from the data line.
9. The manufacturing method according to claim 8, wherein a gate electrode of the thin film transistor in the sub-pixel is connected to a gate line;
the grid electrode of the thin film transistor in the virtual sub-pixel is electrically connected with a first common electrode wire;
the first transparent electrode in the virtual sub-pixel is connected with the first common electrode line through a via hole.
10. The method of claim 8, wherein the sub-pixels and the dummy sub-pixels further comprise second transparent electrodes, respectively;
the second transparent electrode is electrically connected with a second common electrode wire;
the first transparent electrode in the virtual sub-pixel and the second transparent electrode in the virtual sub-pixel are connected through a through hole; or,
and the first transparent electrode in the virtual sub-pixel is connected with the second common electrode wire through a via hole.
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| CN201611015730.4A CN106356381B (en) | 2016-11-18 | 2016-11-18 | A kind of array substrate and preparation method thereof, display panel |
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| CN201611015730.4A CN106356381B (en) | 2016-11-18 | 2016-11-18 | A kind of array substrate and preparation method thereof, display panel |
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| CN106356381B CN106356381B (en) | 2019-06-14 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107644879A (en) * | 2017-09-19 | 2018-01-30 | 京东方科技集团股份有限公司 | Prepare method, array base palte, the display device of array base palte |
| CN107870493A (en) * | 2017-11-01 | 2018-04-03 | 厦门天马微电子有限公司 | Display panel and display device |
| CN109375439A (en) * | 2018-12-20 | 2019-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN110718180A (en) * | 2019-11-15 | 2020-01-21 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof |
| CN111624803A (en) * | 2019-02-27 | 2020-09-04 | 株式会社日本显示器 | Display device |
| CN112764281A (en) * | 2021-01-28 | 2021-05-07 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| US20220326558A1 (en) * | 2019-06-12 | 2022-10-13 | Boe Technology Group Co., Ltd. | Array substrate, display panel and display device |
| CN115668343A (en) * | 2022-08-30 | 2023-01-31 | 京东方科技集团股份有限公司 | Array substrate and display device |
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| CN107644879B (en) * | 2017-09-19 | 2019-11-05 | 京东方科技集团股份有限公司 | Prepare method, array substrate, the display device of array substrate |
| US10620492B2 (en) | 2017-09-19 | 2020-04-14 | Boe Technology Group Co., Ltd. | Method for manufacturing array substrate, array substrate and display device |
| CN107644879A (en) * | 2017-09-19 | 2018-01-30 | 京东方科技集团股份有限公司 | Prepare method, array base palte, the display device of array base palte |
| CN107870493A (en) * | 2017-11-01 | 2018-04-03 | 厦门天马微电子有限公司 | Display panel and display device |
| CN107870493B (en) * | 2017-11-01 | 2021-06-04 | 厦门天马微电子有限公司 | Display panel and display device |
| US11037961B2 (en) | 2018-12-20 | 2021-06-15 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate and display panel |
| CN109375439A (en) * | 2018-12-20 | 2019-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN111624803B (en) * | 2019-02-27 | 2023-04-28 | 株式会社日本显示器 | Display device |
| CN111624803A (en) * | 2019-02-27 | 2020-09-04 | 株式会社日本显示器 | Display device |
| US20220326558A1 (en) * | 2019-06-12 | 2022-10-13 | Boe Technology Group Co., Ltd. | Array substrate, display panel and display device |
| US11940700B2 (en) * | 2019-06-12 | 2024-03-26 | Boe Technology Group Co., Ltd. | Array substrate, display panel and display device |
| CN110718180A (en) * | 2019-11-15 | 2020-01-21 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof |
| CN112764281B (en) * | 2021-01-28 | 2021-11-23 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| WO2022160392A1 (en) * | 2021-01-28 | 2022-08-04 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN112764281A (en) * | 2021-01-28 | 2021-05-07 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN115668343A (en) * | 2022-08-30 | 2023-01-31 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN115668343B (en) * | 2022-08-30 | 2023-09-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
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