CN106356301A - Semiconductor apparatus and manufacturing method thereof - Google Patents
Semiconductor apparatus and manufacturing method thereof Download PDFInfo
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- CN106356301A CN106356301A CN201510422550.7A CN201510422550A CN106356301A CN 106356301 A CN106356301 A CN 106356301A CN 201510422550 A CN201510422550 A CN 201510422550A CN 106356301 A CN106356301 A CN 106356301A
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- 239000010410 layer Substances 0.000 claims description 220
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a semiconductor apparatus and a manufacturing method of a semiconductor apparatus, and relates to the technical field of a semiconductor. The manufacturing method of the semiconductor apparatus includes steps of providing a semiconductor substrate, wherein the semiconductor substrate includes a first zone and a second zone; forming a first fin on the surface of the semiconductor substrate corresponding to the first zone, forming a second fin on the surface of the semiconductor substrate corresponding to the second zone; forming an adhesion layer including first conductive type mixing impurity on an exposed surface of the first fin; forming an epitaxial layer including second conductive type mixing impurity on an exposed surface of the second fin; forming a shallow channel isolating structure on the surface of the semiconductor substrate; removing the epitaxial layer exposed at the upper part of the shallow channel isolating structure; removing the adhesion layer exposed at the upper part of the shallow channel isolating structure; performing a first annealing treatment. The semiconductor apparatus manufactured through the method of the invention has higher carrier mobility, and avoids fine damage caused by ion injection, thus further improving the apparatus performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and its
Manufacture method.
Background technology
With the continuous development of semiconductor technology, in order to improve the performance of device, need constantly to contract
The size of little IC-components, with constantly reducing of cmos device size, promotes
The development of three dimensional design such as FinFET (finfet).Brilliant with respect to existing plane
Body pipe, described finfet device has at the aspect such as raceway groove control and reduction short-channel effect
More superior performance；Planar gate is arranged above described raceway groove, and in finfet
Described in grid arrange around described fin, therefore can control electrostatic from three faces, in electrostatic
The performance of control aspect is also more prominent.
There are a lot of methods in prior art for improving the performance of semiconductor device, for example, partly leading
Form super steep retroversion trap (super steep retrograde well, letter in body device fabrication process
Claim ssrw), isolation deep trap is formed by ion implanting and anti-body punctures (anti-punch
Trough, abbreviation apt) ion implanting etc..
For p trap, the formation of super steep retroversion trap is extremely difficult, is difficult to mainly due to boron loss
Control especially be susceptible to oxidation strengthen (oxidation enhanced diffusion, referred to as
Oed) the oxidation stage of effect, for example, laying growth, sti annealing stage and grid afterwards
Oxygen forms link, and in the above-mentioned stage, impurity boron readily diffuses in oxide,
And cause b to lose.And in order to control short-channel effect well, attempt in finfet device
Raceway groove in heavy dose of in or bf of heavy doping2.But so heavy dose of doping leads to narrow fin
The major injury of piece, also is difficult to repair to fin even with the annealing after ion implanting
The damage causing, and the fin sustaining damage significantly reduces the mobility of carrier and so that mixes
Impurity inactivates (de-activation).
In addition, the manufacturing process of commonplace use at present is, deep trap isolation is infused in fin shape
Carry out before one-tenth, anti-body punctures (anti-punch trough, abbreviation apt) ion implanting
Carry out after fin is formed, carrying out anti-body after fin is formed, to puncture ion implanting favourable
In the loss controlling impurity, but substantial amounts of injection ion also results in the damage of fin,
As shown in figure 1, a large amount of impaired locis are had on fin, observe and find to damage especially at the top of fin
It is serious.
Therefore, it is necessary to propose a kind of manufacture method of new semiconductor device, above-mentioned to solve
Technical problem.
Content of the invention
Introduce a series of concept of reduced forms in Summary, this will be specifically real
Apply mode partly middle further description.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
For the deficiencies in the prior art, the embodiment of the present invention one provides a kind of system of semiconductor device
Make method, comprising:
Step s1: provide Semiconductor substrate, described Semiconductor substrate includes first area and the
Two regions, are formed with the first conduction type in the described Semiconductor substrate of corresponding described first area
The first trap, be formed with second in the described Semiconductor substrate in corresponding described second area conductive
Second trap of type, described semiconductor substrate surface corresponding with described first area is formed with
First fin, described semiconductor substrate surface corresponding with described second area is formed with second
Fin；
Step s2: formed on the surface that described first fin exposes and include the first conduction type
The adhesion layer of impurity；
Step s3: formed on the surface that described second fin exposes and include the second conduction type
The epitaxial layer of impurity；
Step s4: fleet plough groove isolation structure, institute are formed on the surface of described Semiconductor substrate
The top surface stating fleet plough groove isolation structure is less than the top surface of described first fin and described second fin；
Step s5: remove the described epitaxial layer exposing above described fleet plough groove isolation structure；
Step s6: remove the described adhesion layer exposing above described fleet plough groove isolation structure；
Step s7: carry out the first annealing, so that the first conductive-type in described adhesion layer
The second conduction type impurity in type impurity and described epitaxial layer is respectively to described
One fin and described second fin internal diffusion are to form channel stop layer.
Alternatively, in described step s1, formed described first conduction type the first trap and
The method of the second trap of the second conduction type comprises the following steps:
Protective layer is formed on the surface of described Semiconductor substrate；In corresponding described first area
First photoresist layer of patterning is formed on the surface of described protective layer；
First ion implanting is carried out for mask with described first photoresist layer, with correspondence described the
Form the second trap of the second conduction type in the described Semiconductor substrate in two regions；
Remove described first photoresist layer；
The surface of the described protective layer of corresponding described second area forms the second of patterning
Photoresist layer；
Second ion implanting is carried out for mask with described second photoresist layer, with correspondence described the
Form the first trap of the first conduction type in the described Semiconductor substrate in one region；
Remove described second photoresist layer.
Alternatively, in described step s1, described first fin and described second fin are formed
Method comprise the following steps:
Form the mask layer of patterning, the covering of described patterning on the surface of described Semiconductor substrate
Film layer definition has described first fin and the pattern of described second fin；
With the mask layer of described patterning as mask, etch described Semiconductor substrate, to be formed
State the first fin and described second fin.
Alternatively, further comprising the steps of between described step s1 and described step s2:
Form the laying on the surface covering described first fin and described second fin, to repair
The damaging and make described first fin and described second of described first fin and described second fin
The smooth surface of fin；
Remove described laying.
Alternatively, described laying produces oxide liner layer for original position steam.
Alternatively, it is additionally included in formation cover layer on described adhesion layer in described step s2
Step.
Alternatively, in described step s2, the surface that described first fin exposes is formed
Adhesion layer including the first conduction type impurity includes:
Sequentially form including the adhesion layer of the first conduction type impurity and cover layer in described
On the surface that Semiconductor substrate and described first fin and described second fin expose；
Remove on the semiconductor substrate surface of described second area and described second fin table
Described adhesion layer on face and cover layer.
Alternatively, in described step step s4, form the side of described fleet plough groove isolation structure
Method comprises the following steps:
Formed and cover described semiconductor substrate surface and described first fin and described second fin
Spacer material layer；
Planarize described spacer material layer, stop at described first fin and described second fin
On top surface；
Spacer material layer described in etch-back, to form described fleet plough groove isolation structure.
Alternatively, the method forming described spacer material layer comprises the following steps:
Cover described semiconductor substrate surface and described first fin using fcvd process deposits
Spacer material layer with described second fin；
Carry out the second annealing.
The embodiment of the present invention two provides the semiconductor device that a kind of employing preceding method manufactures.
In sum, the manufacture method of the present invention does not need using channel stop ion implanting system
Journey, therefore avoids the appearance that ion implanting causes damage problem to fin, further increases
The performance of device, in addition, manufacturing method according to the invention is doped to fin, fin
Top section is undoped, and the part that the bottom of fin is doped is by fleet plough groove isolation structure bag
Enclose, therefore higher carrier mobility is had by the semiconductor device that the method for the present invention makes
Rate.
Brief description
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
In figure shows embodiments of the invention and its description, for explaining the principle of the present invention.
In accompanying drawing:
Fig. 1 is that anti-body punctures the schematic diagram that ion implanting causes to damage to fin；
Fig. 2 a to Fig. 2 m is a kind of manufacture of semiconductor device of one embodiment of the present of invention
The sectional view of the structure that the correlation step of method is formed；
Fig. 3 is a kind of showing of the manufacture method of semiconductor device of one embodiment of the present of invention
Meaning property flow chart.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that the present invention
Can one or more of these details and be carried out.In other examples, in order to keep away
Exempt to obscure with the present invention, some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly and complete to provide these embodiments will make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He area and relative size may be exaggerated.Identical attached from start to finish
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... adjacent ", " being connected to "
Or " being coupled to " other element or during layer, its can directly on other elements or layer and
Adjacent, be connected or coupled to other elements or layer, or there may be element between two parties or layer.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other element or layer, then there is not element between two parties or layer.Should
Understand, although can using term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term limits.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, without departing from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience here and by using from
And the relation of shown in figure a element or feature and other elements or feature is described.Should be bright
In vain, in addition to the orientation shown in except in figure, spatial relationship term is intended to also include using and operating
In device different orientation.For example, if the device upset in accompanying drawing, then, it is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
Be other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (ratate 90 degrees or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When here uses, " one " of singulative, " one " and " described/should "
It is also intended to including plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " inclusion ", when using in this specification, determine described feature,
The presence of integer, step, operation, element and/or part, but be not excluded for one or more its
The presence of its feature, integer, step, operation, element, part and/or group or interpolation.
When here uses, term "and/or" includes any and all combination of related Listed Items.
Horizontal stroke herein with reference to the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view is describing inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or the change from shown shape that tolerance leads to.Therefore, embodiments of the invention should not limit to
In the given shape in area shown here, but include inclined due to for example manufacturing the shape leading to
Difference.For example, be shown as the injection region of rectangle its edge generally have round or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
May result in the surface that this disposal area and injection are passed through when carrying out by injecting the disposal area being formed
Between area in some injection.Therefore, the area that in figure shows is substantially schematically, it
Shape be not intended the true form in area of display device and be not intended to limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed step and in detail will be proposed in following description
Thin structure, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is detailed
Carefully it is described as follows, but in addition to these describe in detail, the present invention can also have other enforcements
Mode.
Embodiment one
Below, reference picture 2a to Fig. 2 m and Fig. 3 carries describing one embodiment of the present of invention
A kind of manufacture method of the semiconductor device going out.Wherein, Fig. 2 a to Fig. 2 m is the present invention's
The structure that a kind of correlation step of the manufacture method of semiconductor device of one embodiment is formed
Sectional view；Fig. 3 is a kind of manufacture method of semiconductor device of one embodiment of the present of invention
Indicative flowchart.
Exemplarily, the manufacture method of the semiconductor device of one embodiment of the present of invention, including
Following steps:
First, execution step s301, provides Semiconductor substrate, and described Semiconductor substrate includes
First area and second area, are formed with the described Semiconductor substrate of corresponding described first area
First trap of the first conduction type, shape in the described Semiconductor substrate in corresponding described second area
Become to have the second trap of the second conduction type, described Semiconductor substrate corresponding with described first area
First fin is formed with surface, described semiconductor substrate surface corresponding with described second area
On be formed with the second fin.
Specifically, described Semiconductor substrate can be at least in the following material being previously mentioned
Kind: stacking silicon (ssoi), insulator upper strata on silicon, silicon-on-insulator (soi), insulator
Folded SiGe (s-sigeoi), germanium on insulator SiClx (sigeoi) and germanium on insulator
(geoi) etc..
First area is pmos area, and second area is nmos area, described first conductive-type
Type is N-shaped, and described second conduction type is p-type, or, described first area is nmos
Area, second area is pmos area, and described first conduction type is p-type, and described second leads
Electric type is N-shaped.
Described first trap and described can be formed using any method well known to those skilled in the art
Second trap, exemplarily, when first area is pmos area, second area is nmos area,
Described first conduction type is N-shaped, and described second conduction type is p-type, as shown in Figure 2 a,
Semiconductor substrate 200 is provided, the surface of described Semiconductor substrate 200 forms protective layer 21,
In the present embodiment, the material of protective layer 21 is preferably silicon oxide, can using chemical vapor deposition,
The methods such as thermal oxide are formed, and this protective layer 21 can prevent follow-up photoresist layer directly contact half
Conductor substrate, after still preventing, ion implanting is formed during well region to semiconductor substrate surface simultaneously
Bombardment damage generation；Then, on the surface of the described protective layer 21 in corresponding pmos area
Upper the first photoresist layer 201p forming patterning；With described first photoresist layer 201p for covering
Film carries out the first ion implanting, with the described Semiconductor substrate 200 in corresponding nmos area
Form p-type trap (not shown)；Remove described first photoresist layer.As shown in Figure 2 b, exist
Second photoresist layer of patterning is formed on the surface of described protective layer 21 in corresponding nmos area
201n；Second ion implanting is carried out for mask with described second photoresist layer 201n, with right
Answer formation N-shaped trap (not shown) in the described Semiconductor substrate 200 in pmos area；Remove institute
State the second photoresist layer 201n.When the first photoresist layer 201p covers pmos region, expose
Nmos region carries out ion doping injection to nmos region, impurity can be phosphorus,
Arsenic etc., dosage is 1e13～5e15Atom/cm2；When the second photoresist layer 201p covers nmos
Pmos region is exposed in region, carries out ion doping injection, impurity to pmos region
Can be boron, bf2Deng dosage can be 1e13～3e15Atom/cm2.It is, of course, also possible to first
Pmos area is carried out with ion implanting and forms N-shaped well region, then ion note is carried out to nmos area
Enter to be formed p-type well region.
In one example, as shown in Figure 2 c, form described first fin 202p and described
The method of the second fin 202n comprises the following steps:
Form the mask layer 203 of patterning, described figure on the surface of described Semiconductor substrate 200
Mask layer 203 definition of case has described first fin 202p's and described second fin 202n
Pattern, including the width of fin, length and position etc.；Mask layer with described patterning
203 is mask, is sequentially etched described protective layer 21 and Semiconductor substrate 200, described to be formed
First fin 202p and described second fin 202n.Mask layer generally can include several masks
Any one of material, including but not limited to: hard mask material and photoresist mask material.This
In embodiment, mask layer includes hard mask material.Described hard mask material can be this area skill
Known to art personnel can as the material of hard mask, it is preferred that hard mask material be silicon nitride,
Lamination of film layer that hard mask material can also be suitable for other for silicon nitride material etc..
Above-mentioned etching, wherein, dry etching can be carried out using the method such as dry etching or wet etching
Etching technique can for reactive ion etching, ion beam etching, plasma etching, laser ablation or
The combination in any of these methods of person.Using single lithographic method, or can also can also make
With more than one lithographic method.
The forming method of described first fin 202p and described second fin 202n can also be:
Form semiconductor material layer on a semiconductor substrate first, formed in Semiconductor substrate and had
Well region, described semiconductor material layer can be with si, sige, ge or such as GaAs etc
Iii-v race material, then forms the mask layer of patterning, example on described semiconductor material layer
As photoresist mask layer, described photoresist mask layer define the width of described fin, length with
And position etc., semiconductor material layer described in then with described photoresist mask layer as mask etch,
To form fin.
It should be noted that forming described first fin 202p's and described second fin 202n
That method is merely exemplary it is not limited to said method.
It is also possible to described first fin 202p and described second fin in above-mentioned etching process
Piece 202n causes to damage, and therefore optionally carries out to the first fin 202p and the second fin
The reparation step of 202n.
In one example, as shown in Figure 2 d, formed cover described first fin 202p and
The laying 204 on the surface of described second fin 202n, to repair described first fin 202p
With the damaging and make described first fin 202p and described second fin of described second fin 202n
The smooth surface of 202n.Laying 204 can include any one of several gasket materials,
Including but not limited to: silicon oxide liner cushion material and silicon nitride liner material, laying preferably wraps
Include described laying 204 for original position steam produce (in-situ steam generation, referred to as
Issg) oxide liner layer.As shown in Figure 2 e, remove described laying.Using issg
Oxidation technology, in the epontic one layer of oxide liner layer of the first fin and the second fin, should
The formation of laying consumes the first fin and the part silicon materials on the second fin surface, removes lining
After bed course, the damage on fin surface is also repaired simultaneously, and also can make the surface of fin more
Smooth.
Then, execution step s302, forms on the surface that described first fin exposes and includes
The adhesion layer of the first conduction type impurity.
In one example, as shown in figure 2f, the step forming described adhesion layer includes: according to
The secondary adhesion layer 205 including the first conduction type impurity and the cover layer 206 of being formed is in described
The table that Semiconductor substrate 200 and described first fin 202p and described second fin 202n expose
The mask layer 203 of face and patterning.In the present embodiment, mask layer 203 is preferably covered firmly
Film layer, hard mask layer for silicon nitride layer or can comprise combination layer of silicon nitride etc..Described inclusion
The adhesion layer 205 of the first conduction type impurity can be including as element or p element or
The adherent layer of oxide of both combinations.Can be using including but not limited to: chemical vapor deposition side
The method of method and physical vapor deposition methods forms adhesion layer 205.Any this area skill can be adopted
Method known to art personnel makes adhesion layer include the first conduction type impurity, for example may be used
Inject the first conduction type by way of ion implanting in the adhesion layer 205 of formation of deposits
Impurity, forms the adhesion layer including the first conduction type impurity.Can also be in adhesion
While layer 205 deposition, the first conduction type impurity is incorporated in adhesion layer 205, example
As supply such as hydrogen phosphide (ph can be passed through during adhesion layer 205 depositing operation3) or arsenic hydride
(ash3) etc. admixture material so that adhesion layer 205 is included as phosphorus (p) or arsenic (as) or a combination thereof etc.
N-shaped impurity.The material of cover layer 206 can selected from sicn, sin, sic, siof,
One or more of materials such as sion, wherein, in the present embodiment, the material of cover layer 206
Expect for silicon nitride.
Then, as shown in Figure 2 g, form the photoresist layer 207a covering pmos area, remove
The surface with described second fin 202n on Semiconductor substrate 200 surface in nmos area
On described adhesion layer 205 and cover layer 206, retain pmos area correspond to Semiconductor substrate table
Described adhesion layer 205 on face and on the surface of described first fin 202p and cover layer 206.
The adhesion layer 205 on the first fin 202p surface and cover layer 206 can also only be retained.
Described adhesion layer 205 and cover layer can be removed using the method for wet etching or dry etching
206, afterwards, remove photoresist layer 207a.
Then, execution step s303, forms on the surface that described second fin exposes and includes
The epitaxial layer of the second conduction type impurity.
Exemplarily, as shown in fig. 2h, on the corresponding Semiconductor substrate in noms area 200 surface
Formed on the upper surface with described second fin 202n and include the second conduction type impurity
Epitaxial layer 208.The material of described epitaxial layer 208 can be including the second conduction type impurity
Any semi-conducting material, for example, described semi-conducting material can for si, sige, ge or
The iii-v race material of such as GaAs etc.In the present embodiment, preferably described inclusion second is led
The epitaxial layer 208 of electric type impurity is the silicon epitaxy layer that boron element adulterates in situ.
Also optionally only on the surface that second fin in nmos area exposes, grow extension
Layer, for example, using mask layer by other region overlay beyond the second fin, and makes extension
Layer is only optionally grown on the surface that the second fin exposes.
Selective epitaxial growth can adopt low-pressure chemical vapor deposition (lpcvd), plasma
Body strengthen chemical vapor deposition (pecvd), ultra-high vacuum CVD (uhvcvd),
One of rapid thermal CVD (rtcvd) and molecular beam epitaxy (mbe).
Described selective epitaxial growth can be carried out in uhv/cvd reaction chamber.Outside described selectivity
Epitaxial growth is to be 1～100 support and temperature is under 500～1000 degrees Celsius of process conditions in pressure
Carry out.
Adulterated in situ with depositing the epitaxial layer including the second conduction type impurity for boron element
Silicon epitaxy layer as a example, depositing operation can be chemical vapor deposition or plasma enhanced chemical gas
Mutually deposit (pecvd), wherein use as sicl4、sihcl3Or sih2cl2Deng inclusion
The reacting gas of chlorine and/or wherein use such as hcl etc. include chlorine also just like sih4Or
si2h6Deng the compound including silicon.Chlorine atom can be deposited in silicon dioxide or silicon nitride
Silicon chemically reactive and produce the gaseous reaction products that can be extracted out from reative cell, and include
Silicon metal is in interior electrodeposition substance on the surface that Semiconductor substrate 200 exposes and the second fin
On the surface of 202n, without or seldom have semiconductor material deposition on mask layer 203, with
And on the surface of mask layer 207b in the pmos area covering.Can pass through to carry during depositing operation
For such as boron, boron difluoride (bf2) and/or diborane (b2h6) etc. admixture material so that epitaxial layer
208 include the p-type impurity as boron etc.
During outer layer growth, also can be initially formed the mask layer covering in pmos area
207b, so that epitaxial layer will not be deposited in pmos area, this mask layer 207b can include
Any one of several mask materials, including but not limited to: hard mask material and photoresist mask
Material.In the present embodiment, mask layer includes hard mask material.Described hard mask material can be
Well known to those skilled in the art can be as the material of hard mask, it is preferred that hard mask material
For silicon oxide, this silicon oxide also can be directly used as after fleet plough groove isolation structure packing material,
And if when mask layer 207b is other such as photoresist layer, it can need to lead to after epitaxial deposition
Cross the methods such as ashing to remove.
Wherein, the thickness range of described epitaxial layer 208 can be 1～5nm, such as 1nm, 2nm,
3nm, 4nm, 5nm, in the present embodiment, the thickness of epitaxial layer 208 is 2nm.Above-mentioned thickness
Degree scope and numerical value are only exemplarily, also can suitably be adjusted according to actual process process requirements
Whole.
Then, execution step s304, forms shallow trench on the surface of described Semiconductor substrate
Isolation structure, the top surface of described fleet plough groove isolation structure is less than described first fin and described second
The top surface of fin.
In one example, the step forming fleet plough groove isolation structure includes:
First, as shown in fig. 2i, formed and cover described Semiconductor substrate 200 surface and described
The first fin 202p and spacer material layer 209a of described second fin 202n.Described isolation
The material of material layer 209a can include silicon oxide, silicon nitride, silicon oxynitride etc..Can adopt
The deposition process of any spacer material layer 209a well known to those skilled in the art is formed, for example,
The method such as chemical gaseous phase depositing process or plasma reinforced chemical vapour deposition.In the present embodiment,
Fcvd process deposits are preferably adopted to cover described Semiconductor substrate 200 surface and described the
The one fin 202p and spacer material layer 209a of described second fin 202n, and carry out afterwards
Annealing, described annealing can be using wet method annealing or dry method annealing, also can individually or two
Person is used in combination, and also can anneal this spacer material layer in conjunction with other annealing technologies, including etc. from
Daughter annealing, ultraviolet photo-annealing, electron beam annealing and/or microwave annealing etc..Dry method annealing
Inert atmosphere can be drying nitrogen, helium or argon etc..Wherein, annealing temperature is less than or equal to
600 DEG C, for example, 400～600 DEG C, or other temperature that can improve flowable dielectric material quality
Degree may be applicable to the present invention.
Then, as shown in figure 2j, planarize described spacer material layer 209a, stop at described
On the top surface of the first fin 202p and described second fin 202n.As the first fin 202p and
When being formed with mask layer 203 on the second fin 202n, this planarization can be made to stop at mask layer
In 203.Surface can be realized using conventional flattening method in field of semiconductor manufacture
Planarization.The non-limiting examples of this flattening method include mechanical planarization method and chemical machine
Tool polishes flattening method.Chemically mechanical polishing flattening method is more often used.
Then, as shown in Fig. 2 k, spacer material layer 209a described in etch-back, described to be formed
Fleet plough groove isolation structure 209, and remove mask layer 203 and protective layer 21.Described it is etched back to work
Skill can adopt wet etching or dry etching.In a specific embodiment of the present invention, can
To be etched back to technique using dry etching execution, dry method etch technology includes but is not limited to: reaction
Ion(ic) etching (rie), ion beam milling, plasma etching or cut.Mask layer
203 and protective layer 21 minimizing technology can according to its material select be suitable for method, here is not
Repeat.
Then, execution step s305, removes the institute exposing above described fleet plough groove isolation structure
State epitaxial layer.
As illustrated in figure 21, remove the described outer of described fleet plough groove isolation structure 209 top exposure
Prolong layer 208.Described epitaxial layer can be removed using any method well known to those skilled in the art,
Such as wet etching or dry etching.In the present embodiment, have using to described epitaxial layer 208
There is the etching agent of extremely low etch rate, wet etching removes above described fleet plough groove isolation structure
The described epitaxial layer exposing.Exemplarily, described etching agent can be tmah etching agent.
In this step, mask layer such as photoresist layer can be formed in the region beyond the epitaxial layer exposing,
Make this step wet etching just for epitaxial layer, rather than other film layers.
Then, execution step s306, removes the institute exposing above described fleet plough groove isolation structure
State adhesion layer.
As shown in Fig. 2 m, remove the described viscous of described fleet plough groove isolation structure 209 top exposure
Attached layer 205.Both oxide skin(coating) can also be removed using wet etch method using dry ecthing method.
Dry ecthing method can be using the anisotropic etch process based on carbon fluoride gas.Wet etch method adopts
Method including the solution cleaning of Fluohydric acid. (dhf) removes described fleet plough groove isolation structure 209
The described adhesion layer 205 that top exposes, such as buffer oxide etch agent
(buffer oxide etchant (boe)) or Fluohydric acid. buffer solution
(buffer solution of hydrofluoric acid(bhf)).
Exemplarily, only remove part adhesion layer 205 due in this step, therefore can will adhere to
Other regions beyond layer 205 adopt mask layer such as photoresist layer to cover, and make this step clear
Wash just for the adhesion layer 205 exposing, and do not affect other film layers and material.
Wherein, the order of above-mentioned steps s305 and s306 is also commutative, you can first carry out step
S306 carries out step s305 again, also can achieve identical effect.
Finally, execution step s307, carries out the first annealing, so that in described adhesion layer
The first conduction type impurity and described epitaxial layer in the second conduction type impurity
Respectively to described first fin and described second fin internal diffusion to form channel stop layer.
With continued reference to Fig. 2 m, carry out the first annealing, so that first in described adhesion layer
The second conduction type impurity in conduction type impurity and described epitaxial layer respectively to
Described first fin and described second fin internal diffusion are to form channel stop layer.Therefore, in quilt
The surface of partly described first fin that described adhesion layer surrounds defines has the first conductive-type
The channel stop layer (not shown) of type, and partly described being surrounded by described epitaxial layer again
The surface of two fins is formed with the channel stop layer (not shown) with the second conduction type.Institute
State the first annealing to carry out under an inert atmosphere, described inert atmosphere can be drying nitrogen, helium
Gas or argon etc..Annealing can be thermal anneal process, such as rapid thermal annealing, since being wherein
From the radiation of lamp or laser, Semiconductor substrate and various film layer structures thereon are irradiated.Right
The absorption of radiation can make Semiconductor substrate and the temperature of various film layer structures thereon raise, and then
Activation impurity is so as to fin internal diffusion.In other specific embodiments, can be in baking oven
Inside made annealing treatment.Annealing can be entered in about 550 DEG C to about 700 DEG C of temperature range
Carry out can OK, and in the time range of about 15 minutes to about 45 minutes.
Because adhesion layer 205 and epitaxial layer 208 only enclose the bottom of fin, the bottom of this fin
Portion is located in fleet plough groove isolation structure, and annealing only can make impurity enter the bottom of fin,
And the top section not being attached the fin of layer 205 and epitaxial layer 208 encirclement does not then have and mixes
Impurity diffuses into, and therefore improves the mobility of carrier in device.
So far, complete the correlation step of the manufacturing process of the semiconductor device of the embodiment of the present invention
Introduction.After the above step, other correlation step can also be included, such as described
Formation grid structure on one fin and described second fin, and make its of finfet device
His conventional steps, here is omitted.And, in addition to the foregoing steps, the present embodiment
Preparation method can also include other steps among each step above-mentioned or between different steps
Suddenly, these steps all can be realized by various techniques of the prior art, no longer superfluous herein
State.
In sum, the manufacture method of the present invention does not need using channel stop ion implanting system
Journey, therefore avoids the appearance that ion implanting causes damage problem to fin, further increases
The performance of device, in addition, manufacturing method according to the invention is doped to fin, fin
Top section is undoped, and the part that the bottom of fin is doped is by fleet plough groove isolation structure bag
Enclose, therefore higher carrier mobility is had by the semiconductor device that the method for the present invention makes
Rate.
Embodiment two
A kind of partly leading using the manufacture method acquisition in embodiment one is also provided in the present embodiment
Body device, this semiconductor device can be finfet device.Below with reference to Fig. 2 m to this
Bright semiconductor device is described in detail.
The semiconductor device of the present invention includes: Semiconductor substrate 200, described semiconductor substrate
Include first area and second area, formed in the described Semiconductor substrate of corresponding described first area
There is the first trap of the first conduction type, in the described Semiconductor substrate in corresponding described second area
It is formed with the second trap of the second conduction type, described quasiconductor lining corresponding with described first area
First fin 202p, described quasiconductor corresponding with described second area are formed with basal surface
Second fin 202n is formed with substrate surface.Described Semiconductor substrate 200 can be following
At least one in the material being previously mentioned: be laminated on silicon, silicon-on-insulator (soi), insulator
Stacking SiGe (s-sigeoi), germanium on insulator SiClx on silicon (ssoi), insulator
And germanium on insulator (geoi) etc. (sigeoi).Exemplarily, as shown in Fig. 2 m,
First area is pmos area, and second area is nmos area, and described first conduction type is
N-shaped, described second conduction type is p-type.
Also include the fleet plough groove isolation structure 209 on described semiconductor substrate surface, described
The top surface of fleet plough groove isolation structure 209 is less than described first fin 202p and described second fin
The top surface of 202n.The material of described spacer material layer 209a can include silicon oxide, silicon nitride,
Silicon oxynitride etc..Can adopt any spacer material layer 209a's well known to those skilled in the art
Deposition process is formed, for example, chemical gaseous phase depositing process or plasma reinforced chemical vapour deposition
Etc. method.
As shown in Fig. 2 m, also include described first fin 202p and described shallow trench isolation junction
Adhesion layer between structure 209, and partly described first fin being surrounded by described adhesion layer
Surface is formed with the channel stop layer (not shown) with the first conduction type, and this adhesion layer enters
One step extend to the surface of described Semiconductor substrate 200 and described fleet plough groove isolation structure 209 it
Between.In one example, described adhesion layer 205 and described fleet plough groove isolation structure 209 it
Between be also formed with cover layer 206.The material of cover layer 206 can selected from sicn, sin, sic,
One or more of materials such as siof, sion, wherein, in the present embodiment, cover layer 206
Material be silicon nitride.Exemplarily, described adhesion layer 205 is including as element or p unit
Element or the adherent layer of oxide of both combinations, the channel stop layer with the first conduction type is
The n-type channel stop-layer of as element or p element or both combined dopants.Or described adhesion
N-shaped impurity in layer 205 all diffuses into fin, and makes adhesion layer
Through not being doped.
As shown in Fig. 2 m, also include positioned at described second fin and described fleet plough groove isolation structure
Between epitaxial layer 208, and partly described second fin being surrounded by described epitaxial layer 208
The surface of 202n is formed with the channel stop layer (not shown) with the second conduction type.Described
Epitaxial layer 208 can also further extend into the described quasiconductor lining of corresponding described second area
Between the surface at bottom 200 and described fleet plough groove isolation structure 209.The material of described epitaxial layer 208
Material can be any semi-conducting material including the second conduction type impurity, for example, described
Semi-conducting material can be the iii-v race material of si, sige, ge or such as GaAs etc.
In the present embodiment, preferably the epitaxial layer 208 of described inclusion the second conduction type impurity is
The silicon epitaxy layer 208 of boron element in situ doping, then corresponding described have the second conduction type
Channel stop layer is p-type channel stop layer.Or, boron element has all diffused into second
Fin 202n, and make silicon epitaxy layer be undoped p epitaxial layer 208.Wherein, described epitaxial layer
208 thickness range can be 1～5nm, such as 1nm, 2nm, 3nm, 4nm, 5nm,
In the present embodiment, the thickness of epitaxial layer 208 is 2nm.Above-mentioned thickness range and numerical value only show
Example property ground, also can suitably be adjusted according to actual process process requirements.
In the above, first area is pmos area, and second area is nmos area, institute
Stating the first conduction type is N-shaped, and described second conduction type is p-type, or, described the
One region is nmos area, and second area is pmos area, and described first conduction type is p
Type, described second conduction type is N-shaped.
Said structure illustrate only the key structure part of the semiconductor device of the present invention, for
Complete finfet device also includes other structure sheafs, for example, be formed at the first fin and
Grid structure on two fins, source-drain electrode of grid structure both sides etc., here does not make detailed going to live in the household of one's in-laws on getting married
State.
In sum, the semiconductor device of the present invention does not need to stop using raceway groove in the fabrication process
Only ion implantation process, therefore avoids the appearance that ion implanting causes damage problem to fin,
Device is made to have higher performance, in addition, the fin top of semiconductor device according to the invention
Portion is partly undoped, and the part that the bottom of fin is doped is by fleet plough groove isolation structure bag
Enclose, the semiconductor device of the therefore present invention has higher carrier mobility.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of manufacture method of semiconductor device, methods described includes:
Step s1: provide Semiconductor substrate, described Semiconductor substrate includes first area and the
Two regions, are formed with the first conduction type in the described Semiconductor substrate of corresponding described first area
The first trap, be formed with second in the described Semiconductor substrate in corresponding described second area conductive
Second trap of type, described semiconductor substrate surface corresponding with described first area is formed with
First fin, described semiconductor substrate surface corresponding with described second area is formed with second
Fin；
Step s2: formed on the surface that described first fin exposes and include the first conduction type
The adhesion layer of impurity；
Step s3: formed on the surface that described second fin exposes and include the second conduction type
The epitaxial layer of impurity；
Step s4: fleet plough groove isolation structure, institute are formed on the surface of described Semiconductor substrate
The top surface stating fleet plough groove isolation structure is less than the top surface of described first fin and described second fin；
Step s5: remove the described epitaxial layer exposing above described fleet plough groove isolation structure；
Step s6: remove the described adhesion layer exposing above described fleet plough groove isolation structure；
Step s7: carry out the first annealing, so that the first conductive-type in described adhesion layer
The second conduction type impurity in type impurity and described epitaxial layer is respectively to described
One fin and described second fin internal diffusion are to form channel stop layer.
2. manufacture method according to claim 1 is it is characterised in that in described step
In s1, form the second trap of the first trap of described first conduction type and the second conduction type
Method comprises the following steps:
Protective layer is formed on the surface of described Semiconductor substrate；
The surface of the described protective layer of corresponding described first area forms the first of patterning
Photoresist layer；
First ion implanting is carried out for mask with described first photoresist layer, with correspondence described the
Form the second trap of the second conduction type in the described Semiconductor substrate in two regions；
Remove described first photoresist layer；
The surface of the described protective layer of corresponding described second area forms the second of patterning
Photoresist layer；
Second ion implanting is carried out for mask with described second photoresist layer, with correspondence described the
Form the first trap of the first conduction type in the described Semiconductor substrate in one region；
Remove described second photoresist layer.
3. manufacture method according to claim 1 is it is characterised in that in described step
In s1, form described first fin and the method for described second fin comprise the following steps:
Form the mask layer of patterning, the covering of described patterning on the surface of described Semiconductor substrate
Film layer definition has described first fin and the pattern of described second fin；
With the mask layer of described patterning as mask, etch described Semiconductor substrate, to be formed
State the first fin and described second fin.
4. the manufacture method according to claim 1 or 3 is it is characterised in that described
Further comprising the steps of between step s1 and described step s2:
Form the laying on the surface covering described first fin and described second fin, to repair
The damaging and make described first fin and described second of described first fin and described second fin
The smooth surface of fin；
Remove described laying.
5. manufacture method according to claim 4 is it is characterised in that described laying
Produce oxide liner layer for original position steam.
6. manufacture method according to claim 1 is it is characterised in that in described step
It is additionally included in the step forming cover layer on described adhesion layer in s2.
7. manufacture method according to claim 1 is it is characterised in that in described step
In s2, described first fin expose surface on formed includes first conduction type adulterate miscellaneous
The adhesion layer of matter includes:
Sequentially form including the adhesion layer of the first conduction type impurity and cover layer in described
On the surface that Semiconductor substrate and described first fin and described second fin expose；
Remove on the semiconductor substrate surface of described second area and described second fin table
Described adhesion layer on face and cover layer.
8. manufacture method according to claim 1 is it is characterised in that in described step
In step s4, the method forming described fleet plough groove isolation structure comprises the following steps:
Formed and cover described semiconductor substrate surface and described first fin and described second fin
Spacer material layer；
Planarize described spacer material layer, stop at described first fin and described second fin
On top surface；
Spacer material layer described in etch-back, to form described fleet plough groove isolation structure.
9. manufacture method according to claim 8 it is characterised in that formed described every
Method from material layer comprises the following steps:
Cover described semiconductor substrate surface and described first fin using fcvd process deposits
Spacer material layer with described second fin；
Carry out the second annealing.
10. the semiconductor device that a kind of one of employing claim 1-9 methods described manufactures.
Priority Applications (1)
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| CN109148581A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110634942A (en) * | 2018-06-22 | 2019-12-31 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN111463173A (en) * | 2019-01-18 | 2020-07-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113972136A (en) * | 2020-07-22 | 2022-01-25 | 中芯南方集成电路制造有限公司 | Semiconductor structure and forming method thereof |
| CN110634942B (en) * | 2018-06-22 | 2024-04-26 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
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| CN109148581A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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