CN106356089B - A kind of DDR2 DRAM ODT structure reducing electric power network Resistance Influence - Google Patents
A kind of DDR2 DRAM ODT structure reducing electric power network Resistance Influence Download PDFInfo
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- CN106356089B CN106356089B CN201610792364.7A CN201610792364A CN106356089B CN 106356089 B CN106356089 B CN 106356089B CN 201610792364 A CN201610792364 A CN 201610792364A CN 106356089 B CN106356089 B CN 106356089B
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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Abstract
The present invention proposes a kind of DDR2 DRAM ODT structure for reducing electric power network Resistance Influence, and overcoming the problems, such as the prior art, there are resistance deviations under different resistance modes.Voltage comparison module and signal conversion circuit are provided in the DDR2 DRAM ODT structure, voltage comparison module obtains the partial pressure of the resistance Rvddq on electric power network, the partial pressure switch is made to be to reduce with the independent compensation resistance in parallel of fixed resistance R0 in the resistive module of other resistance values, the resistance value of the compensation resistance with the increase of the partial pressure by signal conversion circuit.The present invention carries out feedback regulation using resistance of the partial pressure on the resistance Rvddq on electric power network to other resistance modes, so that the resistance of the corresponding resistive module of other modes increases with Rvddq and is reduced, to eliminate under different resistance modes because of Rvddq bring difference.
Description
Technical field
The present invention relates to a kind of circuit structures of DDR2 DRAM terminal resistance.
Background technique
In DDR2 DRAM, in order to improve signal integrity, each data interface module can provide terminal resistance
(ODT:On Die Termination), wherein ODT resistance includes pull-up resistor and pull down resistor, present patent application mainly for
The case where pull-up resistor.Wherein pull-up resistor can provide the resistance value of 3 kinds of modes: 100 ohm or 150 ohm or 300 ohm.
Traditional design is as shown in Figure 1, include the duplicate resistive module of three pieces (resistive module 1, resistive module 2, electricity
Hinder module 3), wherein each resistive module includes a fixed resistance (R0) and an adjustable resistance (Rx).In addition also
Including a resistance configuration module, for example, by the settable resistance mode of resistance configuration module be 300 ohm or 150 ohm or
100 ohm.It further include a resistance adjustment module, resistance adjustment module is mainly for for compensation process deviation and electric power network
On resistance (Rvddq).Rvddq be power supply (vddq) network on resistance, generally in 5~10 ohms comprising envelope
Load line resistance, metal connecting line resistance and via resistance in chip.
When being arranged to 300 ohm of modes, by resistance configuration module, en1 is set as high level, and resistive module 1 is selected
With；En2 and en3 is arranged to low level, and resistive module 2 and resistive module 3 are disabled (infinite).
When being arranged to 150 ohm of modes, by resistance configuration module, en1 and en2 are set as high level, resistive module 1
It is selected with resistive module 2；En3 is arranged to low level, and resistive module 3 is disabled (infinite).
When being arranged to 100 ohm of modes, by resistance configuration module, en1 and en2 and en3 are set as high level, resistance
Module 1 and resistive module 2 and resistive module 3 are all selected.
Fixed resistance (R0) structure for including in resistive module 1 and resistive module 2 and resistive module 3 is just the same, is all
Very stable linear resistance.
Adjustable resistance (Rx) structure for including in resistive module 1 and resistive module 2 and resistive module 3 is just the same, resistance
Value can be adjusted by resistance adjustment module.Resistance adjustment module is specifically to be based on maximum resistance mode (i.e. 300 ohm of modes)
Under, by signal sel<5:0>, resistance is accurately adjusted to 300 ohm, i.e. Rvddq+Rx+R0=300 ohm.
Although this traditional circuit structure as shown in Figure 1 can guarantee the accuracy of resistance under 300 ohm of modes, but work as
When being arranged to 150 ohm, resistance value is the parallel resistance that Rvddq adds resistive module 1 and resistive module 2, i.e. Rvddq+ (Rx+
R0)/2=Rvddq/2+Rvddq/2+ (Rx+R0)/2=Rvddq/2+ (Rvddq+Rx+R0)/2=Rvddq+75 (passes through resistance
Rvddq+Rx+R0=300 ohm after adjustment module), so the resistance Rvddq/2 bigger than normal at 150 ohm.
Similarly, but when being arranged to 100 ohm, resistance value is Rvddq plus resistive module 1 and resistive module 2 and resistance
The parallel resistance of module 3, i.e. Rvddq+ (Rx+R0)/3=Rvddq*2/3+Rvddq/3+ (Rx+R0)/3=Rvddq*2/3+
(Rvddq+Rx+R0)/3=Rvddq+50 (passes through Rvddq+Rx+R0=300 ohm after resistance adjustment module), so in 75 Europe
Resistance Rvddq*2/3 bigger than normal when nurse.
Summary of the invention
The present invention proposes a kind of DDR2 DRAM ODT structure for reducing electric power network Resistance Influence, it is intended to overcome existing skill
There is resistance deviation in different modes in art.
Solution of the invention is as follows:
The DDR2 DRAM ODT structure part identical with traditional structure is, all including resistance configuration module, resistance adjustment
Several resistive modules in parallel of module and different resistance values, each resistive module is by equivalent fixed resistance R0 and different resistances
The adjustable resistance Rx of value is in series；The resistance configuration module realizes different resistance by the combination gating to resistive module
Mode, the resistance adjustment module are gated described several based on the resistance Rvddq on maximum resistance mode tuning electric power network
The resistive module R of maximum value in a resistive modulemax, adjust resistance Rvddq make the standard resistance value of maximum resistance mode=
Rvddq+Rmax；It is different from traditional structure:
The DDR2 DRAM ODT structure further includes voltage comparison module and signal conversion circuit, and voltage comparison module obtains
The partial pressure of resistance Rvddq on electric power network makes the partial pressure switch be the electricity with other resistance values by signal conversion circuit
The independent compensation resistance in parallel of fixed resistance R0 in module is hindered, the resistance value of the compensation resistance subtracts with the increase of the partial pressure
It is small.
Above-mentioned signal conversion circuit and its concrete form of connection structure may is that signal conversion circuit includes multiple NMOS
Pipe, each NMOS tube are corresponded with the resistive module of other resistance values respectively, in each NMOS tube and corresponding resistor module
Fixed resistance R0 it is in parallel；The fence gate of whole NMOS tubes connects the output end (the i.e. described partial pressure) of voltage comparison module.
In view of current actual product situation, several above-mentioned resistive modules can be first resistor module, second resistance
Module and 3rd resistor module correspond respectively to 300 ohm of modes, 150 ohm of modes and 100 ohm of modes, second resistance mould
Block and the fixed resistance R0 of 3rd resistor module are in parallel with NMOS tube N3 and NMOS tube N2 respectively, NMOS tube N3 and NMOS tube N2's
Fence gate is connected to the output end of voltage comparison module altogether；Wherein, the size of NMOS tube N3 is 2 times of the size of NMOS tube N2.
The present invention has following technical effect that
It is (dynamic that feedback regulation is carried out using resistance of the partial pressure on the resistance Rvddq on electric power network to other resistance modes
State compensation) so that the resistance of the corresponding resistive module of other modes increases with Rvddq and is reduced, to eliminate in different resistance
Because of Rvddq bring difference under mode.
Structure of the invention is concise, using few and conventional component, achieves satisfied effect.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional scheme.
Fig. 2 is electrical block diagram of the invention.
Specific embodiment
The present embodiment is a kind of scheme for solving 150 ohm and the resistance deviation under 100 ohm of modes.After ODT is opened,
VDDQ becomes vddq_local after passing through electric power network resistance Rvddq, and voltage difference is generated between VDDQ and vddq_local, this
Voltage difference increases as Rvddq increases.
As shown in Fig. 2, voltage difference between VDDQ and vddq_local is changed into voltage signal by voltage comparison module
vout.A NMOS tube (N2) in parallel on side fixed resistance (R0) of resistive module 2, while in the fixation of resistive module 3
A NMOS tube (N3) in parallel on the side resistance (R0).The size of NMOS tube N3 is the 2 of the size (channel width) of NMOS tube N2
Times or so.The fence gate of NMOS tube N3 and N2 are all connected to vout.
When being arranged to 150 ohm of modes, resistive module 1 and resistive module 2 are connected, and resistive module 3 is forbidden.Due to
The presence of Rvddq generates pressure drop VDDQ-vddq_local on VDDQ, is converted to vout by voltage comparison module, vout with
Rvddq increases and increases, so the gate voltage of NMOS tube N2 also increases with Rvddq and is increased, the conducting resistance Ron of NMOS tube N2
Also increase with Rvddq and reduce.The resistance of resistive module 2 is equivalent to the conducting resistance Ron of fixed resistance R0 and upper N2, adds
Adjustable resistance Rx.So the resistance of resistive module 2 increases with Rvddq and is reduced.Guarantee in this way in 150 ohm of modes, resistance
Value is at 150 ohm, without changing with Rvddq.
When being arranged to 100 ohm of modes, resistive module 1 and resistive module 2 and resistive module 3 are connected.Due to Rvddq's
In the presence of generation pressure drop VDDQ-vddq_local, zooms into vout by voltage comparison module, vout increases with Rvddq on VDDQ
And increase, so the gate voltage of NMOS tube N2 also increases with Rvddq and increased, the conducting resistance Ron of NMOS tube N2 is also with Rvddq
Increase and reduces.The resistance of resistive module 2 is equivalent to the conducting resistance Ron of fixed resistance R0 and upper N2, along with adjustable resistance
Rx.So the resistance of resistive module 2 increases with Rvddq and is reduced.The gate voltage of same NMOS tube N3 also increases with Rvddq and is increased
Add, so the conducting resistance Ron of NMOS tube N3 also increases with Rvddq and reduced.The resistance of resistive module 3 is equivalent to fixed resistance
The conducting resistance Ron of R0 and upper N3, adjustable resistance Rx is added.So the resistance of resistive module 3 increases with Rvddq and is reduced.
Guarantee in this way in 100 ohm of modes, resistance value is at 100 ohm, without changing with Rvddq.
Claims (3)
1. a kind of DDR2 DRAM ODT structure for reducing electric power network Resistance Influence, including resistance configuration module, resistance adjustment mould
Several resistive modules in parallel of block and different resistance values, each resistive module is by equivalent fixed resistance R0 and different resistance values
Adjustable resistance Rx it is in series；The resistance configuration module realizes different resistive modes by the combination gating to resistive module
Formula, the resistance adjustment module based on the resistance Rvddq on maximum resistance mode tuning electric power network, i.e., gating it is described several
The resistive module R of maximum value in resistive modulemax, adjust resistance Rvddq make the standard resistance value of maximum resistance mode=
Rvddq+Rmax；It is characterized by:
The DDR2 DRAM ODT structure further includes voltage comparison module and signal conversion circuit, and voltage comparison module obtains power supply
The partial pressure of resistance Rvddq on network makes the partial pressure switch be the resistive mode with other resistance values by signal conversion circuit
The resistance value of the independent compensation resistance in parallel of fixed resistance R0 in block, the compensation resistance reduces with the increase of the partial pressure.
2. the DDR2 DRAM ODT structure according to claim 1 for reducing electric power network Resistance Influence, it is characterised in that:
The signal conversion circuit includes multiple NMOS tubes, and each NMOS tube is a pair of with the resistive module of other resistance values one respectively
It answers, each NMOS tube is in parallel with the fixed resistance R0 in corresponding resistor module；The fence gate of whole NMOS tubes connects voltage and compares mould
The output end of block.
3. the DDR2 DRAM ODT structure according to claim 2 for reducing electric power network Resistance Influence, it is characterised in that:
Several described resistive modules are first resistor module, second resistance module and 3rd resistor module, correspond respectively to 300 ohm
The fixed resistance R0 of mode, 150 ohm of modes and 100 ohm of modes, second resistance module and 3rd resistor module respectively with
NMOS tube N3 and NMOS tube N2 are in parallel, and the fence gate of NMOS tube N3 and NMOS tube N2 are connected to the output end of voltage comparison module altogether；Its
In, the size of NMOS tube N3 is 2 times of the size of NMOS tube N2.
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| CN201610792364.7A CN106356089B (en) | 2016-08-31 | 2016-08-31 | A kind of DDR2 DRAM ODT structure reducing electric power network Resistance Influence |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050096064A (en) * | 2004-03-29 | 2005-10-05 | 삼성전자주식회사 | Semiconductor integrated circuit device and on die termination circuit of this |
| CN1770322A (en) * | 2004-11-01 | 2006-05-10 | 海力士半导体有限公司 | Semiconductor memory device with on-die termination circuit |
| CN105185410A (en) * | 2015-08-14 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Reference unit with variable resistance value |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9111671B2 (en) * | 2012-05-23 | 2015-08-18 | Invensas Corporation | On-chip impedance network with digital coarse and analog fine tuning |
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- 2016-08-31 CN CN201610792364.7A patent/CN106356089B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050096064A (en) * | 2004-03-29 | 2005-10-05 | 삼성전자주식회사 | Semiconductor integrated circuit device and on die termination circuit of this |
| CN1770322A (en) * | 2004-11-01 | 2006-05-10 | 海力士半导体有限公司 | Semiconductor memory device with on-die termination circuit |
| CN105185410A (en) * | 2015-08-14 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Reference unit with variable resistance value |
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