CN106340522A - Film transistor panel structure and manufacturing method thereof - Google Patents
Film transistor panel structure and manufacturing method thereof Download PDFInfo
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- CN106340522A CN106340522A CN201610920074.6A CN201610920074A CN106340522A CN 106340522 A CN106340522 A CN 106340522A CN 201610920074 A CN201610920074 A CN 201610920074A CN 106340522 A CN106340522 A CN 106340522A
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- passivation layer
- layer
- film transistor
- metal layer
- thin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
Abstract
The invention provides a film transistor panel structure and a manufacturing method thereof. The structure comprises a first metallic layer as a scan line, a first passivation layer on the first metallic layer, an organic film on the first passivation layer, a second passivation layer on the organic film, through holes passing through the first passivation layer, the organic film and the second passivation layer, a second metallic layer which contacts with the first metallic layer through the through holes and serves as a grid electrode, a third passivation layer covering the grid electrode, a semiconductor active layer on the third passivation layer, and a third metallic layer which serves as a data line, a source electrode, a drain electrode and a pixel electrode. The distance between the two poles of a flat parasitic capacitor and a parallel parasitic capacitor in pixels can be increased, the parasitic capacitance is reduced, pixel noise is also reduced, and the pixel performance is improved.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of thin-film transistor display panel structure and manufacture method.
Background technology
The thin film transistor (TFT) face array of the thin film transistor (TFT) face array driving panel of flat faced display or x-ray sensor passes
Sensor panel can be collectively referred to as tft (thin film transistor, thin film transistor (TFT)) panel.In quasiconductor tft panel process
In, the thin film of different material is deposited over the planar surface of glass or other materials, and is patterned to various circuit with reality
Existing various functions, the driving of such as display panels, the driving of organic LED display panel, x-ray flat board detect
Sensing function of device panel etc..The elementary cell of the function of tft panel is pixel, and each pixel comprise a scan line,
One data line, film transistor switch device (being hereafter referred to as tft device).Scan line is used for controlling the switch of tft device, even
Connect the grid of tft device, data wire is used for the driving of the reading (the tft panel of detector) of pixel charge or pixel, and (flat board shows
Show the tft panel of device), connect the source-drain electrode of tft device.
Overlap capacitance between grid and source-drain electrode, scanning in overlap capacitance between scan line data line, tft device
Line is unrelated with pixel functional realiey with the parallel of the parallel capacitance of pixel electrode, scan line and public electrode or overlap capacitance etc.
Electric capacity, together form the parasitic capacitance of pixel.The moment opening and closing when scanning line traffic control tft device, the electricity of scan line
Position can occur significant change, due to the coupling effect of parasitic capacitance, in detector tft panel, the change of scan line current potential
The change in electrical charge of source-drain electrode, public electrode, pixel electrode etc. can be caused, additional noise when causing pixel charge to read, impact
Detector performance；In flat pannel display tft panel, the change of scan line current potential can cause the fluctuation of pixel potential, affects flat board
The display effect of display.
Therefore, how to reduce the pixel parasitic capacitance on tft panel has become people in the art to improve panel performance
One of member's problem demanding prompt solution.
Content of the invention
Prior art in view of the above, it is an object of the invention to provide a kind of thin-film transistor display panel structure and making
Method, for solving the problems, such as that on tft panel in prior art, pixel parasitic capacitance is larger.
For achieving the above object and other related purposes, the present invention provides a kind of thin-film transistor display panel structure, comprising:
The first metal layer, graphically as scan line；
First passivation layer, on described the first metal layer；
Organic film, on described first passivation layer；
Second passivation layer, on described organic film；
Via, through described first passivation layer, organic film and the second passivation layer, exposes described the first metal layer；
Second metal layer, on described second passivation layer, graphically as grid, and by described via with described
The first metal layer contacts；
3rd passivation layer, on described second passivation layer, and includes covering the part on described second metal layer surface；
Semiconductor active layer, is positioned on the 3rd passivation layer on described second metal layer surface；
3rd metal level, on described 3rd passivation layer, graphically as data wire, source electrode, drain electrode and pixel electricity
Pole, described source electrode and described drain electrode are located at respectively and are not in contact with each other on described semiconductor active layer, described data wire and described drain electrode
Connect, described pixel electrode is connected with described source electrode.
Preferably, described scan line is perpendicular with described data wire.
Preferably, the material of described first passivation layer and described second passivation layer is selected from silicon nitride, silicon oxide, silicon oxynitride
One or more of.
Preferably, the material of described organic film is selected from polyimides, tetrafluoroethene perfluorinated alkoxy vinyl ether altogether
One or more of polymers.
For achieving the above object and other related purposes, the present invention also provides a kind of making of thin-film transistor display panel structure
Method, comprises the following steps:
One substrate is provided, forms the first metal layer on the substrate, and graphically as scan line；
Form the first passivation layer on described the first metal layer；
Form organic film on described first passivation layer；
Form the second passivation layer on described organic film；
Make via, make described via pass through described first passivation layer, organic film and the second passivation layer, expose described the
One metal level；
Form second metal layer on described second passivation layer, and graphically as grid, described second metal layer is led to
Cross described via to contact with described the first metal layer；
Form the 3rd passivation layer on described second passivation layer, and make described 3rd passivation layer cover described second metal layer
Surface；
Form semiconductor active layer on described 3rd passivation layer covering described second metal layer surface；
Form the 3rd metal level on described 3rd passivation layer, and graphically as data wire, source electrode, drain electrode and pixel
Electrode, makes described source electrode and described drain electrode be located on described semiconductor active layer respectively and be not in contact with each other, described data wire and institute
State drain electrode to connect, described pixel electrode is connected with described source electrode.
Preferably, the material of described substrate is glass, polyimides or polyethylene terephthalate.
Preferably, graphically the method for described the first metal layer, second metal layer and the 3rd metal level is photoetching.
Preferably, the method making via is photoetching.
Preferably, make described first passivation layer and the material of described second passivation layer is selected from silicon nitride, silicon oxide, nitrogen oxygen
One or more of SiClx.
Preferably, the material making described organic film is selected from polyimides, tetrafluoroethene perfluorinated alkoxy vinyl
One or more of ether copolymer.
As described above, the thin-film transistor display panel structure of the present invention and manufacture method, have the advantages that
Scan line metal level and gate metal layer are separated film forming by the thin-film transistor display panel structure of the present invention, make scan line
The electrode spacing of the capacity plate antenna and data wire between is substantially increased, simultaneously the parallel capacitance between scan line and pixel electrode
Electrode spacing also substantially increased.The parasitic capacitance of pixel is shown due to the electrode spacing between scan line and pixel other parts
Write increase and substantially reduce, effectively reduce the capacitance coupling effect causing during scanning wiretap, reduce pixel charge and read
When noise, be conducive to the lifting of detector performance.
Brief description
Fig. 1 is shown as a kind of schematic diagram of thin-film transistor display panel structure provided in an embodiment of the present invention.
Fig. 2 is shown as a kind of schematic top plan view of thin-film transistor display panel structure provided in an embodiment of the present invention.
Fig. 3 a- Fig. 3 g is shown as a kind of signal of thin-film transistor display panel construction manufacturing method provided in an embodiment of the present invention
Figure.
Component label instructions
100 substrates
201 the first metal layers
202 second metal layers
203 the 3rd metal levels
2011 scan lines
2021 grids
301 first passivation layers
302 second passivation layers
303 the 3rd passivation layers
400 organic films
500 semiconductor active layers
600 vias
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Carry out various modifications and changes under the spirit of the present invention.It should be noted that, in the case of not conflicting, following examples and enforcement
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way
Think, then only show the assembly relevant with the present invention in schema rather than according to component count during actual enforcement, shape and size
Draw, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
In prior art, existing typical pixel design is graphically as scan line and grid with first layer metal
Pole, covers passivation layer and patterned semiconductor layer on first layer metal layer, semiconductor layer covers the patterned second layer
Metal is as data wire, source-drain electrode and pixel electrode.Because scan line data line is mutually perpendicular to, its point of intersection certainly exists one
Individual capacity plate antenna, its electrolyte is passivation layer, and its electrode spacing is passivation layer thickness.Due to the construction featuress of tft device, grid
Deposit overlapping, i.e. composition capacity plate antenna in the two-dimensional direction and source-drain electrode between, its electrolyte is passivation layer and semiconductor layer, its
Electrode spacing is the thickness sum of passivation layer and semiconductor layer.Although might not there is friendship between scan line and pixel electrode
Folded, but there is also parallel capacitance.
In order to, on the premise of not affecting pixel basic structure and performance, reduce the parasitic capacitance of pixel, the present invention proposes
A kind of new tft display pixel design scheme, scan line metal level and gate metal layer is separated film forming, sets between the two layers
Put thicker passivation layer or organic film, the electric connection between scan line metal and gate metal is realized with via.This
Scheme can make the flat board parasitic capacitance in pixel increase with two die openings of parallel parasitic capacitance, reduce parasitic capacitance, reduce
Pixel noise, improves pixel performance.
Refer to Fig. 1, the embodiment of the present invention provides a kind of thin-film transistor display panel structure, comprising:
The first metal layer 201, graphically as scan line；
First passivation layer 301, on described the first metal layer 201；
Organic film 400, on described first passivation layer 301；
Second passivation layer 302, on described organic film 400；
Via, through described first passivation layer 301, organic film 400 and the second passivation layer 302, exposes described first gold medal
Belong to layer 201；
Second metal layer 202, on described second passivation layer 302, graphically as grid, and passes through described via
Contact with described the first metal layer 201；
3rd passivation layer 303, on described second passivation layer 302, and includes covering described second metal layer 202 table
The part in face；
Semiconductor active layer 500, is positioned on the 3rd passivation layer 303 on described second metal layer 202 surface；
3rd metal level 203, on described 3rd passivation layer 303, graphically as data wire, source electrode, drain electrode and
Pixel electrode；
Wherein, as shown in Fig. 2 described source electrode 2031 and described drain electrode 2032 are located at described semiconductor active layer 500 respectively
On be not in contact with each other, described data wire 2,033 2032 is connected with described drain electrode, described pixel electrode 2034 and described source electrode 2031 company
Connect.Scan line 2011 and grid 2021 are connected by via 600.
In some embodiments of the invention, as shown in Fig. 2 described scan line 2011 is mutually hung down with described data wire 2033
Directly.
Specifically, the material of described first passivation layer 301 and described second passivation layer 302 can be selected from silicon nitride, oxidation
One or more of silicon, silicon oxynitride.
Specifically, the material of described organic film 400 is selected from pi (polyimides), pfa (tetrafluoroethene perfluoro alkoxy
One or more of vinyl ether co-polymer).
Wherein, described 3rd passivation layer 303 covers the part on described second metal layer 202 surface as gate passivation layers,
The semiconductor active layer 500 being located at thereon can be island patterns, or other suitable shapes.The present invention is to semiconductor active
Layer, grid, gate passivation layers, source electrode, the material of drain electrode and shape are not restricted, in actual applications can be according to tft device
Design choosing.
It should be noted that Fig. 1 and Fig. 2 is shown that the partial structurtes of thin-film transistor display panel, thin-film transistor display panel
The face array being made up of multiple tft devices, that is, include the source-drain electrode of multiple composition tft devices, grid and connect grid and sweep
Retouch the via of line, face array structure is that this area is known, and and therefore not to repeat here.
Refer to Fig. 3 a-3g, the embodiment of the present invention also provides the method making above-mentioned thin-film transistor display panel structure, including
Following steps:
S1 provides a substrate 100, forms the first metal layer 201 in described substrate 100, and graphically as scan line,
As shown in Figure 3 a；
S2 forms the first passivation layer 301 on described the first metal layer 201；
S3 forms organic film 400 on described first passivation layer 301；
S4 forms the second passivation layer 302 on described organic film 400, as shown in Figure 3 b；
S5 makes via, makes described via pass through described first passivation layer 301, organic film 400 and the second passivation layer
302, expose described the first metal layer 201, as shown in Figure 3 c；
S6 forms second metal layer 202 on described second passivation layer 302, and graphically as grid, described second
Metal level 202 is contacted with described the first metal layer 201, as shown in Figure 3 d by described via；
Form the 3rd passivation layer 303 on second passivation layer 302 described in s7, and make described 3rd passivation layer 303 cover institute
State second metal layer 202 surface as gate passivation layers, as shown in Figure 3 e；
S8 cover described second metal layer 202 surface described 3rd passivation layer 303 on, that is, on gate passivation layers
Form semiconductor active layer 500, as illustrated in figure 3f；
S9 forms the 3rd metal level 203 on described 3rd passivation layer 303, and graphically as data wire, source electrode, leakage
Pole and pixel electrode, make described source electrode and described drain electrode be located on described semiconductor active layer respectively and be not in contact with each other, described number
It is connected with described drain electrode according to line, described pixel electrode is connected with described source electrode, as shown in figure 3g.
Specifically, described substrate 100 can be glass, pi (polyimides), pet (polyethylene terephthalate) or
Other materials being suitable for.
Specifically, graphically the method for described the first metal layer 201, second metal layer 202 and the 3rd metal level 203 is
Photoetching or other suitable methods.
Specifically, the method making via is photoetching or other suitable methods.
Specifically, semiconductor active layer 500 can be photo-etched into island patterns or other suitable shapes.
Specifically, make described first passivation layer 301 and the material of described second passivation layer 302 is selected from silicon nitride, oxidation
One or more of silicon, silicon oxynitride.
Specifically, the material making described organic film 400 is selected from pi (polyimides), pfa (tetrafluoroethene perfluor alkane
One or more of ethoxy ethylene base ether copolymer).
In sum, scan line metal level and gate metal layer are separated into by the thin-film transistor display panel structure of the present invention
Film, makes the electrode spacing of the capacity plate antenna between scan line and data wire be substantially increased, simultaneously scan line and pixel electrode it
Between the electrode spacing of parallel capacitance also substantially increased.The parasitic capacitance of pixel is due between scan line and pixel other parts
Electrode spacing significantly increase and substantially reduce, the capacitance coupling effect that causes when effectively reducing scanning wiretap, reduce
Noise when pixel charge reads, is conducive to the lifting of detector performance.So, the present invention effectively overcomes of the prior art
Various shortcoming and have high industrial utilization.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (10)
1. a kind of thin-film transistor display panel structure is it is characterised in that include:
The first metal layer, graphically as scan line；
First passivation layer, on described the first metal layer；
Organic film, on described first passivation layer；
Second passivation layer, on described organic film；
Via, through described first passivation layer, organic film and the second passivation layer, exposes described the first metal layer；
Second metal layer, on described second passivation layer, graphically as grid, and passes through described via and described first
Metal level contacts；
3rd passivation layer, on described second passivation layer, and includes covering the part on described second metal layer surface；
Semiconductor active layer, is positioned on the 3rd passivation layer on described second metal layer surface；
3rd metal level, on described 3rd passivation layer, graphically as data wire, source electrode, drain electrode and pixel electrode, institute
State source electrode and described drain electrode be located at respectively and be not in contact with each other on described semiconductor active layer, described data wire is connected with described drain electrode,
Described pixel electrode is connected with described source electrode.
2. thin-film transistor display panel structure according to claim 1 it is characterised in that: described scan line and described data wire
Perpendicular.
3. thin-film transistor display panel structure according to claim 1 it is characterised in that: described first passivation layer and described
The material of two passivation layers is selected from one or more of silicon nitride, silicon oxide, silicon oxynitride.
4. thin-film transistor display panel structure according to claim 1 it is characterised in that: the material of described organic film is selected from
One or more of polyimides, tetrafluoroethene perfluorinated alkoxy vinyl ether copolymer.
5. a kind of manufacture method of thin-film transistor display panel structure is it is characterised in that comprise the following steps:
One substrate is provided, forms the first metal layer on the substrate, and graphically as scan line；
Form the first passivation layer on described the first metal layer；
Form organic film on described first passivation layer；
Form the second passivation layer on described organic film；
Make via, make described via pass through described first passivation layer, organic film and the second passivation layer, expose described first gold medal
Belong to layer；
Form second metal layer on described second passivation layer, and graphically as grid, described second metal layer passes through institute
State via to contact with described the first metal layer；
Form the 3rd passivation layer on described second passivation layer, and make described 3rd passivation layer cover described second metal layer table
Face；
Form semiconductor active layer on described 3rd passivation layer covering described second metal layer surface；
Form the 3rd metal level on described 3rd passivation layer, and graphical electric as data wire, source electrode, drain electrode and pixel
Pole, makes described source electrode and described drain electrode be located on described semiconductor active layer respectively and be not in contact with each other, described data wire with described
Drain electrode connects, and described pixel electrode is connected with described source electrode.
6. thin-film transistor display panel structure according to claim 5 manufacture method it is characterised in that: described substrate be glass
Glass, polyimides or polyethylene terephthalate.
7. thin-film transistor display panel structure according to claim 5 manufacture method it is characterised in that: graphically described
The method of one metal level, second metal layer and the 3rd metal level is photoetching.
8. thin-film transistor display panel structure according to claim 5 manufacture method it is characterised in that: make via side
Method is photoetching.
9. thin-film transistor display panel structure according to claim 5 manufacture method it is characterised in that: make described first
The material of passivation layer and described second passivation layer is selected from one or more of silicon nitride, silicon oxide, silicon oxynitride.
10. thin-film transistor display panel structure according to claim 5 manufacture method it is characterised in that: have described in making
The material of machine film layer is selected from one or more of polyimides, tetrafluoroethene perfluorinated alkoxy vinyl ether copolymer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019056513A1 (en) * | 2017-09-21 | 2019-03-28 | 武汉华星光电半导体显示技术有限公司 | Display panel and display apparatus |
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| US20120327321A1 (en) * | 2011-06-23 | 2012-12-27 | Appl Inc. | Display pixel having oxide thin-film transistor (tft) with reduced loading |
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