CN106328594B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN106328594B CN106328594B CN201510381679.8A CN201510381679A CN106328594B CN 106328594 B CN106328594 B CN 106328594B CN 201510381679 A CN201510381679 A CN 201510381679A CN 106328594 B CN106328594 B CN 106328594B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
A kind of forming method of transistor, it include: that the substrate with the first active area and the second active area is provided, substrate surface has dielectric layer, has the first opening for exposing the first active area of part and the second surfaces of active regions in dielectric layer, and the bottom surface of the first opening has gate dielectric layer；In the side wall and bottom surface the first work function film of formation that dielectric layer surface and first are open；Work function adjusting processing is carried out to the first work function film of the first active area, the first work function film of the first active area is made to be transformed into the second work function film；Later, the first work function film and the second work function film of dielectric layer surface are removed, the second work-function layer for being located at the first active area and the first work-function layer positioned at the second active area are formed；After work function prevention technique, the grid layer of full first opening of filling is formed in the first opening.The process simplification for forming transistor is formed by transistor performance improvement.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of forming methods of transistor.
Background technique
Static RAM (Static Random Access Memory, SRAM) is as a member in memory, tool
Have the advantages that high speed, low-power consumption are mutually compatible with standard technology, is widely used in computer, personal communication, consumption electronic product (intelligence
Can card, digital camera, multimedia player) etc. fields.
The storage unit of Static RAM includes 4T (transistor) structure and 6T (transistor) structure.For 6T static state
For the dimension cells of random access memory, comprising: the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS crystal
Pipe N1, the second NMOS transistor N2, third NMOS transistor N3 and the 4th NMOS transistor N4.Wherein, the P1 and P2 are
It pulls up transistor；The N1 and N2 is pull-down transistor；The N3 and N4 is transmission transistor.
The prior art proposes a kind of high k gold to inhibit the generation of short-channel effect while reducing grid size
Belong to grid (High K Metal Gate, abbreviation HKMG) structure transistor.In the high-k/metal gate structure transistor, using height
K (dielectric constant) dielectric material replaces the gate dielectric layers of the materials as transistor such as conventional silica, is taken using metal material
The gate electrode layers of the materials as transistor such as the polysilicon of generation routine.
Moreover, in order to adjust the threshold voltage of PMOS tube and NMOS tube, the prior art can be brilliant in PMOS transistor and NMOS
The gate dielectric layer surface of body pipe forms work-function layer (work function layer).Wherein, the work-function layer of PMOS transistor
Work function with higher is needed, and the work-function layer of NMOS transistor needs to have lower work function.Therefore, in PMOS crystalline substance
In body pipe and NMOS transistor, the work-function layer different using material is needed, to meet the needs of respective work function adjusting.
However, causing to be formed by quiet as PMOS transistor and the difference of work-function layer material needed for NMOS transistor
The performance of state random access memory is unstable.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of transistor, is capable of the forming process of simplifying transistor,
Improve the reliability and stability of transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, comprising: provide substrate, the substrate
With the first active area and the second active area, the substrate surface has dielectric layer, has in the dielectric layer and exposes part
The bottom surface of first opening of the first active area and the second surfaces of active regions, first opening has gate dielectric layer；Institute
The side wall and bottom surface for stating dielectric layer surface and the first opening form the first work function film；To the first of the first active area
Work function film carries out work function adjusting processing, and the first work function film of the first active area is made to be transformed into the second work function film, described
Second work function film is different from the work function of the first work function film；After the work function adjusts treatment process, medium is removed
The the first work function film and the second work function film of layer surface form the second work-function layer for being located at the first active area and are located at
First work-function layer of the second active area；After the work function prevention technique, is formed and filled out in first opening
Grid layer full of first opening.
Optionally, it is ion implantation technology that the work function, which adjusts treatment process,.
Optionally, it is 1E15atoms/cm that the parameter of the ion implantation technology, which includes: dosage,2~1E17atoms/cm2,
Energy is 1Kev~3Kev.
Optionally, the material of the first work function film is p-type work function material, to the first function of first active area
The ion that function film carries out ion implanting is N-type work function material ion.
Optionally, the material of the first work function film is TiN；N-type work function material ion includes aluminium ion, titanium ion
One or both of.
Optionally, the step of carrying out ion implanting to the first work function film of first active area includes: in the first function
Function film surface forms patterned layer, and the patterned layer exposes the first work function film of the first active area；With the figure
Change layer is exposure mask, carries out ion implanting to the first work function film of first active area.
Optionally, the first work function film of the dielectric layer surface and the second work function film are before forming the grid layer
Removal.
Optionally, the forming step of the grid layer and the gate dielectric layer include: before forming the first work function film,
In the side wall and bottom surface formation gate dielectric film that the dielectric layer surface and first are open；In the work function prevention
After technique, the gate electrode film of full first opening of filling is formed in first opening and on dielectric layer；Planarization institute
Gate electrode film and gate dielectric film are stated, until exposing the dielectric layer surface, forms grid layer and gate dielectric layer.
Optionally, further includes: after the first work function film and the second work function film of removal dielectric layer surface, described
First work-function layer and the second work-function layer surface form third work function film；It is removed on dielectric layer after forming grid layer
Third work function film forms third work-function layer in the first opening.
Optionally, the material of the first work function film is p-type work function material, and the material of the third work function film is
N-type work function material；The material of the first work function film is N-type work function material, and the material of the third work function film is P
Type work function material.
Optionally, the material of the first work function film is TiN, and the material of the third work function film is TiAl.
Optionally, further includes: before forming the grid layer, in the side wall and bottom surface and medium of the first opening
Barrier layer is formed on layer；The grid layer of full first opening of filling is formed in the barrier layer surface.
Optionally, the forming step of first opening includes: the first active area and the second active area in the substrate
Surface forms dummy gate structure, and the dummy gate structure includes dummy gate layer；The shape in the substrate of the dummy gate structure two sides
At source region and drain region；After forming the source region and drain region, is formed in the substrate surface and cover the dummy gate structure side
The dielectric layer of wall, the dielectric layer surface are flushed with the top surface of the dummy gate structure；The dummy gate layer is removed, in institute
It states and forms the first opening in dielectric layer.
Optionally, the source region and the forming step in drain region include: to be formed in the substrate of the dummy gate structure two sides
Stressor layers；Doped p-type ion or N-type ion in the stressor layers form source region and drain region.
Optionally, the dummy gate structure further includes the gate dielectric layer between dummy gate layer and substrate；In removal institute
After stating dummy gate layer, first open bottom exposes the gate dielectric layer.
Optionally, further includes: before forming the first work function film, formed and be isolated on the gate dielectric layer surface
Layer；The first work function film is formed in the insulation surface；The material of the separation layer is titanium nitride.
Optionally, the substrate include: substrate, the first fin positioned at substrate surface and the second fin and be located at institute
State the separation layer of substrate surface and the first fin of covering part and the second fin side wall；It is active that first fin forms first
Area；Second fin forms the second active area.
Optionally, first active area and the second active area are adjacent and arranged in parallel, adjacent first active area of substrate
And second have separation layer mutually isolated between active area；First opening is active across first active area and second
Area.
Optionally, further includes: before forming gate dielectric layer, form grid oxide layer in the bottom surface of first opening.
Optionally, the material of the gate dielectric layer is high K medium material；Before forming the first work function film,
The side wall and bottom surface of the dielectric layer surface and the first opening form gate dielectric layer；After forming the grid layer,
Remove the gate dielectric layer of the dielectric layer surface.
Compared with prior art, technical solution of the present invention has the advantage that
In forming method of the invention, work function adjusting processing is carried out by the first work function film to the first active area,
The work function for being formed by the second work function film can be made different from the first work function film, so that the function of the second work function film
Function is higher or lower than the first work function film.By the first work function film and the second work function that remove dielectric layer surface
Film, can form the second work-function layer in the first active area, form the first work-function layer in the second active area；Have when described first
The transistor types that source region and the second active area are used to form are not simultaneously as first work-function layer and the second work-function layer
Work function it is different, be used as the work-function layer of the different type transistor.It is active due to avoiding etching first
The step of area or the part of the second active area the first work function film, can guarantee to be formed after carrying out work function adjusting processing
The location and shape of first work function film and the second work function film are accurate, can be avoided the first work function film and prolong to the first active area
It stretches or the problem of the second work function film extends to the second active area.Moreover, because avoiding the first active area of etching or second having
The step of part the first work function film of source region, can be avoided the material layer positioned at the first work function film bottom and be damaged.Cause
This, the performance for being formed by transistor is stablized, and the mismatch problems of the semiconductor devices formed with the transistor are inhibited.
Further, it includes ion implantation technology that the work function, which adjusts treatment process,.When the material of the first work function film
Material is p-type work function material, and when the first work function film is used to form the work-function layer of the second active area, to described first
The ion that first work function film of active area carries out ion implanting is N-type work function material ion, such as aluminium ion.The N-type
Work function ion can drag down the work function of the first work function film, so that the work content for the second work function film that the first active area is formed
Number is lower than the first work function film, then the second work function film can be used in being formed the work-function layer of NMOS transistor, the first function
Function film can be used in being formed the work-function layer of PMOS transistor.
Further, after the first work function film and the second work function film of removal dielectric layer surface, in first function
Function layer and the second work-function layer surface form third work function film；Moreover, when the material of the first work function film is p-type function
When function material, the material of the third work function film is N-type work function material；When the material of the first work function film is N
When type work function material, the material of the third work function film is p-type work function material.The third work function film is used for and the
The work-function layer of the first active area is collectively formed in two work function films；Meanwhile by adjusting the first work function film and third work function
The work function of the second active area can be adjusted in the thickness of film, make the work content of the first work function film Yu third work function film
Number is adapted to the transistor of the second active area formation.
Detailed description of the invention
Fig. 1 to Fig. 4 is a kind of the schematic diagram of the section structure of the forming process of transistor of the embodiment of the present invention；
Fig. 5 to Figure 16 is the schematic diagram of the section structure of the forming process of another transistor of the embodiment of the present invention.
Specific embodiment
As stated in the background art, the performance of prior art Static RAM is unstable.
It finds after study, since the storage unit of Static RAM includes PMOS transistor and NMOS transistor,
And the PMOS transistor and the difference of work-function layer material needed for NMOS transistor, therefore, in depositing for Static RAM
In the forming process of storage unit, needs in the work-function layer formed in PMOS transistor and then formed in NMOS transistor
Work-function layer, or the work-function layer in the work-function layer and then formation PMOS transistor formed in NMOS transistor.So
And as the device density of Static RAM improves, the work-function layer being formed in NMOS transistor is easy to PMOS crystal
Extend in pipe, or the work-function layer being formed in PMOS transistor extends into NMOS transistor, so that being formed by static state
The performance of random access memory is unstable, so that pull up transistor is easy to happen mismatch between pull-down transistor, specifically please refers to
Fig. 1 to Fig. 4, Fig. 1 to Fig. 4 are a kind of the schematic diagram of the section structure of the forming process of transistor of the embodiment of the present invention.
Fig. 1 and Fig. 2 are please referred to, Fig. 2 is the schematic diagram of the section structure of the Fig. 1 along the direction AA ', provides substrate 100, the substrate
100 have adjacent and the arranged in parallel area PMOS 110 and NMOS area 120, have between the area PMOS 110 and NMOS area 120
Separation layer 101 is mutually isolated, and 100 surface of substrate has dielectric layer 102, has in the dielectric layer 102 and exposes part
The opening 103 on 120 surface of the area PMOS 110 and NMOS area, it is described opening 103 across the area PMOS 110, NMOS area 120 and every
101 surface of absciss layer；High-k gate dielectric layer 104 is formed in the side wall and bottom surface of 102 surface of dielectric layer and opening 103；
Coating 105 is formed on 104 surface of high-k gate dielectric layer；P-type workfunction layer 106 is formed on 105 surface of coating.
Referring to FIG. 3, Fig. 3 is consistent with the profile direction of Fig. 2, formed on 106 surface of P-type workfunction layer patterned
Photoresist layer 107, the patterned photoresist layer 107 expose the p-type function on 101 surface of NMOS area 120 and part separation layer
Function layer 106；It is exposure mask with the patterned photoresist layer 107, the P-type workfunction layer 106 of etching removal NMOS area.
Referring to FIG. 4, Fig. 4 is consistent with the profile direction of Fig. 3, etching removal NMOS area P-type workfunction layer 106 it
Afterwards, patterned photoresist layer 107 is removed；After removing patterned photoresist layer 107, in high-k gate dielectric layer 104 and P
106 surface of type work-function layer forms N-type workfunction layer 108.
As the size of transistor constantly reduces, it is formed by the thickness of P-type workfunction layer 106 and N-type workfunction layer 108
Also corresponding to be thinned, in order to reduce damage and consumption of the technique of etching P-type workfunction layer 106 to coating 105, etching removal
The etching technics of the P-type workfunction layer 106 of NMOS area is isotropic wet-etching technology.However, due to described respectively to same
The etch rate of the wet-etching technology of property in all directions is uniform, is carved on the direction perpendicular to 100 surface of substrate
While erosion, it can also be performed etching on the direction for being parallel to 100 surface of substrate.
As the device density of Static RAM improves, the spacing in the adjacent area PMOS 110 and NMOS area 120
From smaller, and described across 101 surface of the area PMOS 110, NMOS area 120 and separation layer, then the P-type workfunction layer 110
101 surface of surface and separation layer in 103 bottoms of covering the opening adjacent area PMOS 110 and NMOS area 120.Due to it is described respectively to
The etching technics of the same sex can perform etching on the direction for being parallel to 100 surface of substrate, the p-type function in etching NMOS area 120
It when function layer 106, is easy in the area PMOS 110, will be adjacent to the etching removal of part P-type workfunction layer 106 of NMOS area 120；
Moreover, also being needed after etching exposes coating 105 in order to completely remove the P-type workfunction layer 106 of NMOS area 120
Certain over etching is carried out, however, the over etching can consume the coating 105 of segment thickness, makes NMOS area 120 and PMOS
105 thickness of coating in area 110 is inconsistent, as shown in the region A in Fig. 3.It is described when being subsequently formed N-type workfunction layer 108
N-type workfunction layer 108 is easy the area covering part PMOS 110, as shown in the region B in Fig. 4.To what the area PMOS 110 was formed
Mismatch occurs between the NMOS transistor that PMOS transistor and NMOS area 120 are formed, then is formed by Static RAM
Performance is bad, bad stability.
To solve the above-mentioned problems, the present invention provides a kind of forming method of transistor.The forming method of the transistor
It include: offer substrate, the substrate has the first active area and the second active area, and the substrate surface has dielectric layer, described
There is the first opening for exposing the first active area of part and the second surfaces of active regions, the bottom of first opening in dielectric layer
Surface has gate dielectric layer；The first work function is formed in the side wall and bottom surface of the dielectric layer surface and the first opening
Film；Work function adjusting processing is carried out to the first work function film of the first active area, turns the first work function film of the first active area
Become the second work function film, the second work function film is different from the work function of the first work function film；It is adjusted in the work function
After treatment process, the first work function film and the second work function film of dielectric layer surface are removed, is formed and is located at the first active area
Second work-function layer and the first work-function layer positioned at the second active area；After the work function prevention technique,
The grid layer of full first opening of filling is formed in first opening.
Wherein, work function adjusting processing is carried out by the first work function film to the first active area, can makes to be formed by
The work function of second work function film is different from the first work function film, so that the work function of the second work function film is higher or lower than
The first work function film.By removing the first work function film and the second work function film of dielectric layer surface, can have first
Source region forms the second work-function layer, forms the first work-function layer in the second active area；When first active area and second active
The transistor types that area is used to form not simultaneously as the work function of first work-function layer and the second work-function layer is different,
It is used as the work-function layer of the different type transistor.Due to avoiding the first active area of etching or the second active area
Part the first work function film the step of, can guarantee the first work function film formed after carrying out work function adjusting processing and
The location and shape of second work function film are accurate, can be avoided the first work function film and extend to the first active area or the second work function
The problem of film extends to the second active area.Moreover, because avoiding the part first of the first active area of etching or the second active area
The step of work function film, can be avoided the material layer positioned at the first work function film bottom and be damaged.Therefore, it is formed by crystal
The performance of pipe is stablized, and the mismatch problems of the semiconductor devices formed with the transistor are inhibited.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 16 is the schematic diagram of the section structure of the forming process of the transistor of the embodiment of the present invention.
Fig. 5 and Fig. 6 are please referred to, Fig. 6 is the schematic diagram of the section structure of the Fig. 5 along the direction BB ', provides substrate 200, the substrate
200 have the first active area 201 and the second active area 202, and 200 surface of substrate has dielectric layer 203, the dielectric layer
There is the first opening 204 for exposing 202 surface of part the first active area 201 and the second active area in 203.
The substrate 200 is silicon substrate, on silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, insulator
Germanium (GOI) substrate, glass substrate or III-V compound substrate (such as silicon nitride or GaAs etc.).It is described in the present embodiment
Substrate 200 is silicon substrate.
In the present embodiment, first active area 201 is used to form NMOS transistor, and second active area 202 is used
In formation PMOS transistor.First active area 201 and the second active area 202 are adjacent and arranged in parallel, substrate 200 it is adjacent
Have separation layer 206 mutually isolated between first active area 201 and the second active area 202.
In the present embodiment, pull-down transistor of the transistor that first active area 201 is formed as SRAM device, institute
State pull-down transistor of the transistor of the second active area 202 formation as SRAM device；Adjacent 201 He of the first active area
The distance between second active area 202 is 50 nanometers~60 nanometers.
In the present embodiment, the gate structure for being formed by transistor is high-k/metal gate (High K Metal Gate, letter
Claim HKMG) structure, i.e., gate dielectric layer is formed with high K dielectric material, grid layer is formed with metal material；After the transistor uses
Grid (Gate Last) technique is formed, it is necessary first to be formed dummy gate structure, and be taken up space position for the gate structure of transistor
It sets.
It is described first opening 204 forming step include: the substrate 200 the first active area 201 and second it is active
202 surface of area forms dummy gate structure, and the dummy gate structure includes dummy gate layer；Substrate in the dummy gate structure two sides
Source region and drain region are formed in 200；After forming the source region and drain region, is formed on 200 surface of substrate and cover the puppet
The dielectric layer 203 of gate structure sidewall, 203 surface of dielectric layer are flushed with the top surface of the dummy gate structure；Removal
The dummy gate layer forms the first opening 204 in the dielectric layer.
In the present embodiment, the dummy gate structure is across first active area 201, the second active area 202 and described
Therefore separation layer 206 is formed by the first opening 204 also across first active area 201, the second active area 202 and isolation
Layer 206.
The dummy gate structure further include: positioned at the side wall of dummy gate layer sidewall surfaces；The side wall is for defining source region
With the distance between drain region and dummy gate layer；The material of the side wall is one of silica, silicon nitride, silicon oxynitride or more
Kind combination.
The dummy gate structure can also include the grid oxide layer positioned at substrate surface, and the dummy gate layer is located at the grid oxygen
Change layer surface；The material of the grid oxide layer is silica；The grid oxide layer is used for during removing dummy gate layer, protection lining
200 surface of bottom.In the present embodiment, after removing the dummy gate layer, the grid oxide layer is removed.
In another embodiment, the dummy gate structure further includes the gate medium between grid oxide layer and dummy gate layer
Layer, the material of the gate dielectric layer are high K medium material (dielectric constant is greater than 3.9)；After removing the dummy gate layer, cruelly
Expose the gate dielectric layer, the bottom surface for being formed by the first opening has gate dielectric layer.
In the present embodiment, the source region and the forming step in drain region include: the substrate in the dummy gate structure two sides
Stressor layers 305 are formed in 200；Doped p-type ion or N-type ion in the stressor layers 305 form source region and drain region.
The forming step of the stressor layers 305 includes: to form second in the substrate 200 of the dummy gate structure two sides to open
Mouthful；The stressor layers 305 of full second opening of filling, institute are formed in second opening using selective epitaxial depositing operation
The surface for stating stressor layers 305 is higher than or is flush to 200 surface of substrate.
It wherein, is silicon carbide positioned at 305 material of stressor layers of the first active area 201, positioned at the stress of the second active area 202
305 material of layer are SiGe.305 side wall of stressor layers positioned at the first active area 201 has perpendicular to 200 surface of substrate positioned at second
305 side wall of stressor layers of source region 202 and 200 surface of substrate are in " ∑ " shape, and the side wall of the stressor layers 305 has to dummy grid
The vertex that the substrate 200 of layer bottom extends.The technique of doped p-type ion or N-type ion can mix in stressor layers 305 to be in situ
General labourer's skill or ion implantation technology.
In the present embodiment, being formed by transistor is fin formula field effect transistor；The substrate 200 includes: substrate, position
In the first fin of substrate surface and the second fin and positioned at the substrate surface and the first fin of covering part and the second fin
The separation layer 206 of portion's side wall；First fin forms the first active area 201；Second fin forms the second active area
202.Wherein, the material of the substrate, the first fin and the second fin is polysilicon, and the material of the separation layer 206 is oxidation
Silicon；First fin and the second fin are arranged in parallel, and the distance between adjacent first fin and the second fin are 50 nanometers
~60 nanometers；The width of first fin is 10 nanometers~20 nanometers；The width of second fin is received for 10 nanometers~20
Rice；In the present embodiment, the width of first fin and the second fin is 14 nanometers.In other embodiments, the substrate 200
Surface it is flat, be formed by transistor be planar transistor.
Referring to FIG. 7, Fig. 7 is consistent with the profile direction of Fig. 5, in 203 surface of dielectric layer and the first opening 204
Side wall and bottom surface formed gate dielectric film 205.
The material of the gate dielectric film 205 is high K medium material；The high K medium material include hafnium oxide, zirconium oxide,
Hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide；
The material technology of the gate dielectric film 205 is chemical vapor deposition process, physical gas-phase deposition or atom layer deposition process；
The gate dielectric film 205 with a thickness of
In the present embodiment, first opening 204 exposes the first active area 201 (as shown in Figure 5) and second active
200 surface of substrate and separation layer 206 (as shown in Figure 5) surface in area 202 (as shown in Figure 5), then the gate dielectric film 205 covers
206 surface of 200 surface of substrate and separation layer of lid the first active area 201 and the second active area 202.
In one embodiment, before forming the gate dielectric film 205, additionally it is possible in the bottom of first opening 204
Surface forms grid oxide layer, forms the gate dielectric film 205 in the grid oxygen layer surface；The material of the grid oxide layer is silica,
The formation process of the grid oxide layer can be thermal oxidation technology or wet process oxidation technology；The grid oxide layer is situated between for improving the grid
Bond strength between plasma membrane 205 and substrate 200.
In another embodiment, the dummy gate structure includes the gate dielectric layer between dummy gate layer and substrate 200,
Then without forming the gate dielectric film 205 after removing dummy gate layer.
It in the present embodiment, further include in the 205 surface shape of gate dielectric film before forming the first work function film
At separation layer 206.The separation layer 206 is for preventing the material for the grid layer being subsequently formed from expanding into the gate dielectric film 205
It dissipates, guarantees the dielectric coefficient stabilization of the gate dielectric film 205 with this, make to be formed by transistor performance stabilization.The separation layer
206 material is the combination of one or both of titanium nitride, tantalum nitride；The formation process chemical vapor deposition of the separation layer 206
Product technique, physical gas-phase deposition or atom layer deposition process；The separation layer 206 with a thickness of
Referring to FIG. 8, Fig. 8 is consistent with the profile direction of Fig. 5, the first work function film is formed on 206 surface of separation layer
207。
In the present embodiment, the first work function film 207 is used to form the work-function layer of PMOS transistor, and described first
The material of work function film 207 work function with higher；Correspondingly, the first official letter film 207 is not suitable as NMOS crystal
The work-function layer of pipe.In the present embodiment, first active area 201 is used to form NMOS transistor, second active area
202 are used to form PMOS transistor, and therefore, it is necessary to adjust the work content for being located at the first work function film 207 of the first active area 201
Number, so that the first work function film 207 for being located at the first active area 201 after adjustment suitably forms NMOS transistor.
The material of the first work function film 207 is TiN；The formation process of the first work function film 207 is chemical gas
Phase depositing operation, physical gas-phase deposition or atom layer deposition process；The first work function film 207 with a thickness ofThe thickness of the first work function film 207 is unsuitable blocked up, is otherwise unfavorable for reducing the size of transistor；And institute
The thickness for stating the first work function film 207 also should not the excessively thin threshold voltage for otherwise being not enough to adjust PMOS transistor.
207 formation process of the first work function film in the present embodiment is atom layer deposition process；Using atomic layer deposition work
Skill is capable of forming the first work function film 207 with good covering power, and the first work function film 207 can be opened with first
The side wall and bottom surface of mouth 204 fit closely, and are capable of side wall and the top of good covering and the first fin and the second fin
Portion surface；Moreover, atom layer deposition process can make the thickness for being formed by the first work function film 206 uniform, make PMOS crystal
The threshold voltage adjustments ability of pipe is stablized easily-controllable.
Referring to FIG. 9, Fig. 9 is consistent with the profile direction of Fig. 6, the first work function film 207 of the first active area 201 is carried out
Work function adjusting processing, makes the first work function film 207 of the first active area 201 be transformed into the second work function film 208, and described second
Work function film 208 is different from the work function of the first work function film 207.
In the present embodiment, due to being formed by transistor for constituting SRAM device, it is close to be formed by transistor
Degree is higher, and the spacing between adjacent first active area 201 and the second active area 202 is smaller.Due to the first work function film 207
It is suitable for the work-function layer of PMOS transistor, and is not suitable as the work-function layer of NMOS transistor, it is therefore desirable to first
First work function film 207 of active area 201 is adjusted.
The first work function film 207 of the first active area 201 is removed according to etching technics, is based on the first work function film
207 thinner thickness, and the first work function film 207 is covered in the side wall and bottom surface and first of the first opening 204
The side wall and top surface of fin, the technique of the first work function film 207 of removal are wet-etching technology.However, due to and wet process
Etching technics is isotropic etching technics, and the distance between the first active area 201 and the second active area are smaller, are removing
When the first work function film 207 of the first active area 201, it is also easy to the part first on removal 202 substrate of the second active area, 200 surface
Work function film 207, then when being subsequently formed the work function film suitable for NMOS transistor, the work function film of the NMOS transistor can also
200 surface of substrate of the second active area of covering part 202, thus the threshold for the PMOS transistor for causing the second active area 202 to be formed
Threshold voltage is unstable, and is formed by NMOS transistor and PMOS transistor is easy to happen mismatch problems, is formed by SRAM device
Part performance is bad.
For the above problem, in the present embodiment, work function is carried out to the first work function film 207 of the first active area 201
Adjusting processing, makes the first work function film 207 of the first active area 201 be transformed into the second work function film 208, so as to avoid etching
The step of first work function film 207 of the first active area 201, can guarantee the first work content that processing is adjusted by work function with this
The location and shape of number film 207 and the second work function film 208 are accurate, guarantee that being formed by transistor performance stablizes with this, institute's shape
At SRAM device performance improvement.
In the present embodiment, it includes ion implantation technology that the work function, which adjusts treatment process,.To first active area 201
The first work function film 207 carry out ion implanting the step of include: 207 surface of the first work function film formed patterned layer 209,
The patterned layer 209 exposes the first work function film 207 of the first active area 201；It is exposure mask with the patterned layer 209,
Ion implanting is carried out to the first work function film 207 of first active area 201.
Wherein, the patterned layer 209 is patterned photoresist layer；The forming step of the patterned photoresist layer
It include: in 207 surface coating photoresist film of the first work function film；Development is exposed with graphical to the photoresist film, is gone
Except the photoresist film of the first active area 201.Before forming the photoresist film, additionally it is possible in the first work function film 207
Surface forms bottom layer anti-reflection layer, and the surface of the bottom layer anti-reflection layer is flat.
The parameter of the ion implantation technology includes: that dosage is 1E15atoms/cm2~1E17 atoms/cm2, energy is
1Kev~3Kev.
Energy by adjusting the ion implantation technology can control the depth of injection ion；Due to first work content
The thinner thickness of number film 207, therefore the depth of the ion implantation technology should not be too large, and otherwise be easy to inject ions into separation layer
206 or gate dielectric film 205 in.The angle vertical of the ion implanting in the top surface of the first fin and the second fin so that
The region of ion range is consistent with the region that the patterned layer 209 exposes, so as to make the position of the second work function film 208
It is accurate with shape to set, and can be avoided the second work function film 208 and extends to the second active area 202.
In the present embodiment, the material of the first work function film 207 is p-type work function material, active to described first
The ion that the first work function film 207 in area 201 carries out ion implanting is N-type work function material ion；The N-type work function material
Ion is with one or both of material ions compared with low work function, such as aluminium ion, titanium ion.
In the present embodiment, it is aluminium ion that the work function, which adjusts the ion that treatment process is injected,；Due to the work content of aluminium
Number is lower, injects aluminium ion in the first work function film 207, the work function for being formed by the second work function film 208 can be made low
In the first work function film 207, then it is formed by the second work function film 208 and is suitable for being used to form NMOS crystalline substance in the first active area 201
Body pipe.In other embodiments, the ion injected can also be other N-type work function material ions.
Figure 10, Figure 11 and Figure 12 are please referred to, Figure 11 is the schematic diagram of the section structure of the Figure 10 along the direction BB ', and Figure 12 is Figure 10
The schematic diagram of the section structure along the direction CC ', after the work function adjusts treatment process, removal is close to 204 top of the first opening
The the first work function film 207 (as shown in Figure 9) and the second work function film 208 (as shown in Figure 9) of portion's sidewall surfaces and be located at be situated between
The first work function film 207 and the second work function film 208 on 203 surface of matter layer form the second work content for being located at the first active area 201
Several layers of 208a and the first work-function layer 207a positioned at the second active area 202.
In the present embodiment, before the grid layer continued after its formation, removal is close to the first 204 top sidewall surfaces of opening
First work function film 207 and the second work function film 208 and the first work function film 207 and second positioned at 203 surface of dielectric layer
Work function film 208, with this increase it is described first opening 204 top size, make it is subsequent it is described first opening 204 in fill grid
The technique of pole film is easy to carry out, and keeps the gate electrode film inside solid being filled in the first opening 204 uniform.In other embodiments,
The first work function film 207 or the second work function film 208 close to the first 204 top sidewall surfaces of opening can also only be removed.
The step of forming the second work-function layer 208a and the first work-function layer 207a includes: in first opening
Sacrificial layer is formed in 204, the surface of the sacrificial layer is lower than 203 surface of dielectric layer；Using the sacrificial layer as exposure mask, use
Wet-etching technology etches the first work function film 207 and the second work function film 208, forms the first work-function layer 207a
With the second work-function layer 208a；After the wet-etching technology, the sacrificial layer is removed.
Wherein, the etching liquid of the wet-etching technology is SC-1 solution and SC-2 solution；The SC-1 solution includes ammonia
Water, hydrogen peroxide and water, wherein the volume ratio of ammonium hydroxide and hydrogen peroxide is 1: 20~60: 100, and the volume ratio of hydrogen peroxide and water is 60:
100~1: 300, SC-1 solution are for removing impurity particle or organic matter；The SC-2 solution include hydrogen chloride, hydrogen peroxide and
Water, wherein the volume ratio of hydrogen chloride and hydrogen peroxide is 1: 1~2: 6, and the volume ratio of hydrogen peroxide and water is 2: 6~1: 12, described
SC-2 solution is for removing metal.
Figure 13 and 14 is please referred to, Figure 13 is consistent with the profile direction of Figure 11, and Figure 14 is consistent with the direction of Figure 12, described
One work-function layer 207a and the second surface work-function layer 208a form third work function film 210.
In the present embodiment, first active area 201 is used to form NMOS transistor, the third work function film 210
For being used for the work-function layer as NMOS transistor in the first active area 201.The material of the third work function film 210 is N
The work function of type work function material, the third work-function layer 210 is lower.
In the present embodiment, 210 material of third work function film is TiAl；The formation work of the third work function film 210
Skill is chemical vapor deposition process, physical gas-phase deposition or atom layer deposition process；The thickness of the third work function film 210
Degree is
In other embodiments, when first active area 201 is used to form PMOS transistor, the third work function film
210 material is p-type work function material.
There is the second work-function layer 208a and third work function in first active area 201, first opening 204
Film 210, then the total work function of the second work-function layer 208a and third work function film 210 needs lower, to meet NMOS crystalline substance
The process requirement of body pipe.Specifically, by adjusting the thickness between the second work-function layer 208a and third work function film 210
Ratio can adjust the total work function of the second work-function layer 208a and third work function film 210.
There is the first work-function layer 207a and third work function in second active area 202, first opening 204
Film 210, then the total work function of the first work-function layer 207a and third work function film 210 needs higher, to meet PMOS crystalline substance
The process requirement of body pipe.Specifically, by adjusting the thickness between the first work-function layer 207a and third work function film 210
Ratio can adjust the total work function of the first work-function layer 207a and third work function film 210.
After forming the third work function film 210, filling full described first is formed in first opening 204 and is opened
The grid layer of mouth 204.The forming step of grid layer and gate dielectric layer will be illustrated below.
Figure 15 and Figure 16 are please referred to, Figure 15 is consistent with the profile direction of Figure 11, and Figure 16 is consistent with the profile direction of Figure 12,
Full first opening 204 of filling is formed in first opening, 204 (as shown in Figure 13 and Figure 14) and on dielectric layer 203
Gate electrode film 211.
Before forming the gate electrode film 211, on the side wall and bottom surface and dielectric layer 203 of the first opening 204
Form barrier layer；The grid layer of full first opening 204 of filling is formed in the barrier layer surface.The barrier layer is for putting
The material for setting the gate electrode film 211 expands into the first work-function layer 207a, the second work-function layer 208a and third work function film 210
It dissipates, ensure that the work function of the first work-function layer 207a, the second work-function layer 208a and third work function film 210 is stablized；
In addition, the barrier layer 212 can also be as the stop-layer of gate electrode film 211 described in subsequent planarization.The material on the barrier layer
For one or both of titanium nitride, tantalum nitride；The formation process on the barrier layer is chemical vapor deposition process, physical vapor
Depositing operation or atom layer deposition process.
The material of the gate electrode film 211 is metal；The metal includes tungsten, aluminium, copper, titanium, silver, gold, lead or nickel；The grid
The formation process of pole film 211 is physical gas-phase deposition, chemical vapor deposition process, electroplating technology or chemical plating process.
After forming the gate electrode film 211, further includes: planarization removes the gate electrode film 211, third work function film
210 and gate dielectric film 205, until exposing 203 surface of dielectric layer, form grid layer, third work-function layer and grid
Dielectric layer.The flatening process is CMP process.
In other embodiments, additionally it is possible to after the gate electrode film using flatening process removal dielectric layer surface, use
Etching technics remove dielectric layer surface third work function film and gate dielectric film, first opening in formed third work-function layer and
Gate dielectric layer.
To sum up, in the present embodiment, work function adjusting processing is carried out by the first work function film to the first active area, it can
Keep the work function for being formed by the second work function film different from the first work function film, so that the work function of the second work function film
Higher or lower than the first work function film.By removing the first work function film and the second work function film of dielectric layer surface, energy
It is enough to form the second work-function layer in the first active area, the first work-function layer is formed in the second active area；When first active area
The transistor types being used to form with the second active area are not simultaneously as the function of first work-function layer and the second work-function layer
Function is different, is used as the work-function layer of the different type transistor.Due to avoid etching the first active area or
The step of part the first work function film of second active area, can guarantee formed after carrying out work function adjusting processing first
The location and shape of work function film and the second work function film are accurate, can be avoided the first work function film extend to the first active area or
The problem of second work function film extends to the second active area.Moreover, because avoiding the first active area of etching or the second active area
Part the first work function film the step of, can be avoided the material layer positioned at the first work function film bottom and be damaged.Therefore, institute
The performance of the transistor of formation is stablized, and the mismatch problems of the semiconductor devices formed with the transistor are inhibited.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of transistor characterized by comprising
Substrate is provided, the substrate has the first active area and the second active area, and the substrate surface has dielectric layer, given an account of
There is the first opening for exposing the first active area of part and the second surfaces of active regions, the bottom table of first opening in matter layer
Face has gate dielectric layer；
In the side wall and bottom surface the first work function film of formation that the dielectric layer surface and first are open；
Work function adjusting processing is carried out to the first work function film of the first active area, turns the first work function film of the first active area
Become the second work function film, the second work function film is different from the work function of the first work function film；
After the work function adjusts treatment process, the first work function film and the second work function film of dielectric layer surface are removed,
Form the second work-function layer for being located at the first active area and the first work-function layer positioned at the second active area；
After the first work function film and the second work function film of removal dielectric layer surface, in first work-function layer and second
Work-function layer surface forms third work function film；
After the work function prevention technique, the grid of full first opening of filling is formed in first opening
Layer；
The third work function film on dielectric layer is removed after forming grid layer, forms third work-function layer in the first opening.
2. the forming method of transistor as described in claim 1, which is characterized in that the work function adjust treatment process be from
Sub- injection technology.
3. the forming method of transistor as claimed in claim 2, which is characterized in that the parameter packet of the ion implantation technology
It includes: dosage 1E15atoms/cm2~1E17atoms/cm2, energy is 1Kev~3Kev.
4. the forming method of transistor as claimed in claim 2, which is characterized in that the material of the first work function film is P
Type work function material, the ion for carrying out ion implanting to the first work function film of first active area is N-type work function material
Ion.
5. the forming method of transistor as claimed in claim 4, which is characterized in that the material of the first work function film is
TiN；N-type work function material ion includes one or both of aluminium ion, titanium ion.
6. the forming method of transistor as claimed in claim 2, which is characterized in that the first work content of first active area
The step of number film carries out ion implanting includes: to form patterned layer in the first work function film surface, and the patterned layer exposes
First work function film of the first active area；Using the patterned layer as exposure mask, to the first work function film of first active area
Carry out ion implanting.
7. the forming method of transistor as described in claim 1, which is characterized in that the first work function of the dielectric layer surface
Film and the second work function film remove before forming the grid layer.
8. the forming method of transistor as described in claim 1, which is characterized in that the grid layer and the gate dielectric layer
Forming step includes: before forming the first work function film, in the side wall and bottom of the dielectric layer surface and the first opening
Surface forms gate dielectric film；After the work function prevention technique, shape in first opening and on dielectric layer
At the gate electrode film of full first opening of filling；The gate electrode film and gate dielectric film are planarized, until exposing the dielectric layer
Until surface, grid layer and gate dielectric layer are formed.
9. the forming method of transistor as described in claim 1, which is characterized in that the material of the first work function film is P
Type work function material, the material of the third work function film are N-type work function material；The material of the first work function film is N
Type work function material, the material of the third work function film are p-type work function material.
10. the forming method of transistor as claimed in claim 9, which is characterized in that the material of the first work function film is
TiN, the material of the third work function film are TiAl.
11. the forming method of transistor as described in claim 1, which is characterized in that further include: formed the grid layer it
Before, barrier layer is formed on the side wall and bottom surface and dielectric layer of the first opening；It is formed and is filled in the barrier layer surface
The grid layer of full first opening.
12. the forming method of transistor as described in claim 1, which is characterized in that the forming step packet of first opening
It includes: forming dummy gate structure in the first active area of the substrate and the second surfaces of active regions, the dummy gate structure includes puppet
Grid layer；Source region and drain region are formed in the substrate of the dummy gate structure two sides；After forming the source region and drain region,
The substrate surface forms the dielectric layer for covering the dummy gate structure side wall, the dielectric layer surface and the dummy gate structure
Top surface flush；The dummy gate layer is removed, forms the first opening in the dielectric layer.
13. the forming method of transistor as claimed in claim 12, which is characterized in that the forming step of the source region and drain region
It include: to form stressor layers in the substrate of the dummy gate structure two sides；In the stressor layers doped p-type ion or N-type from
Son forms source region and drain region.
14. the forming method of transistor as claimed in claim 12, which is characterized in that the dummy gate structure further includes being located at
Gate dielectric layer between dummy gate layer and substrate；After removing the dummy gate layer, first open bottom exposes institute
State gate dielectric layer.
15. the forming method of transistor as described in claim 1, which is characterized in that further include: forming first work content
Before number film, separation layer is formed on the gate dielectric layer surface；The first work function film is formed in the insulation surface；It is described every
The material of absciss layer is titanium nitride.
16. the forming method of transistor as described in claim 1, which is characterized in that the substrate includes: substrate, is located at base
The first fin and the second fin of bottom surface and it is located at the substrate surface and the first fin of covering part and the second fin side
The separation layer of wall；First fin forms the first active area；Second fin forms the second active area.
17. the forming method of transistor as described in claim 1, which is characterized in that first active area and second active
Area is adjacent and arranged in parallel, has separation layer mutually isolated between adjacent first active area of substrate and the second active area；It is described
First opening is across first active area and the second active area.
18. the forming method of transistor as described in claim 1, which is characterized in that further include: formed gate dielectric layer it
Before, grid oxide layer is formed in the bottom surface of first opening.
19. the forming method of transistor as described in claim 1, which is characterized in that the material of the gate dielectric layer is high k Jie
Material；Before forming the first work function film, in the side wall and bottom table that the dielectric layer surface and first are open
Face forms gate dielectric layer；After forming the grid layer, the gate dielectric layer of the dielectric layer surface is removed.
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| CN103094214A (en) * | 2011-11-04 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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| CN103094214A (en) * | 2011-11-04 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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