CN106324476A - On-chip debug and diagnostic method, device and chip - Google Patents
On-chip debug and diagnostic method, device and chip Download PDFInfo
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- CN106324476A CN106324476A CN201510387089.6A CN201510387089A CN106324476A CN 106324476 A CN106324476 A CN 106324476A CN 201510387089 A CN201510387089 A CN 201510387089A CN 106324476 A CN106324476 A CN 106324476A
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Abstract
The present invention provides an on-chip debug and diagnostic method, a device and a chip. The method comprises the steps of monitoring the interrupt trigger information; generating a stop clock signal, a freeze signal and an interrupt trigger flag based on the interrupt trigger information; according to the stop clock signal, closing a functional clock; according to the freeze signal, freezing the state of a non-debug module port; upon monitoring the interrupt trigger flag, recording the state of an internal trigger and the internal state of a memory; after the recording is completed, recovering the function of the clock. Based on the on-chip debug and diagnostic method, the device and the chip, the functional clock can be automatically closed when the chip goes wrong, and the operation of a processor is paused. Meanwhile, the debug and diagnostic function is triggered automatically, so that the internal state of the chip can be quickly and accurately acquired. The debugging capability of the chip is effectively improved. therefore, the fault diagnosis is more rapid and the fault location is more accurate.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of sheet sand covered and diagnostic method, device and
Chip.
Background technology
Along with in contemporary integrated circuits field, the design scale of chip is increasing, complexity and integrated level are more
Coming the highest, but chip ageing also requires that more and more harsh from be designed into market, these factors make
Verify before the silicon of chip that work is difficult to fully carry out.Owing to verifying before the silicon of chip that work is insufficient, thus
The chip after flow may be caused to there is fault.For these faults, generally by the method for silicon post debugging
Debug and diagnose.
Traditional silicon post debugging method is slightly different because of the difference of chip, generally uses and makes chip be in merit
Under energy pattern (i.e. normal operation function), the method for the input and output situation of record analysis chip, logical
Cross and observe the output situation of chip to judge that chip functions is the most correct.But along with chip complexity increasingly
Height, traditional debud mode is difficult to the adjustable ability at orientation problem place, i.e. chip under many circumstances
Lowly.
In order to promote the adjustable ability of chip, researchers propose adjustable design (Design for
Debugablity, is called for short DFD) method.According to the difference of debud mode, adjustable design can divide
Be two classes: a class is the mode (Runtime-Trace type) of real-time tracing, another kind of be based on suspend and
The mode (Stop/Halt type) interrupted.The difference of two ways is, when observing chip status,
Runtime-Trace type can run chip functions；And Stop/Halt type, owing to being observed the function of part
Logic (typically functional clock) is shielded, then be unable to simultaneously perform chip functions.Stop/Halt type is adjusted
Examination structure specifically include that triggerings (Trigger) generation, clock control, state observation, breakpoint setup and
Single step etc..
In the mode of real-time tracing, observable part range is less, and chip runs and continues to fortune when makeing mistakes
OK, it is impossible to suspend.And common Stop/Halt type debud mode, chip runs when makeing mistakes, and the most still continues
Reforwarding row, it is impossible to automatic pause, and need manual unlatching to debug and diagnostic function, the method chips simultaneously
Observability and controllability the lowest.
Summary of the invention
The embodiment of the present invention provides a kind of sheet sand covered and diagnostic method, device and chip, to solve chip
Cannot automatic pause and the problem of fault diagnosis inefficiency during debugging.
On the one hand the embodiment of the present invention provides a kind of sheet sand covered and diagnostic method, including:
Monitoring down trigger information, generates according to described down trigger information and stops clock signal, freeze signal
With down trigger mark；
According to described clock signal of stopping, closing function clock, according to described freeze signal, freeze non-debugging
Module port state；
And after monitoring described down trigger mark, record internal trigger state and memory inside shape
State；
After record completes, recover described functional clock；
Described clock signal of stopping is for stopping the functional clock of chip, and described freeze signal is used for freezing described
The non-debugging module port status of chip internal, described down trigger mark represents that described chip accepts interruption
Trigger.
On the other hand the embodiment of the present invention provides a kind of sheet sand covered and the diagnostic equipment, including:
Trigger analysis and processing module, be used for monitoring down trigger information, raw according to described down trigger information
Become to stop clock signal, freeze signal and down trigger mark；
Suspend module, for stopping clock signal, closing function clock described in basis, freeze letter according to described
Number, freeze non-debugging module port status；
Logging modle, after being used for monitoring described down trigger mark, records internal trigger state and deposits
Reservoir interior state；
Recover module, for after record completes, recover described functional clock；
Described clock signal of stopping is for stopping the functional clock of chip, and described freeze signal is used for freezing described
The non-debugging module port status of chip internal, described down trigger mark represents that described chip accepts interruption
Trigger.
On the other hand the embodiment of the present invention provides a kind of chip, including: sheet sand covered as above with examine
Disconnected device, and chip body.
Sheet sand covered and diagnostic method, device and chip that the embodiment of the present invention proposes are carrying out actual debugging
Time, by monitoring down trigger information, and stop clock signal according to the generation of down trigger information, freeze letter
Number and down trigger mark so that chip run make mistakes time can automatic closing function clock, at time-out
Reason device runs；The most automatically debugging and diagnostic function are triggered such that it is able to obtain chip fast and accurately
Internal state, is effectively improved the adjustable ability of chip so that fault diagnosis is more quick, fault location
More accurate.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in embodiment being described below
The required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is this
Some bright embodiments, for those of ordinary skill in the art, are not paying creative work
Under premise, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
A kind of sheet sand covered that Fig. 1 provides for the embodiment of the present invention and the flow chart of diagnostic method；
A kind of structural representation triggering analysis and processing module that Fig. 2 provides for the embodiment of the present invention；
The structural representation of a kind of jtag port that Fig. 3 provides for the embodiment of the present invention；
A kind of sheet sand covered that Fig. 4 provides for the embodiment of the present invention and the structural representation of the diagnostic equipment.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under not making creative work premise
The every other embodiment obtained, broadly falls into the scope of protection of the invention.
On the one hand the embodiment of the present invention provides a kind of sheet sand covered and diagnostic method, is used for debugging and diagnosing core
Sheet.Chip includes sheet sand covered and diagnostic module and chip body module, and chip body module includes adjustable
Die trial block and non-debugging module.As it is shown in figure 1, the method includes:
Step 101, monitoring down trigger information, stop clock signal according to the generation of down trigger information, freeze
Knot signal and down trigger mark.
Wherein, when down trigger information is for there is mistake during chip is properly functioning, in triggering
Disconnected.I.e. when chip is in properly functioning middle appearance mistake, interruption can be triggered by down trigger information,
Suspend the operation of chip processor, facilitate technical staff to debug for the operating mistake of chip and examine
Disconnected.Optionally, down trigger information can be produced according to intercepting the operation result of processor and presupposed information
Raw, concrete, obtain when operation result and presupposed information are inconsistent, first according to the design of chip
Function and input data obtain correct chip operation information, then set according to correct chip operation information
Put corresponding presupposed information, the processor operation result of real-time sense chip, it is judged that processor operation result
The most consistent with presupposed information, if inconsistent, then generate down trigger information.Optionally, interrupt touching
Photos and sending messages can also be produced by the configuration to configuration bus, and technical staff can be as required in certain bits
Put pre-breaking so that chip runs to produce down trigger information during precalculated position.
Sheet sand covered and diagnostic module include triggering analysis and processing module, trigger in analysis and processing module monitoring
Disconnected trigger message, and stop clock signal, freeze signal and down trigger mark according to the generation of down trigger information
Will.Exemplary, as in figure 2 it is shown, trigger analysis and processing module to generate the stopping time according to down trigger information
Clock signal, freeze signal and down trigger mark.Trigger analysis and processing module include stopping clock counter,
DFD_ state machine and triggering maker, monitor down trigger information when triggering analysis and processing module, stop
Clock counter starts counting up, along with stopping the accumulative of clock counter, when being accumulated to default value,
DFD_ state machine generates corresponding state, and along with stopping persistently adding up of clock counter, DFD_ state machine enters
Row state switches, corresponding different state, triggers analysis and processing module and the most externally sends stopping time clock letter
Number, freeze signal and down trigger mark.Exemplary, monitor interruption when triggering analysis and processing module
Trigger message, stops clock counter and starts counting up, and now DFD_ state machine is original state, optionally,
When stopping clock counter and being accumulated to 10, DFD_ state machine is switched to the first state, when stopping clock count
When device continues to be accumulated to 20, DFD_ state machine is switched to the second state, continues tired when stopping clock counter
When meter is to 30, DFD_ state machine is switched to the third state, and at subsequent time, DFD_ state machine is switched to
Original state, the value stopping clock counter remains unchanged or is set to null value.When the first state is effective status
Time, clock signal will be stopped and be set to effectively, and i.e. be equivalent to externally send and stop clock signal；When the second state is
During effective status, freeze signal is set to effectively, is i.e. equivalent to externally send freeze signal；When the 3rd shape
When state is effective status, down trigger mark is set to effectively, is i.e. equivalent to externally send down trigger mark
Know.
Optionally, stop clock counter to configure by configuring bus, it is also possible to analyzed by triggering
The scan chain configuration of processing module.Chip is properly functioning there is no down trigger information time, stop clock count
The value of device keeps constant (such as null value).Exemplary, stop the parameter in clock counter and can artificially pass through
Configuration bus is preset, it is possible to when chip reset, unified with other module parameters by configuring bus
Automatically configure.Optionally, it is possible to after triggering analysis and processing module monitors down trigger information,
Automatically configure by triggering the scan chain of analysis and processing module.
Wherein, down trigger mark is used for representing that chip accepts down trigger.
Step 102, basis stop clock signal, closing function clock, according to freeze signal, freeze non-tune
Die trial block port status.
Wherein, stopping clock signal for stopping the functional clock of chip body module, freeze signal is used for freezing
The non-debugging module port status of knot chip body inside modules.
Chip body module receives stops clock signal and freeze signal, is stopped by functional clock and terminates prefetching
Behavior.During the properly functioning of chip and debugging, relate to clock control, can according to region difference
Chip body block region is divided into disparate modules: for only having single clock (functional clock) or only having
The module of functional clock and outside low-speed clock is defined as adjustable module or module to be debugged, other
Part is defined as can not debugging module or non-debugging module.For adjustable module, its functional clock according to
Triggering and analyze the clock signal of stopping that module spreads out of and carry out clock and be turned on or off, outside low speed sections is by outward
Portion controls (stop or continuing).For can not debugging module, its functional clock also responsive to trigger analyze mould
What block spread out of stops clock signal, closing function clock, and other clock parts continue to keep original state.
Step 103 after monitoring down trigger mark, record internal trigger state and memorizer
Internal state.
After sheet sand covered and diagnostic module monitor down trigger mark, start memorization COMS clip internal state.
Concrete, including record internal trigger state and memory inside state.Technical staff is remembered by analysis
Record chip to be measured internal trigger state and memory inside state can carry out location of mistake and problem is examined
Disconnected, so that it is determined that problem place.
Optionally, after sheet sand covered and diagnostic module monitor down trigger mark, sheet sand covered and diagnosis
Module configuration scan clock signal, scan chain proceeds by displacement behaviour under the control of scan clock signal
Make, scan chain removal internal trigger state and memory inside state and be recorded in depositor or
In other memory element.
Optionally, internal trigger state includes: memory scans chain flip-flop states, non-memory are swept
Retouch chain flip-flop states and all flip-flop states.
Step 104, after record completes, recover functional clock.
Optionally, before recovering functional clock, first moved by by the clock control scan chain of bus configuration
Position, moves into scan chain from scan chain input port successively by the scan chain information of above-mentioned record.Optional
, according to internal trigger difference in configuration and recovery, can deposit configuring accordingly to be divided into recovery
Reservoir scan chain trigger arrangement and recovery, non-memory scan chain trigger arrangement and recovery, all touch
Send out device configuration and recover and the configuration of debugging control chain.Wherein, debugging control chain refer in Fig. 2 for
Generate the data acquisition module of down trigger information, anticipatory data module and all of configuration bus module to touch
Send out the scan chain that device independently forms.
The sheet sand covered of embodiment of the present invention offer and diagnostic method are when carrying out actual debugging, by monitoring
Down trigger information, and stop clock signal, freeze signal and down trigger according to the generation of down trigger information
Mark so that chip run make mistakes time can automatic closing function clock, suspend processor run；With
Shi Zidong triggers debugging and diagnostic function such that it is able to obtains the internal state of chip fast and accurately, has
Effect improves the adjustable ability of chip so that fault diagnosis is more quick, and fault location is more accurate.
In order to enable those skilled in the art to be more clearly understood that the technical side that the embodiment of the present invention provides
Case, below by specific embodiment, the sheet sand covered providing embodiments of the invention and diagnostic method
It is described in detail.
Before the monitoring down trigger information of step 101 in the above-described embodiments, also include:
Monitoring triggers observation signal, opens triggering observation mode according to triggering observation signal.
Wherein, trigger observation mode and refer to the pattern for observing down trigger mark.In such a mode,
The function command of chip normal operation, until monitoring the internal down trigger information that produces, then will trigger
Information sends to triggering analysis and processing module, triggers analysis and processing module and is analyzed interrupting trigger message
And generation stops clock signal, freeze signal and down trigger mark in real time, during by closing corresponding function
Clock and access control, and make chip running status be in time-out, then according to down trigger mark, start to adjust
Examination and diagnosis.When being made without debugging and diagnosis, then without observing down trigger mark, close and touch
Send out observation mode.
Optionally, for chip power supply, after chip reset, first chip can be configured to normal function mould
Formula, after running a period of time, then switches to trigger observation mode, it is possible to directly be configured to touch by chip
Send out observation mode.
Optionally, the embodiment of the present invention provides sheet sand covered and diagnostic method are to work based on joint test
Group (Joint Test Action Group is called for short JTAG).
JTAG is a kind of international standard test protocol (IEEE 1149.1), for chip internal test and
Debugging.IEEE1149.1 standard regulation jtag port circuit includes a TAP controller and 5 TAP
The port of access, be test clock TCK, test data input TDI, test data output respectively
TDO, test pattern select TMS, test reset TRSTn.
Exemplary, as it is shown on figure 3, be a kind of based on jtag port of embodiment of the present invention offer
Debugging structural representation.Wherein, SE represents that scan enable signal, CLK represent scan clock signal.This
In embodiment, first, for chip power supply, reset signal is sent to chip, by the TMS end of JTAG
Chip is configured to trigger observation mode by mouth.Optionally, it is possible to first pass through the TMS port of JTAG by core
Sheet is configured to functional mode, after chip runs a period of time, then by the TMS port of JTAG by core
Sheet is configured to trigger observation mode.
Secondly, chip performs function, produces down trigger information, triggers analysis and processing module according to interruption
Trigger message generates and stops clock signal, freeze signal and down trigger mark, eventually through JTAG's
TDO port output down trigger mark.Wherein, down trigger information can be configured by TDI port.
The enumerator triggering analysis and processing module also can be configured by TDI port.
Again, chip receives and stops clock signal and freeze signal, is stopped by functional clock according to stopping clock signal
Only and freeze the non-debugging module port status of chip internal according to freeze signal, by the TMS of JTAG
Chip is configured to observation and logging mode, observation and the internal trigger state of memorization COMS clip and deposits by port
Reservoir interior state.Concrete, by controlling the tck clock of JTAG, control scan chain and shift
Operation, is carried out internal trigger state and the memory inside state of chip by TDO port removal
Observation and record.
Again, it is configured to recover functional clock pattern by chip by the TMS port of JTAG, passes through
Tck clock controls scan chain displacement, by the scan chain information of above-mentioned record from scan chain input port TDI
Move in scan chain successively, to carry out recovering state, and recover the functional clock of chip.
Finally, once again chip is configured to by JTAG functional mode and continues to run with follow-up function, or logical
Cross the TMS port of JTAG chip is configured to trigger observation mode to continue to run with follow-up function.This kind of feelings
Under condition, chip is without resetting, and the clock interval that down trigger again can be configured by the last time controls,
Single-step debug operation can be realized when clock interval is configured to unit clock interval.
During the debugging of said chip, carry out memory scans chain displacement by controlling TCK, can be real
Existing memory access configuration (including the control signals such as address, data, read-write enable)；By controlling TCK
Carry out memory scans chain capture, memory read/write operation can be realized；Non-memory is carried out by controlling TCK
Device scan chain shifts, and can realize the observation of non-memory sweep trigger, now observe the memorizer of module
All clocks stop；Carry out all trigger displacements by controlling TCK, the observation of all triggers can be realized,
Now observe all triggers of module and memorizer that inside can be scanned switches to shift mode, shielding to deposit
Enable write by reservoir；Carry out the displacement of debugging control chain trigger by controlling TCK, debugging control chain can be realized
Configuration.
Optionally, also by JTAG, chip is configured to debugging control chain configuration mode, with to debugging
Quality Initiative configures.
By utilizing the mutex relation between the different mode of JTAG, it then follows first configuration mode, then switch
Clock, thus ensure that clock switches steady impulse-free robustness.Such as, in order to prevent scan chain shift clock from arriving
The switching of functional clock brings fluctuation, increases and recovers functional clock pattern.Before clock switches, it is necessary to
First pass through JTAG to be configured to recover functional clock pattern, so that during configuration mode, displacement
Clock is first closed.After waiting that configuration completes, it is then turned on functional clock.Meanwhile, JTAG is used to carry out
The control of debugging signal has the advantages such as succinct, flexible, low cost with observation.
On the other hand the embodiment of the present invention provides a kind of sheet sand covered and the diagnostic equipment, as shown in Figure 4, bag
Include:
Trigger analysis and processing module 401, be used for monitoring down trigger information, raw according to down trigger information
Become to stop clock signal, freeze signal and down trigger mark；
Suspend module 402, be used for according to stopping clock signal, closing function clock, according to freeze signal,
Freeze non-debugging module port status；
Logging modle 403, after being used for monitoring down trigger mark, records internal trigger state and deposits
Reservoir interior state；
Recover module 404, for after record completes, recover functional clock；
Wherein, stopping clock signal for stopping the functional clock of chip, freeze signal is used for freezing in chip
The non-debugging module port status in portion, down trigger mark represents that chip accepts down trigger.
Optionally, this sheet sand covered and the diagnostic equipment also include:
Configuration bus module, is used for configuring down trigger information；
Data acquisition module and anticipatory data module, preset for the operation result and storage intercepting processor
Information also produces down trigger information according to described operation result and presupposed information.
Optionally, also include:
Trigger observation monitoring modular, be used for monitoring triggering observation signal, open tactile according to triggering observation signal
Send out observation mode.
Optionally, logging modle also includes:
Scan chain module, after being used for monitoring down trigger mark, controls scan clock signal and realizes scanning
Chain shifting function, the internal trigger state of writing scan chain removal and memory inside state.
Wherein, internal trigger state includes: memory scans chain flip-flop states, non-memory scan
Chain flip-flop states and all flip-flop states.
Optionally, above-mentioned sheet sand covered and the diagnostic equipment are based on JTAG.
On the other hand the embodiment of the present invention provides a kind of chip, including: sheet sand covered as above with examine
Disconnected device, and chip body.
Sheet sand covered and diagnostic method, device and chip that the embodiment of the present invention provides are carrying out actual debugging
Time, by monitoring down trigger information, and stop clock signal, freeze signal according to the generation of down trigger information
With down trigger mark so that chip run make mistakes time can automatic closing function clock, suspend processor
Run；The most automatically debugging and diagnostic function are triggered such that it is able to obtain the inside shape of chip fast and accurately
State, is effectively improved the adjustable ability of chip so that fault diagnosis is more quick, and fault location is more accurate
Really.Meanwhile, by configuring debugging breakpoints by software flexible, the life of down trigger information is set
Become position, it is achieved debugging that program is controlled and diagnostic requirements；Chip is utilized to carry scan chain to chip internal shape
State is observed and configures, and easily chip internal memorizer can be captured and be observed, be greatly improved
The observability of chip and controllability；Use debugging based on JTAG and diagnosis, it is only necessary to pass through JTAG
Port can complete whole debugging and diagnostic process, test cost is little, simple to operation, it is easy to the palm
Hold.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be repaiied by it
Change, or the most some or all of technical characteristic is carried out equivalent；And these are revised or replace
Change, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (12)
1. a sheet sand covered and diagnostic method, it is characterised in that including:
Monitoring down trigger information, generates according to described down trigger information and stops clock signal, freeze signal
With down trigger mark；
According to described clock signal of stopping, closing function clock, according to described freeze signal, freeze non-debugging
Module port state；
And after monitoring described down trigger mark, record internal trigger state and memory inside shape
State；
After record completes, recover described functional clock；
Described clock signal of stopping is for stopping the functional clock of chip, and described freeze signal is used for freezing described
The non-debugging module port status of chip internal, described down trigger mark represents that described chip accepts interruption
Trigger.
Sheet sand covered the most according to claim 1 and diagnostic method, it is characterised in that in described
Disconnected trigger message is produced by the configuration to configuration bus；Or described down trigger information is according to intercepting
Operation result and the presupposed information of processor and produce.
Sheet sand covered the most according to claim 1 and diagnostic method, it is characterised in that in monitoring
Before down trigger information, described method also includes:
Monitoring triggers observation signal, opens according to described triggering observation signal and triggers observation mode.
Sheet sand covered the most according to claim 1 and diagnostic method, it is characterised in that described also
After monitoring described down trigger mark, record internal trigger state and memory inside state bag
Include:
After monitoring described down trigger mark, control scan clock signal and realize scan chain shifting function,
The internal trigger state of writing scan chain removal and memory inside state.
Sheet sand covered the most according to claim 4 and diagnostic method, it is characterised in that in described
Portion's flip-flop states includes: memory scans chain flip-flop states, non-memory scan chain flip-flop states
With all flip-flop states.
6. according to the sheet sand covered described in any one of claim 1-5 and diagnostic method, it is characterised in that
Described sheet sand covered and diagnostic method are based on joint test working group JTAG.
7. a sheet sand covered and the diagnostic equipment, it is characterised in that including:
Trigger analysis and processing module, be used for monitoring down trigger information, raw according to described down trigger information
Become to stop clock signal, freeze signal and down trigger mark；
Suspend module, for stopping clock signal, closing function clock described in basis, freeze letter according to described
Number, freeze non-debugging module port status；
Logging modle, after being used for monitoring described down trigger mark, records internal trigger state and deposits
Reservoir interior state；
Recover module, for after record completes, recover described functional clock；
Described clock signal of stopping is for stopping the functional clock of chip, and described freeze signal is used for freezing described
The non-debugging module port status of chip internal, described down trigger mark represents that described chip accepts interruption
Trigger.
Sheet sand covered the most according to claim 7 and the diagnostic equipment, it is characterised in that described
Upper debugging and the diagnostic equipment also include:
Configuration bus module, is used for configuring described down trigger information；
Data acquisition module and anticipatory data module, preset for the operation result and storage intercepting processor
Information also produces down trigger information according to described operation result and described presupposed information.
Sheet sand covered the most according to claim 7 and the diagnostic equipment, it is characterised in that described
Upper debugging and the diagnostic equipment also include:
Trigger observation monitoring modular, be used for monitoring triggering observation signal, open according to described triggering observation signal
Open triggering observation mode.
Sheet sand covered the most according to claim 7 and the diagnostic equipment, it is characterised in that described note
Record module includes:
Scan chain module, after being used for monitoring described down trigger mark, controls scan clock signal and realizes
Scan chain shifting function, the internal trigger state of writing scan chain removal and memory inside state.
11. sheet sand covered according to claim 10 and the diagnostic equipments, it is characterised in that described
Internal trigger state includes: memory scans chain flip-flop states, non-memory scan chain trigger-like
State and all flip-flop states.
12. 1 kinds of chips, it is characterised in that including: the sheet as described in claim 7-11 is arbitrary raises
Examination and the diagnostic equipment.
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| CN109002416A (en) * | 2018-06-26 | 2018-12-14 | 北京中电华大电子设计有限责任公司 | A kind of emulator and method for supporting chip low-power consumption debugging |
| CN109271288A (en) * | 2017-07-17 | 2019-01-25 | 展讯通信（上海）有限公司 | Performance estimating method before processor silicon |
| CN109444716A (en) * | 2018-11-27 | 2019-03-08 | 中科曙光信息产业成都有限公司 | A kind of sweep test structure and method with positioning function |
| CN109857642A (en) * | 2018-12-30 | 2019-06-07 | 贝壳技术有限公司 | A kind of the block type adjustment method and debugging tool of UI automatized script |
| CN110032482A (en) * | 2019-04-11 | 2019-07-19 | 盛科网络（苏州）有限公司 | Sheet sand covered device and method |
| CN112540288A (en) * | 2020-11-30 | 2021-03-23 | 海光信息技术股份有限公司 | Method, system, device and storage medium for chip-after-silicon verification |
| CN114978965A (en) * | 2022-05-25 | 2022-08-30 | 中国第一汽车股份有限公司 | CAN diagnosis message and network message processing method and system under high-load condition of chip, electronic device and storage medium |
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| CN109002388A (en) * | 2018-07-17 | 2018-12-14 | 京信通信系统（中国）有限公司 | A kind of adjustment method and device |
| CN109002388B (en) * | 2018-07-17 | 2021-11-23 | 京信网络系统股份有限公司 | Debugging method and device |
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| CN114978965A (en) * | 2022-05-25 | 2022-08-30 | 中国第一汽车股份有限公司 | CAN diagnosis message and network message processing method and system under high-load condition of chip, electronic device and storage medium |
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |