CN106302242A - One realizes message handling system and method based on FPGA - Google Patents
One realizes message handling system and method based on FPGA Download PDFInfo
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- CN106302242A CN106302242A CN201610858493.1A CN201610858493A CN106302242A CN 106302242 A CN106302242 A CN 106302242A CN 201610858493 A CN201610858493 A CN 201610858493A CN 106302242 A CN106302242 A CN 106302242A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/52—Queue scheduling by attributing bandwidth to queues
- H04L47/527—Quantum based scheduling, e.g. credit or deficit based scheduling or token bank
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/60—Queue scheduling implementing hierarchical scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/252—Store and forward routing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9084—Reactions to storage capacity overflow
Abstract
The present invention provides a kind of and realizes message handling system based on FPGA, including message convergence module and packet forwarding module, line side port and multiple system side port, the input of described message convergence module is connected with the plurality of system side port respectively, and the outfan of described message convergence module is connected with described line side port；The input of described packet forwarding module is connected with described line side port, the outfan of described packet forwarding module is connected with the plurality of system side port respectively, described message convergence module and packet forwarding module all including, caching cutting is multi-level buffer and selects data to process width according to message flow by multi-level buffer unit, described message convergence module and packet forwarding module.Present invention also offers one and realize message processing method based on FPGA.The system structure that the present invention provides is simpler, modular design, efficiently solves data bandwidth and cache module is numerous and the equally distributed problem of internal resource.
Description
Technical field
The invention belongs to field of network communication, realize message handling system and method particularly to one based on FPGA.
Background technology
Along with the development of network technology, the extensively application of 100G high-speed interface technology brings the biggest machine to upgrading network equipment
Meeting.The interface upgrade of following application of 400G interface, chip and the equipment vendors can draw some interface problems equally.100G connects
During mouth application, port data is transmitted to internal 10G port by some application scenarios.Need to forward the data to 12 system side
10G port.FPGA realizes high-speed interface can realize the application of high-speed interface in low cost mode.But do not mate port this
In the packet switch structure of speed, FPGA faces internal complicated wiring and limits, and is often difficult to obtain normal timing results.FPGA
Internal data buffer uses block ram to realize needing a lot of block block ram use stitched together during high amount of traffic amount, with
Time data from 100G linear speed to 12 ports forward need all of data buffer storage data exchange a large amount of interconnection resource is existed
Internal local is complicated to be used.Data bandwidth and cache module numerous be FPGA 100G end with the equally distributed contradiction of internal resource
Mouth is problems faced under this type of is applied.
Summary of the invention
Goal of the invention: for the problem overcoming prior art to exist, the invention provides a kind of simple in construction, cache module
Few, internal resource equally distributed can realize message handling system based on FPGA.
Technical scheme: the invention provides and a kind of realize message handling system based on FPGA, including message convergence module and
Packet forwarding module, line side port and multiple system side port, the input of described message convergence module is many with described respectively
Individual system side port connects, and the outfan of described message convergence module is connected with described line side port；Described message forwards mould
The input of block is connected with described line side port, the outfan of described packet forwarding module respectively with the plurality of system side
Mouthful connect, described message convergence module and packet forwarding module all include multi-level buffer unit, described message convergence module and
Caching cutting is multi-level buffer and selects data to process width according to message flow by packet forwarding module.
Further, described message convergence module and packet forwarding module all include three grades of buffer units.Three grades are used to delay
Deposit and can alleviate the internal big data bandwidth of FPGA and turn to the data wiring difficulty of a lot of port.Such as 100G is transmitted to two two
The 60g caching of the low data bandwidth of level；60g Buffer forwarding gives the 30g caching of lower data bandwidth；Two end interface wirings are received step by step
Narrow and divide level, be effectively increased FPGA internal wiring efficiency；
Further, described system side port has 12, and the linear speed of each system side port is 10G, described line side port
Linear speed be 100G.
Further, in described message convergence module, first order convergence buffer unit includes that four first order converge caching list
Unit；The second level is converged buffer unit and is included that caching subelement is converged in two second level；The third level is converged buffer unit and includes one
The third level converges caching subelement；Described each first order converge caching subelement input respectively with three system side ports
Connecting, the described each two first order converges the outfan of caching subelement and converges the defeated of caching subelement respectively with a second level
Enter end to connect；The described each two second level is converged the outfan of caching subelement and is converged the input caching subelement with the third level
Connecting, the outfan that the described third level converges caching subelement new is connected with described line side port.
Further, in described packet forwarding module, first order forwarding cache unit includes a first order forwarding cache list
Unit；Second level forwarding cache unit includes two second level forwarding cache subelements；Third level forwarding cache unit includes four
Third level forwarding cache subelement；The input of described first order forwarding cache subelement is connected with line side port, the first order
Two outfans of forwarding cache subelement input with two second level forwarding cache subelements respectively is connected, and each second
The input of two outfans of level forwarding cache subelement third level forwarding cache subelement respectively connects, and each 3rd
Three outfans of level forwarding cache subelement are connected with a system side port respectively.
Present invention also offers and a kind of use the above-mentioned message processing method realizing message handling system based on FPGA, work as report
Literary composition is when line side port inputs, and the message of input, after identifying processing, is sent to packet forwarding module, packet forwarding module
Obtain the sending module being forwarded the packet to correspondence system side ports after forwarding destination interface by multi-level buffer, system side port
Sending module add message relevant information after heading, message is sent；When message inputs from system side port, message
After system side port receives, extract the relevant information in heading, connecing of message each system side port of convergence module poll
Receipts state, is sent by the message sending module of line side port after message is converged by multi-level buffer.
Further, during carrying out multi-level buffer, also include the judgement whether overflowed of every grade of buffer unit capacity,
If overflowing occurs in buffer unit capacity, then by corresponding packet loss.It is effectively increased the performance of whole method, the side of adding
The reliability of method.
Further, the identifying processing method of the message of described input is: be identified obtaining mesh to message five-tuple information
Port, or according to buffer status random assortment destination interface.The most intelligent, it is possible to carry out according to the information in message
Distribution, or direct random assortment purpose in the case of message is anomic.
Beneficial effect: compared with prior art, the present invention realizes by caching carries out the system and method for multistage cutting
The Large Copacity interface of communication equipment and the process of low capacity interface docking message.The system structure that the present invention provides is simpler
Single, modular design, efficiently solves data bandwidth and cache module is numerous and the equally distributed problem of internal resource.Simultaneously
The FPGA Development Engineering debugging time after interconnection resource is uniform is greatly shortened, and the output of whole system is more stable.
Accompanying drawing explanation
Fig. 1 is the system construction drawing of the present invention；
Fig. 2 is the structural representation of message convergence module in the present invention；
Fig. 3 is the control method flow chart of message convergence module in the present invention；
Fig. 4 is the structural representation of packet forwarding module in the present invention；
Fig. 5 is the control method flow chart of packet forwarding module in the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings the present invention is done and further explain.
As it is shown in figure 1, the one that the present invention provides realizes message handling system based on FPGA, including message convergence module and
Packet forwarding module, line side port and multiple system side port, wherein, line side port is high linear speed port, system side
Mouthful being low linear speed port, the input of message convergence module is connected with multiple system side ports respectively, message convergence module defeated
Go out end to be connected with line side port；The input of packet forwarding module is connected with line side port, the output of packet forwarding module
End is connected with multiple system side ports respectively.
As in figure 2 it is shown, the message that message convergence module uses multi-level buffer unit to be inputted by multiple system side ports converges
A message is become to export from line side port.In the present embodiment, line side port is the port of 100G linear speed, and system side port has
12, the port of respectively 10G linear speed, three grades of buffer units that message convergence module uses, wherein the first order converges caching list
Unit includes that four first order converge caching subelement, and each first order converges caching subelement and uses at 256 Bit data bit wides
Reason 30G data traffic；The second level is converged buffer unit and is included that caching subelement is converged in two second level, and each second level is converged slow
Depositing subelement uses 512 Bit data bit wides to process 60G data traffic, and the third level is converged buffer unit and includes that a third level converges
Poly-caching subelement, the third level is converged caching subelement and uses 1024 Bit data bit wides to process 120G data traffic.Each two
The input of outfan and a second level convergence caching subelement that the first order converges caching subelement connects；Each two second
Level converges caching subelement outfan and is connected with the input of third level convergence caching subelement, and the third level converges caching subelement
Outfan be connected with line side port.Wherein, every one-level can also include in converging buffer unit converging caching with each
The convergence buffer control subelement that unit is corresponding, each convergence buffer control subelement is arranged on the convergence caching subelement of correspondence
Input and upper level converge caching subelement outfan between.
The when that the message convergence module using the present invention to provide carrying out message transmission, message receives through system side port
After, extract heading, the reception state of message each system side port of convergence module poll, give message after being converged by message and send out
Send module, send via line side port.As it is shown on figure 3, message convergence module is when carrying out message and converging, the first order is converged
Poly-buffer control subelement receives the message data of three corresponding system side port inputs, and each first order converges caching control
Subunit judges that the first order of correspondence converges whether caching subelement overflows, and does not spills over if the first order converges caching subelement
Time, the first order converges buffer control subelement and message is sent to the first order convergence caching subelement of correspondence, if the first order
Converging caching subelement to overflow, the first order converges buffer control subelement will receive packet loss accordingly.Each second level is converged
The state of two first order convergence caching subelements that the inquiry of poly-buffer control subelement is corresponding, if the first order converges caching
Subelement there is message data then taken out by message and the second level is converged under conditions of caching subelement does not spills over and sent by message
Caching subelement is converged to the corresponding second level.Then second level convergence caching control is overflowed as occurred the second level to converge caching subelement
Subunit will receive packet loss.Each third level is converged each second level corresponding to buffer control subelement inquiry and converges slow
Deposit subunit state, if the second level is converged in caching subelement message data, message is taken out and converges the third level slow
Deposit and under conditions of subelement does not spills over, message is sent in third level convergence caching subelement.As occurred the third level to converge caching
Subelement overflows and is then converged, by the third level, the packet loss that buffer control subelement will receive.The third level converges caching subelement will
Message after convergence is sent to the message sending module of line side port and sends.
As shown in Figure 4, packet forwarding module uses multi-level buffer unit to be delivered to respectively by the message that line side port inputs
Corresponding system side port.In the present embodiment, line side port is the port of 100G linear speed, and system side port has 12, respectively
For the port of 10G linear speed, three grades of buffer units that packet forwarding module uses, first order forwarding cache unit includes one first
Level forwarding cache subelement, first order forwarding cache subelement uses 1024 Bit data bit wides to process 120G data traffic, the
One-level forwarding cache subelement has two outfans；Second level forwarding cache unit includes two second level forwarding cache lists
Unit, each second level forwarding cache subelement uses 512 Bit data bit wides to process 60G data traffic, second level forwarding cache
Subelement has two outfans；Third level forwarding cache unit includes four third level forwarding cache subelements, and the third level turns
Send out caching subelement use 256 Bit data bit wides process 30G data traffics, third level forwarding cache subelement have three defeated
Go out end.Two outfans of first order forwarding cache subelement are respectively with two second level forwarding cache subelement inputs even
Connecing, two outfans of each second level forwarding cache subelement control the defeated of subelement with two third level forwarding caches respectively
Entering end to connect, three outfans of each third level forwarding cache subelement are connected with a system side port respectively.Wherein, often
One-level forwarding cache unit can also including, the forwarding cache corresponding with each forwarding cache subelement controls subelement, each
Forwarding cache controls subelement and is arranged on input and the upper level forwarding cache subelement of corresponding forwarding cache subelement
Between outfan.Packet forwarding module and message converge control identical by caching cutting be three grades and according to flow selection data at
Reason width solves FPGA wiring problem.
When needing the message that line side inputs is forwarded to system side, the message of line side port input is at identification
After reason, being sent to packet forwarding module, packet forwarding module is obtained after forwarding destination interface and is forwarded the packet by multi-level buffer
To the sending module of correspondence system side ports, the sending module of system side port adds message relevant information and will report after heading
Literary composition is sent, and wherein, identifying processing is primarily to obtain the forwarding purpose of message, if by the five-tuple information identified
The forwarding purpose obtained is unique；Packet forwarding module judges corresponding system side port according to the forwarding purpose received,
Then according to forwarding purpose to carry out message transmission.
As it is shown in figure 5, packet forwarding module is when carrying out message and forwarding, first every grade of buffer unit determines forwarding mesh, first
First judge whether to comprise forwarding purpose, if comprised, message being sent to first order forwarding cache control subelement, working as the first order
When forwarding cache subelement does not spills over and include forward purpose, first order forwarding cache control subelement message is sent to first
Level forwarding cache subelement.If first order forwarding cache subelement overflows or do not includes forwarding purpose, the first order forward slow
Deposit control subelement and will receive packet loss accordingly.In first order forwarding cache unit, message is sent and according to forwarding purpose to send out
The second level forwarding cache giving correspondence controls subelement.Each second level forwarding cache controls subelement and judges that the second level forwards
Whether caching subelement overflows and forwards mesh the most correct, if second level forwarding cache subelement is not just spilling over and forwarding mesh
Really, during second level forwarding cache controls the second level forwarding cache subelement that message is sent to correspondence by subelement；As occurred
Two grades of forwarding cache subelements overflow or forward purpose mistake then to be controlled subelement by second level forwarding cache and will receive accordingly
Packet loss.Message is sent to corresponding third level forwarding cache according to forwarding purpose and controls by second level forwarding cache subelement
Subelement.Third level forwarding cache controls subelement and judges whether third level forwarding cache subelement overflows and forward mesh the most just
Really, if third level forwarding cache subelement does not spills over and forward mesh correct, third level forwarding cache controls subelement by message
It is sent in corresponding third level forwarding cache subelement；As occurred third level forwarding cache subelement to overflow or forwarding purpose mistake
Then controlled subelement by third level forwarding cache and will receive packet loss accordingly.Third level forwarding cache subelement will receive
Message be sent to the sending module of correspondence system side ports, the sending module of system side port adds message relevant information to reporting
After literary composition head, message is sent.
The system and method based on FPGA provided by the present invention can save the engineering time of 1/3rd.And generation
The amended engineering of code can stably export normally does not has the result of sequence problem.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. done, within should be included in the scope of protection of the invention.
Claims (8)
1. one kind realizes message handling system based on FPGA, it is characterised in that: include message convergence module and packet forwarding module,
Line side port and multiple system side port, the input of described message convergence module is respectively with the plurality of system side port even
Connecing, the outfan of described message convergence module is connected with described line side port；The input of described packet forwarding module and institute
Stating line side port to connect, the outfan of described packet forwarding module is connected with the plurality of system side port respectively, described report
Literary composition convergence module and packet forwarding module all including, multi-level buffer unit, described message convergence module and packet forwarding module will
Caching cutting is multi-level buffer and selects data to process width according to message flow.
The most according to claim 1 realize message handling system based on FPGA, it is characterised in that: described message convergence module
With packet forwarding module all includes three grades of buffer units.
The most according to claim 2 realize message handling system based on FPGA, it is characterised in that: described system side port has
12, the linear speed of each system side port is 10G, and the linear speed of described line side port is 100G.
The most according to claim 2 realize message handling system based on FPGA, it is characterised in that: described message convergence module
The middle first order converges buffer unit and includes that four first order converge caching subelement；The second level is converged buffer unit and is included two the
Two grades are converged caching subelement；The third level is converged buffer unit and includes that a third level converges caching subelement；Described each
One-level converges the input of caching subelement and is connected with three system side ports respectively, and the described each two first order converges caching
The outfan of unit converges the input of caching subelement respectively and is connected with a second level；The described each two second level is converged slow
The input of the outfan and third level convergence caching subelement of depositing subelement is connected, and it is new that the described third level converges caching subelement
Outfan be connected with described line side port.
The most according to claim 2 realize message handling system based on FPGA, it is characterised in that: described packet forwarding module
Middle first order forwarding cache unit includes a first order forwarding cache subelement；Second level forwarding cache unit includes two
Two grades of forwarding cache subelements；Third level forwarding cache unit includes four third level forwarding cache subelements；The described first order
The input of forwarding cache subelement is connected with line side port, two outfans of first order forwarding cache subelement respectively with
The input of two second level forwarding cache subelements connects, and two outfans of each second level forwarding cache subelement are respectively
The input of one third level forwarding cache subelement connects, and three outfans of each third level forwarding cache subelement are respectively
It is connected with a system side port.
6. using the message processing method realizing message handling system based on FPGA described in claim 1, its feature exists
In: when inputting from line side port when message, the message of input, after identifying processing, is sent to packet forwarding module, message
Forwarding module obtains the sending module being forwarded the packet to correspondence system side ports after forwarding destination interface by multi-level buffer, is
The sending module of system side ports adds message relevant information and is sent by message after heading；When message inputs from system side port
Time, message, after system side port receives, extracts heading, the reception shape of message each system side port of convergence module poll
State, is sent by the message sending module of line side port after message is converged by multi-level buffer.
The most according to claim 6 realize message processing method based on FPGA, it is characterised in that: carrying out multi-level buffer
During, also include the judgement whether overflowed of every grade of buffer unit capacity, if overflowing, then by right occurs in buffer unit capacity
The packet loss answered.
The most according to claim 6 realize message processing method based on FPGA, it is characterised in that: the message of described input
Identifying processing method is: be identified obtaining destination interface to message five-tuple information, or according to buffer status random assortment
Destination interface.
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| CN201610858493.1A CN106302242B (en) | 2016-09-28 | 2016-09-28 | One kind realizing message handling system and method based on FPGA |
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| CN201610858493.1A CN106302242B (en) | 2016-09-28 | 2016-09-28 | One kind realizing message handling system and method based on FPGA |
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| CN106302242B CN106302242B (en) | 2019-05-17 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112003992A (en) * | 2020-08-14 | 2020-11-27 | 迅镭智能（广州）科技有限公司 | Transmission system and method based on scanning gun |
| CN113836048A (en) * | 2021-09-17 | 2021-12-24 | 许昌许继软件技术有限公司 | Data exchange method and device based on FPGA memory dynamic allocation |
| CN113986794A (en) * | 2021-11-10 | 2022-01-28 | 上海鹰觉科技有限公司 | Asynchronous serial port exchange method and system based on FPGA |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130252659A1 (en) * | 2008-04-23 | 2013-09-26 | Qualcomm Incorporated | Multi-level duty cycling |
| CN103634233A (en) * | 2013-11-29 | 2014-03-12 | 华南理工大学 | Multi-level subqueue layered dispatching method for messages in communication network of transformer substation |
| CN104618266A (en) * | 2015-02-09 | 2015-05-13 | 浪潮集团有限公司 | Method and device for transferring messages among a plurality of ports |
| CN105791140A (en) * | 2014-12-19 | 2016-07-20 | 中兴通讯股份有限公司 | Message sending processing method and apparatus and network equipment |
-
2016
- 2016-09-28 CN CN201610858493.1A patent/CN106302242B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130252659A1 (en) * | 2008-04-23 | 2013-09-26 | Qualcomm Incorporated | Multi-level duty cycling |
| CN103634233A (en) * | 2013-11-29 | 2014-03-12 | 华南理工大学 | Multi-level subqueue layered dispatching method for messages in communication network of transformer substation |
| CN105791140A (en) * | 2014-12-19 | 2016-07-20 | 中兴通讯股份有限公司 | Message sending processing method and apparatus and network equipment |
| CN104618266A (en) * | 2015-02-09 | 2015-05-13 | 浪潮集团有限公司 | Method and device for transferring messages among a plurality of ports |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112003992A (en) * | 2020-08-14 | 2020-11-27 | 迅镭智能（广州）科技有限公司 | Transmission system and method based on scanning gun |
| CN113836048A (en) * | 2021-09-17 | 2021-12-24 | 许昌许继软件技术有限公司 | Data exchange method and device based on FPGA memory dynamic allocation |
| CN113986794A (en) * | 2021-11-10 | 2022-01-28 | 上海鹰觉科技有限公司 | Asynchronous serial port exchange method and system based on FPGA |
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| CN106302242B (en) | 2019-05-17 |
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