CN106301745A - The method and device of time synchronized between main control board and slave control board - Google Patents
The method and device of time synchronized between main control board and slave control board Download PDFInfo
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- CN106301745A CN106301745A CN201510269107.0A CN201510269107A CN106301745A CN 106301745 A CN106301745 A CN 106301745A CN 201510269107 A CN201510269107 A CN 201510269107A CN 106301745 A CN106301745 A CN 106301745A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
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Abstract
The invention provides the method and device of time synchronized between a kind of main control board and slave control board, wherein, the method includes: when carrying out the forwarding of accurate time synchronization protocol PTP message between decision-making goes out in master control board state main control board and slave control board, obtains multiple timestamps when sending with reception PTP message every the first Preset Time；Preset rules is used to calculate the time bias value between main control board and slave control board based on multiple timestamps；Foundation time bias value correction slave control board is relative to the time deviation of main control board.By the present invention, have employed the mode of software to realize the synchronization of time, solve and correlation technique realizes the problem that the scheme of time synchronized is with high costs.
Description
Technical field
The present invention relates to the communications field, in particular between a kind of main control board and slave control board
The method and device of time synchronized.
Background technology
Traditional Time Synchronizing is that each base station configures global positioning system (Global Positionging
System is referred to as GPS) or Beidou satellite navigation system (BeiDou Navigation Satellite System
Referred to as BD) equipment, therefore each base station needs to configure a time source, with high costs.From becoming we
Face considers, uses bearer network network to transmit the development trend that high-precision time synchronization information becomes following.With
The continuous evolution of bearing technology, time synchronization network provides the need of time synchronization information to telecommunication network operators
Ask more and more urgent.
For the problem that the scheme realizing time synchronized in correlation technique is with high costs, the most not yet propose effectively
Solution.
Summary of the invention
Present invention is primarily targeted at and time synchronized between a kind of main control board and slave control board is provided
Method and device, the problem with high costs at least to solve to realize in correlation technique the scheme of time synchronized.
According to an aspect of the invention, it is provided time synchronized between a kind of main control board and slave control board
Method, including: carry out essence between decision-making goes out in master control board state main control board and slave control board
When really time synchronization protocol PTP message forwards, obtain every the first Preset Time and send and receive described PTP
Multiple timestamps during message；Preset rules is used to calculate described main control board based on the plurality of timestamp
And the time bias value between described slave control board；According to standby master control described in described time bias value correction
Plate is relative to the time deviation of described main control board.
Further, multiple times when sending with the described PTP message of reception are obtained every the first Preset Time
Stamp includes: first in described slave control board receives the described PTP message that described main control board sends
During message, obtain described first message carries send described first message time the very first time stamp T1 with
And the second time stamp T 2 when receiving described first message；Send out to described master control borad at described slave control board
When sending the second message in described PTP message, obtain the 3rd time stamp T 3 when sending described second message；
Described slave control board receive described main control board send described PTP message in three messages time,
Obtain the 4th time stamp T 4 when sending described three message carried in described 3rd message.
Further, obtain described time bias value in the following manner to include: time-delay value=[(T2+T4)
-(T1+T3)]/2；Described time bias value=(T2-T1)-time-delay value.
Further, described method also includes: obtain the state of described master control borad every the second Preset Time,
When described master control borad is main control board and described main control board switches successfully in execution, by described primary
The state of master control borad is switched to the state of slave control board；It is slave control board and described standby at described master control borad
With master control borad when performing to switch successfully, the state of described slave control board is switched to the shape of main control board
State.
Further, the state of described main control board is switched to the state of slave control board and includes: latch institute
State main control board current time to stab, and close the transmission of the described PTP message of described main control board, and
It is slave control board state by the status modifier of described master control borad；Described second message is write described standby master
In control plate, and trigger the transmission of described second message.
Further, the state that the state of described slave control board is switched to main control board includes: latch
Described main control board current time is stabbed, and closes the transmission of the described PTP message of described slave control board,
And stop the calculating of described offset and the finishing of described time deviation and by the status maintenance of described master control borad
Change slave control board state into；Described first message and described 3rd message are write in described main control board,
And trigger described first message and the transmission of described 3rd message.
Further, described second Preset Time is less than described first Preset Time.
According to another aspect of the present invention, it is provided that between a kind of main control board and slave control board, the time is same
The device of step, including acquisition module, for decision-making goes out in master control board state main control board with standby
When carrying out the forwarding of accurate time synchronization protocol PTP message between master control borad, obtain every the first Preset Time and send out
Multiple timestamps when sending and receive described PTP message；Computing module, for based on the plurality of timestamp
Preset rules is used to calculate the time bias value between described main control board and described slave control board；Revise
Module, is used for according to slave control board described in described time bias value correction relative to described main control board
Time deviation.
Further, described acquisition module includes: the first acquiring unit, for connecing at described slave control board
When receiving the first message in the described PTP message that described main control board sends, obtain in described first message
The stamp T1 of the very first time when sending described first message carried and when receiving described first message the
Two time stamp T 2；Second acquisition unit, for sending described at described slave control board to described master control borad
During the second message in PTP message, obtain the 3rd time stamp T 3 when sending described second message；3rd obtains
Take unit, in receiving, at described slave control board, the described PTP message that described main control board sends
During three messages, obtain the 4th timestamp when sending described three message carried in described 3rd message
T4。
Further, obtain described time bias value in the following manner to include: time-delay value=[(T2+T4)
-(T1+T3)]/2；Described time bias value=(T2-T1)-time-delay value.
By the present invention, it is main control board and slave control board for state in master control borad, uses PTP report
The forwarding of literary composition, and then obtain multiple timestamps when sending with this PTP message of reception every the first Preset Time,
Calculate with the time bias between master control borad and slave control board according to the plurality of timestamp and preset rules
Value, revises the slave control board time deviation relative to main control board by this offset, it is seen that this
The bright mode of software that have employed, to realize the synchronization of time, solves the side realizing time synchronized in correlation technique
The problem that case is with high costs.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application,
The schematic description and description of the present invention is used for explaining the present invention, is not intended that the improper limit to the present invention
Fixed.In the accompanying drawings:
Fig. 1 is the method for time synchronized between main control board according to embodiments of the present invention and slave control board
Flow chart；
Fig. 2 is the device of time synchronized between main control board according to embodiments of the present invention and slave control board
Structured flowchart；
Fig. 3 be according to alternative embodiment of the present invention by PTP message realize standby, main control board time with
Step apparatus structure block diagram；
Fig. 4 is the T1 according to alternative embodiment of the present invention, the schematic diagram of T2, T3, T4 time stamp generation mechanism；
Fig. 5 is the flow chart of the original state control method according to alternative embodiment of the present invention；
Fig. 6 is 1 second timer-operated flow chart according to alternative embodiment of the present invention；
Fig. 7 is 100 milliseconds of timer-operated flow charts according to alternative embodiment of the present invention.
Detailed description of the invention
It should be noted that in the case of not conflicting, the embodiment in the application and the feature in embodiment
Can be mutually combined.Describe the present invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
Can be in the department of computer science of such as one group of computer executable instructions in the step shown in the flow chart of accompanying drawing
System performs, and, although show logical order in flow charts, but in some cases, permissible
To be different from the step shown or described by order execution herein.
Present embodiments provide the method for time synchronized, Fig. 1 between a kind of main control board and slave control board
It is the flow chart of the method for time synchronized between main control board according to embodiments of the present invention and slave control board,
As it is shown in figure 1, the step of the method includes:
Step S102: carry out accurate time synchronization protocol between decision-making goes out in master control board state main control board and slave control board
When (Precision Time Protocol is referred to as PTP) message forwards, obtain every the first Preset Time and send and receive
Multiple timestamps during PTP message；
Step S104: based on multiple timestamps use preset rules calculate main control board and slave control board it
Between time bias value；
Step S106: foundation time bias value correction slave control board is relative to the time deviation of main control board.
By above-mentioned steps S102 in the present embodiment to step S106, it is primary master for state in master control borad
Control plate and slave control board, uses the forwarding of PTP message, so every the first Preset Time obtain send with
Receive multiple timestamps during this PTP message, calculate with main according to the plurality of timestamp and preset rules
Time bias value between control plate and slave control board, revises slave control board relative to master by this offset
By the time deviation of master control borad, it is seen that the present embodiment have employed the mode of software to realize the synchronization of time, solve
Correlation technique realizes the problem that the scheme of time synchronized is with high costs.
Obtain when sending with reception PTP message every the first Preset Time for what the present embodiment related to
The mode of multiple timestamps, in an optional embodiment of the present embodiment, can come real in the following way
Existing:
Step S11: slave control board receive main control board send PTP message in the first message time,
Obtain the stamp T1 of the very first time when sending the first message carried in the first message and receiving the first message
Time the second time stamp T 2；
Step S12: when slave control board sends the second message in PTP message to master control borad, obtain and send
The 3rd time stamp T 3 during the second message；
Step S13: slave control board receive main control board send PTP message in three messages time,
Obtain the 4th time stamp T 4 when sending three messages carried in the 3rd message.
Based on above-mentioned timestamp, time bias value can be obtained in the following manner and include:
Time-delay value=[(T2+T4)-(T1+T3)]/2；
Time bias value=(T2-T1)-time-delay value.
It should be noted that the above-mentioned mode obtaining time bias value based on timestamp, it is intended merely to lift
Example explanation, other are also the protection models in the present invention by the way of obtaining timestamp and obtain time bias value
Within enclosing.
In another optional embodiment of the present embodiment, the method for the present embodiment can also also include:
Step S22: every second Preset Time obtain master control borad state, master control borad be main control board and
The state of main control board, when performing to switch successfully, is switched to the state of slave control board by main control board；
Step S23: when master control borad is slave control board and slave control board switches successfully in execution, by standby
The state of master control borad is switched to the state of main control board.
Wherein, the state of the main control board in step S22 is switched to the mode of the state of slave control board, can
To be achieved in that latch main control board current time stamp, and close the PTP of main control board
The transmission of message, and be slave control board state by the status modifier of master control borad；Second message is write standby master
In control plate, and trigger the transmission of the second message.
The mode of the state that the state of slave control board is switched to main control board in step S23, in this reality
The mode executing example can be achieved in that latch main control board current time stamp, and closes standby
The transmission of the PTP message of master control borad, and stop the calculating of offset and the finishing of time deviation and by main
The status modifier of control plate is slave control board state；First message and the 3rd message are write in main control board,
And trigger the first message and the transmission of the 3rd message.
For above-mentioned steps S22 and step S23, in an application scenarios of the present embodiment, may is that master control
Plate master turn standby during, latch current time stamp, software the PTP message closing this PTP port sends,
The amendment of PTP port status is switched to slave state simultaneously.By CPU in advance by delay_req message format
In write FPGA depositor, and start transmission delay_req message.
Master control borad is standby to be turned in primary process, latches current time stamp, software closes this PTP port PTP message
Transmission, and dwell time deviation calculate and drift correction.This PTP port status is revised as master simultaneously.
In advance sync and delay_resp message format is write in FPGA depositor by CPU, and start sync
And delay_resp message sends.
Furthermore, it is necessary to explanation, pre-less than first for the second Preset Time related in the present embodiment
If the time.Such as, this second Preset Time can be 100 milliseconds, and the first Preset Time is 1 second, certainly
Preset for first and the second value preset, be merely illustrative here, can carry out according to practical situation
Corresponding value.
Additionally provide the device of time synchronized between a kind of main control board and slave control board in the present embodiment,
This device is used for realizing above-described embodiment and preferred implementation, has carried out repeating no more of explanation.As with
Lower used, term " module " " unit " can realize the software of predetermined function and/or the combination of hardware.
Although the device described by following example preferably realizes with software, but hardware, or software and hardware
The realization of combination also may and be contemplated.
Fig. 2 is the device of time synchronized between main control board according to embodiments of the present invention and slave control board
Structured flowchart, as in figure 2 it is shown, this device includes: acquisition module 22, for decision-making in master control board state
When carrying out the forwarding of accurate time synchronization protocol PTP message between the main control board and the slave control board that go out, often
Multiple timestamps when sending with reception PTP message are obtained every the first Preset Time；Computing module 24, and obtains
Delivery block 22 is of coupled connections, for using preset rules to calculate main control board with standby based on multiple timestamps
Time bias value between master control borad；Correcting module 26, is of coupled connections with computing module 24, when foundation
Between offset correction slave control board relative to the time deviation of main control board.
Alternatively, acquisition module 22 includes: the first acquiring unit, for receiving primary master at slave control board
Control plate send PTP message in the first message time, obtain the first message carries send the first message
Time the very first time stamp T1 and receive the first message time the second time stamp T 2；Second acquisition unit, uses
In time sending the second message in PTP message at slave control board to master control borad, when obtaining transmission the second message
The 3rd time stamp T 3；3rd acquiring unit, for receiving, at slave control board, the PTP that main control board sends
During three message in message, obtain the 4th timestamp when sending three messages carried in the 3rd message
T4。
Alternatively, obtain time bias value in the following manner to include: time-delay value=[(T2+T4)-
(T1+T3)]/2；Time bias value=(T2-T1)-time-delay value.
Alternatively, this device can also include: the first handover module, main for obtaining every the second Preset Time
The state of control plate, when master control borad is main control board and main control board switches successfully in execution, by primary master
The state of control plate is switched to the state of slave control board；Second handover module, being used at master control borad is standby master control
The state of slave control board, when performing to switch successfully, is switched to the shape of main control board by plate and slave control board
State.
Alternatively, this first handover module, it is used for latching main control board current time stamp, and closes primary master
The transmission of the PTP message of control plate, and be slave control board state by the status modifier of master control borad；By Secondary Report
In literary composition write slave control board, and trigger the transmission of the second message.
This second handover module, is used for latching main control board current time stamp, and closes slave control board
The transmission of PTP message, and stop the calculating of offset and the finishing of time deviation and by the state of master control borad
It is revised as slave control board state；First message and the 3rd message are write in main control board, and triggers first
Message and the transmission of the 3rd message.
The present invention is illustrated by the alternative embodiment below in conjunction with the present invention；
This alternative embodiment provides a kind of by Precision Time Protocol (Precision Time ProTocol abbreviation
For PTP) message realizes standby, the method for main control board time synchronized.
This alternative embodiment in order to realize slave control board follow the tracks of primary master clock, it is ensured that active and standby plate be
System reference clock is identical, by the most virtual for primary, spare master control borad two the PTP ports mutual for PTP protocol,
Physical circuit can be regarded as full symmetric, meet PTP protocol and use condition.Therefore by primary master control
Plate invents a master port, and slave control board invents a slave port, uses on master control borad
Ethernet exchanging processes chip transmission PTP protocol message, software calculate slave according to PTP protocol algorithm
Hold the deviation relative to master end, and then be adjusted.Visible alternative embodiment need not support BMC
Therefore algorithm, only need to need not structure according to the master/slave state of master control board state configuration port
Announce message is held consultation the master/slave state of port.
Fig. 3 be according to alternative embodiment of the present invention by PTP message realize standby, main control board time with
Step apparatus structure block diagram, as it is shown on figure 3, main control board includes with slave control board: Ethernet exchanging
Processing unit, CPU processing unit and field programmable gate array (Field-Programmade GaTe Array letter
It is referred to as FPGA) processing unit；
The function of this Ethernet exchanging processing unit is processed chip by special Ethernet exchanging or CPU completes
PTP message forward process, and identify type of message, complete the PTP message between primary, spare plate and forward,
It should be noted that in this alternative embodiment the packet congestion time be negligible, therefore can regard main as
Message sending and receiving between the control active and standby FPGA of plate process, and time delay is little, and the synchronization accuracy obtained is high.
This CPU processing unit, for after master control borad competitive decision goes out primary, spare state, creates virtual
PTP port, completes basic parameter configuration.Wherein, at master end, structure needs the sync report sent
Literary composition (Synchronous PackeT, sync message) and delay_resp message (Delay RequesT PackeT,
Latency request message)；At slave port, structure needs delay_req message (the Delay RequesT sent
PackeT, time delay response message), and write FPGA processing unit depositor, and enable the transmission of each message.
This CPU process be additionally operable to slave end from FPGA processing unit depositor obtain T1, T2, T3,
T4 timestamp, calculates the time deviation relative to main control board according to algorithm, and it is single to write FPGA process
Metalogic enumerator, thus realize following the tracks of the requirement of main control board timestamp.
Fig. 4 is the T1 according to alternative embodiment of the present invention, the schematic diagram of T2, T3, T4 time stamp generation mechanism,
As shown in Figure 4, T1, T2, T3, T4 time stamp are read in intervalometer timing in 1 second from FPGA, and complete
OffseT calculates and writes the FPGA deadline and synchronizes, and specifically, at master transmitting terminal, timing arrives,
Stamped T1 time stamp in messages by FPGA processing unit and send Sync message.At slave receiving terminal, by FPGA
Receive Sync message, beat message and receive time stamp T2, and extract time stamp T1 in messages.Additionally receiving
After sync message, FPGA sends delay_req message immediately, stamps T3 time stamp.Receive at master
End, is received delay_req message by FPGA, records time stamp T4；And T4 time stamp is inserted delay_resp
Message passes to slave；At slave receiving terminal, FPGA receive delay_resp message, extract time stamp
T4；Therefore slave end FPGA processing unit can extract T1, T2, T3, T4 time stamp, at CPU
Reason unit calculates time deviation.
This alternative embodiment also relates to another kind of intervalometer, 100 milliseconds of intervalometers, these 100 milliseconds of intervalometers
For real time polling master control borad main and backup status, switch PTP port status according to main and backup status change and join
Put, and in master control reversed process, only latch the timestamp before switching the double master of master control borad or double standby state, stop
Only time deviation calculates and drift correction.
Wherein, CPU processing unit uses a 100ms intervalometer, active and standby for real time polling master control borad
State.If this plate is currently main board, main board is switched, and is not fully complete if switched, and continues to determine whether
Switch；Otherwise switch, be switched to standby plate state, obtained time bias value.If this plate is currently
Being standby plate, standby master control detects switches, and switches and be not fully complete, and continues to determine whether to switch；
Otherwise switch, obtained time bias value.
Wherein, master control borad master turn standby during, latch current time stamp, software close this PTP port
PTP message sends, and the amendment of PTP port status is switched to slave state simultaneously.In advance will by CPU
In delay_req message format write FPGA depositor, and start transmission delay_req message.
Master control borad is standby to be turned in primary process, latches current time stamp, software closes this PTP port PTP message
Transmission, and dwell time deviation calculate and drift correction.This PTP port status is revised as master simultaneously.
In advance sync and delay_resp message format is write in FPGA depositor by CPU, and start sync
And delay_resp message sends.
By above-mentioned alternative embodiment, active and standby master control borad is physically entirely bidirectional symmetry,
Therefore PTP protocol can be applied in active and standby plate time synchronized.Process chip by Ethernet exchanging to carry out
PTP message forwards, and carries out PTP message negotiation, has been used for master control borad active and standby plate time tracking function.
Below in conjunction with the accompanying drawings this alternative embodiment is described in detail；
Fig. 5 is the flow chart of the original state control method according to alternative embodiment of the present invention, as it is shown in figure 5,
The step of the method includes:
Step S502: master control borad powers on；
Step S504: judge whether main control board, performs step S506, is sentencing when judged result is for being
When disconnected result is no, perform step S508；
Step S506: the PTP master port of main control board configuration agreement port numbers；
Step S508: the PTP slave port of slave control board configuration agreement port numbers.
It should be noted that the main control board in this alternative embodiment, one port status of default configuration is
Master PTP port.Configure basic PTP port basic parameter, use one-step method, use Ethernet message envelope
Dress form, message sends the sync report that interval uses the default parameters of PTP protocol definition, structure to need to send
Literary composition and delay_resp message format.
The basic parameter configuration of this PTP port is as follows:
Delay measurements mode: one-step method；
PTP protocol bag form: 1588OverETH；
Sync message sends and is spaced: 0, one sync bag of transmission per second；
Source port ID: the port id allocated in advance；
CPU preserves configuration data and the state of this PTP port, for this PTP port of intervalometer poll time
Stamp.Structure needs sync message and the delay_resp message format sent, and writes FPGA depositor in advance.
Slave control board, configures a PTP port, and port status is slave, configures basic PTP port base
This parameter, uses one-step method to use Ethernet message encapsulation format, and message sends interval and uses PTP protocol definition
Default parameters, configure port identification information.Delay_req message format is previously written FPGA by CPU and posts
In storage.
The basic parameter configuration of this PTP port is as follows:
Delay measurements mode: one-step method；
PTP protocol bag form: 1588OverETH；
Delay_req message sends and is spaced: 1, transmission per second 2 bag；
Source port ID: the port id allocated in advance；
CPU processing unit preserves configuration data and the state of this PTP port, for this PTP of intervalometer poll
The time stamp of port.Structure needs the delay_req message format sent, CPU write into FPGA in advance and deposit
Device.
Fig. 6 is 1 second timer-operated flow chart according to alternative embodiment of the present invention, as shown in Figure 6, and should
Control includes:
Step S602:1 second timer time arrives；
Step S604: judge whether slave control board；When judged result is for being, perform step S606,
When judged result is no, terminate；
Step S606: read T1, T2, T3, T4 timestamp from PFGA processing unit；
Step S608: calculate time offset offset, and write FPGA.
In control flow in above-mentioned Fig. 6, slave end from FPGA processing unit depositor obtain T1, T2,
T3, T4 time stamp, calculates the time deviation relative to main control board according to algorithm, and writes FPGA process
Cellular logic enumerator, thus realize following the tracks of the requirement of main control board timestamp.Wherein, FPGA processes single
Unit realizes a 1MS intervalometer, sends out according to the PTP message transmission frequency timing of CPU processing unit configuration
Send PTP message.In order to realize quickly measuring, the transmitting-receiving of delay delay strategy message is the most respectively by active and standby master
The FPGA of control plate realizes.FPGA processing unit realizes a 1MS intervalometer, is sending port, FPGA
PTP message transmission frequency timing according to the configuration of CPU processing unit sends PTP message, beats corresponding time stamp.
At receiving terminal, FPGA filters and solves the PTP message of this port, extracts corresponding time stamp.
CPU processing unit safeguards a 1S intervalometer, if this plate is main board, does not make any process, this master
Plate is standby plate and is not switch status, and the PTP slave port that poll is made an appointment reads from FPGA
Time stamp T 1, T2, T3 and T4；According to following two expression formula, calculate the value of Delay Yu OffseT.
Delay=[(T2+T4)-(T1+T3)]/2
OffseT=(T2-T1)-Delay
Computed in software OffseT, writes FPGA processing unit by the OffseT calculated, FPGA revises
Slave control board, from the time, reaches the purpose of time synchronized.
Fig. 7 is 100 milliseconds of timer-operated flow charts according to alternative embodiment of the present invention, as it is shown in fig. 7,
This control flow includes:
Step S702:100ms timer time arrives；
Step S704: judge the most primary；Perform step S706 when being judged as YES, be judged as NO
Time, perform step S714；
Step S706: judge whether that master turns standby, when judged result is for being, perform step S708；Judging
Result terminates when being no；
Step S708: close PTP message；
Step S710: judge whether that master turns standby and completes, perform step S712 when judged result is for being；Sentencing
When disconnected result is no, perform step S704；
Step S712: the PTP slave port of standby configuration agreement port numbers, then terminates；
Step S714: judge whether standby turn of master, when judged result is for being, perform step S716, judging
When result is no, terminate；
Step S716: close PTP message；
Step S718: judge whether that standby tuberculosis completes；When being judged as YES, perform step S720, judging
When result is no, perform step S714；
Step S720: the PTP slave port of standby configuration agreement port, then terminates.
During control in figure 7 above, clock software needs to use a 100ms intervalometer, for real
Time poll master control borad main and backup status, software completes switching and the phase of PTP port status according to main and backup status
The process that should configure.If this plate is currently main board, main board is switched, and is not fully complete if switched, and continues
Judge whether to switch；Otherwise switch, be switched to standby plate state, obtained time bias value.If this plate is worked as
Before be standby plate, standby master control detects switches, and switches and be not fully complete, and continues to determine whether to switch；
Otherwise switch, obtained time bias value；Wherein, master control borad master turns standby state, and software needs to close and is somebody's turn to do
The PTP message of PTP port sends.Turn for completing if main, then the amendment of PTP port status is switched to slave
State.In advance delay_req message format is write in FPGA depositor by CPU, and start transmission
Delay_req message.Master control borad is standby turns major state, and software is first shut off the transmission of this PTP port PTP message.
And the calculating of deviation of holding the clock and drift correction.If standby turning has been led, then by this PTP port status
It is revised as master.In advance sync and delay_resp message format is write in FPGA depositor by CPU,
And start the transmission of sync and delay_resp message.
Visible, can effectively realize slave control board by this alternative embodiment and follow the tracks of the function of main control board time.
Those skilled in the art are it should be appreciated that embodiments of the invention can be provided as method, system or meter
Calculation machine program product.Therefore, the present invention can use hardware embodiment, software implementation or combine software and
The form of the embodiment of hardware aspect.And, the present invention can use and wherein include calculating one or more
The computer-usable storage medium of machine usable program code (includes but not limited to disk memory and optical memory
Deng) form of the upper computer program implemented.
The present invention is with reference to method, equipment (system) and computer program according to embodiments of the present invention
Flow chart and/or block diagram describe.It should be understood that can be by computer program instructions flowchart and/or side
Flow process in each flow process in block diagram and/or square frame and flow chart and/or block diagram and/or the knot of square frame
Close.Can provide these computer program instructions to general purpose computer, special-purpose computer, Embedded Processor or
The processor of other programmable data processing device is to produce a machine so that by computer or other can
The instruction that the processor of programming data processing equipment performs produces for realizing in one flow process or multiple of flow chart
The device of the function specified in flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions may be alternatively stored in and can guide computer or other programmable data processing device
In the computer-readable memory worked in a specific way so that be stored in this computer-readable memory
Instruction produces the manufacture including command device, and this command device realizes at one flow process of flow chart or multiple stream
The function specified in journey and/or one square frame of block diagram or multiple square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, makes
Sequence of operations step must be performed to produce computer implemented process on computer or other programmable devices,
Thus the instruction performed on computer or other programmable devices provides for realizing in one flow process of flow chart
Or the step of the function specified in multiple flow process and/or one square frame of block diagram or multiple square frame.
Above are only the alternative embodiment of the present invention, be not limited to the present invention, for this area
For technical staff, the present invention can have various modifications and variations.All within the spirit and principles in the present invention,
Any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (10)
1. the method for a time synchronized between main control board and slave control board, it is characterised in that including:
Precise time is carried out between decision-making goes out in master control board state main control board and slave control board
When synchronous protocol PTP message forwards, obtain every the first Preset Time and send and receive described PTP message
Time multiple timestamps；
Preset rules is used to calculate described main control board and described standby master based on the plurality of timestamp
Time bias value between control plate；
According to slave control board described in described time bias value correction relative to described main control board time
Between deviation.
Method the most according to claim 1, it is characterised in that obtain every the first Preset Time and send and connect
Multiple timestamps when receiving described PTP message include:
In described slave control board receives the described PTP message that described main control board sends first
During message, obtain the stamp of the very first time when sending described first message carried in described first message
T1 and the second time stamp T 2 when receiving described first message；
When described slave control board sends the second message in described PTP message to described master control borad, obtain
Take the 3rd time stamp T 3 when sending described second message；
In described slave control board receives the described PTP message that described main control board sends the 3rd
During message, obtain the 4th timestamp when sending described three message carried in described 3rd message
T4。
Method the most according to claim 2, it is characterised in that obtain described time bias in the following manner
Value includes:
Time-delay value=[(T2+T4)-(T1+T3)]/2；
Described time bias value=(T2-T1)-time-delay value.
Method the most according to claim 2, it is characterised in that described method also includes:
Obtain the state of described master control borad every the second Preset Time, be main control board at described master control borad
And described main control board is when performing to switch successfully, is switched to standby by the state of described main control board
The state of master control borad；
When described master control borad is slave control board and described slave control board switches successfully in execution, by institute
The state stating slave control board is switched to the state of main control board.
Method the most according to claim 4, it is characterised in that the state of described main control board is switched to standby
Include by the state of master control borad:
Latch described main control board current time stamp, and close the described PTP report of described main control board
The transmission of literary composition, and be slave control board state by the status modifier of described master control borad；
Described second message is write in described slave control board, and triggers the transmission of described second message.
Method the most according to claim 4, it is characterised in that the state of described slave control board is switched to
The state of main control board includes:
Latch described main control board current time stamp, and close the described PTP report of described slave control board
The transmission of literary composition, and stop the calculating of described offset and the finishing of described time deviation and by described master
The status modifier of control plate is slave control board state；
Described first message and described 3rd message are write in described main control board, and triggers described the
One message and the transmission of described 3rd message.
Method the most according to claim 4, it is characterised in that described second Preset Time is less than described first
Preset Time.
8. the device of a time synchronized between main control board and slave control board, it is characterised in that including:
Acquisition module, between main control board and the slave control board that decision-making goes out in master control board state
When carrying out the forwarding of accurate time synchronization protocol PTP message, obtain every the first Preset Time and send and receive
Multiple timestamps during described PTP message；
Computing module, for using preset rules to calculate described main control board based on the plurality of timestamp
And the time bias value between described slave control board；
Correcting module, is used for according to slave control board described in described time bias value correction relative to described master
By the time deviation of master control borad.
Device the most according to claim 8, it is characterised in that described acquisition module includes:
First acquiring unit, for receiving described in the transmission of described main control board at described slave control board
During the first message in PTP message, obtain described first message carries sending described first message
Time the very first time stamp T1 and receive described first message time the second time stamp T 2；
Second acquisition unit, for sending described PTP message at described slave control board to described master control borad
In the second message time, obtain send described second message time the 3rd time stamp T 3；
3rd acquiring unit, for receiving described in the transmission of described main control board at described slave control board
During three message in PTP message, obtain described 3rd message carries sending described 3rd message
Time the 4th time stamp T 4.
Device the most according to claim 9, it is characterised in that obtain described time bias in the following manner
Value includes:
Time-delay value=[(T2+T4)-(T1+T3)]/2；
Described time bias value=(T2-T1)-time-delay value.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510269107.0A CN106301745A (en) | 2015-05-22 | 2015-05-22 | The method and device of time synchronized between main control board and slave control board |
| PCT/CN2015/092571 WO2016188026A1 (en) | 2015-05-22 | 2015-10-22 | Time synchronization method and device between primary main board and standby main board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510269107.0A CN106301745A (en) | 2015-05-22 | 2015-05-22 | The method and device of time synchronized between main control board and slave control board |
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| CN106301745A true CN106301745A (en) | 2017-01-04 |
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| CN201510269107.0A Withdrawn CN106301745A (en) | 2015-05-22 | 2015-05-22 | The method and device of time synchronized between main control board and slave control board |
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| CN (1) | CN106301745A (en) |
| WO (1) | WO2016188026A1 (en) |
Cited By (1)
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| CN106851817A (en) * | 2017-02-20 | 2017-06-13 | 成都物梦工场信息技术有限公司 | A kind of high-accuracy clock synchronization method between base station |
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| CN113162813B (en) * | 2020-01-22 | 2022-06-03 | 烽火通信科技股份有限公司 | PTP message loss detection analysis method and device |
| CN112311621B (en) * | 2020-10-15 | 2022-05-24 | 新华三技术有限公司合肥分公司 | Communication detection method and device |
| CN113839816B (en) * | 2021-09-23 | 2024-01-19 | 新华三信息安全技术有限公司 | Wiring device and fault switching method thereof |
| CN114598639B (en) * | 2022-01-28 | 2023-12-26 | 新华三技术有限公司合肥分公司 | Message processing method and device |
| CN116436555B (en) * | 2023-06-09 | 2023-08-18 | 新华三技术有限公司 | Time synchronization method and device and distributed network equipment |
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| WO2016188026A1 (en) | 2016-12-01 |
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