CN106301241A - Charge-domain voltage signal amplifying circuit and use the testing circuit of this amplifying circuit - Google Patents

Abstract

The present invention provides a novel voltage small signal amplifying circuit to replace the high power consumption small voltage signal amplifying circuit based on an operational amplifier. The charge domain voltage small signal amplifying circuit includes: two charge storage nodes, one connected to two charge a charge transfer control switch between the storage nodes, a first capacitor connected to the first charge storage node, a capacity programmable capacitor connected to the second charge storage node, a first voltage transfer switch connected to the first charge storage node, A second voltage transfer switch connected to the first charge storage node, a third voltage transfer switch connected to the second charge storage node, and a fourth voltage transfer switch connected to the second charge storage node. The charge-domain voltage small-signal amplifying circuit can be widely used in detection and amplifying systems of various voltage signals.

Description

Charge domain voltage signal amplifying circuit and detection circuit using the amplifying circuit

technical field

The invention relates to a small signal processing circuit, in particular to a small signal amplifying circuit using charge domain signal processing technology.

Background technique

With the continuous development of digital signal processing technology, the digitization and integration of electronic systems is an inevitable trend. In any electronic system, the detection and amplification of analog small signals is an important link. With the increasing requirements for energy conservation and environmental protection, the energy consumption of small signal detection and amplification processing circuits should be further optimized. Especially in portable terminal products, the power consumption should be minimize.

The existing small signal amplifying circuit is mainly based on an operational amplifier, which has a non-inverting input terminal and an inverting input terminal. The polarity of the input terminal and the output terminal are the same polarity, which is a non-inverting amplifier, and the polarity of the input terminal and the output terminal are opposite polarity. It is called an inverting amplifier. As shown in Figure 1, it is a commonly used voltage inversion amplifier circuit, because the voltage at the input terminal of the op amp is zero, and because the non-inverting input terminal is grounded, it can be concluded that the inverting input terminal is actually grounded. This means that all input voltage Vi is across resistor R1 and all output voltage Vo is across resistor R2. Therefore, the sum of the currents flowing into the inverting input terminal is Vi/R1+Vo/R2=0, ie Vo=-R2/R1*Vi. Therefore, the voltage gain is G=-(R2/R1), which is the negative of the resistance of the feedback resistor divided by the resistance of the input resistor. Fig. 2 is a schematic diagram of a commonly used voltage detection amplifier circuit with a larger magnification, which is formed by cascading two stages of the circuit shown in Fig. 1, and the voltage gain is G=(R2/R1) ² .

The work of the above-mentioned voltage amplification detection amplifier circuit completely depends on the negative feedback of the operational amplifier to ensure the speed of signal amplification. For an ideal operational amplifier, the accuracy of the amplifier circuit depends on the ratio of resistor R2/R1. In the actual circuit, the gain and bandwidth of the operational amplifier are limited, which depends on the gain-bandwidth product of the operational amplifier, and the high-gain and large-bandwidth operational amplifier circuit requires a lot of power consumption, so a new type of voltage small signal amplifier circuit is designed to replace the high The voltage small-signal amplifying circuit based on the op amp that consumes power is of great practical significance.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide a novel low-power voltage small-signal amplifying circuit that does not use a high-gain operational amplifier.

The purpose of the present invention can be achieved through the following technical solutions:

A charge-domain voltage small-signal amplifying circuit is characterized in that it includes two charge storage nodes, a charge transmission control switch connected between the two charge storage nodes, a first capacitor connected to the first charge storage node, and a A capacitance programmable capacitor to the second charge storage node, a first voltage transfer switch connected to the first charge storage node, a second voltage transfer switch connected to the first charge storage node, a second voltage transfer switch connected to the second charge storage node three voltage transfer switches and a fourth voltage transfer switch connected to the second charge storage node;

The connection relationship of the charge domain voltage small signal amplifying circuit is as follows: one end of the first capacitor is connected to the first charge storage node, and the other end is connected to the charge transfer control clock Clk; one end of the capacitance programmable capacitor is connected to the second charge storage node node, the other end is connected to the charge transfer control clock Clkn; the control end of the charge transfer control switch is connected to the transfer signal Clkt, and the two ends of the charge transfer control switch are connected to the first and second charge storage nodes; one end of the first voltage transfer switch is connected to To the first charge storage node, the other end is connected to the reference voltage 1, the switch control signal is connected to Clkr; one end of the second voltage transmission switch is connected to the first charge storage node, the other end is connected to the input voltage Vi, and the switch control signal is connected to Clks; One end of the third voltage transmission switch is connected to the second charge storage node, the other end is connected to the reference voltage 2, and the switch control signal is connected to Clkr; one end of the fourth voltage transmission switch is connected to the second charge storage node, and the other end is connected to the output voltage Vo, switch control signal connected to Clkt.

The charge-domain voltage small-signal amplifying circuit is characterized in that: after completing a voltage amplification, the relationship between the output voltage and the input voltage is a linear relationship in which the amplification factor is -C ₃₀₂ /C ₃₀₅ , wherein: C ₃₀₂ and C ₃₀₅ are respectively The capacitance value of the programmable capacitor for the first capacitor and the capacitance value.

A circuit using a charge domain voltage small signal amplifying circuit for signal detection, characterized by comprising: a sensor, a charge domain voltage small signal amplifying circuit, an analog-to-digital converter and a control circuit; the use of a charge domain voltage small signal amplifying circuit to perform The connection relationship of the signal detection circuit is: the output voltage of the sensor is connected to the input voltage port of the charge domain voltage small signal amplifying circuit, the output voltage port of the charge domain voltage small signal amplifying circuit is connected to the analog voltage input port of the analog-to-digital converter, The quantization code output end of the analog-to-digital converter is connected to the digital code input end of the control circuit, the first control signal generation port output clock Clkr of the control circuit is to the Clkr clock input port of the charge domain voltage small signal amplifying circuit, and the second control circuit The control signal generation port outputs the clock Clks to the Clks clock input port of the charge domain voltage small signal amplifying circuit, the third control signal generation port output clock Clk of the control circuit is connected to the Clk clock input port of the charge domain voltage small signal amplifying circuit, and the control circuit The fourth control signal generation port output clock Clkn to the Clkn clock input port of the charge domain voltage small signal amplifying circuit, the fifth control signal generation port output clock Clkt of the control circuit to the Clkt clock input port of the charge domain voltage small signal amplifying circuit and the analog The data output control terminal of the digital converter.

A method for using a charge domain voltage small signal amplifying circuit for signal detection, characterized in that: firstly, the first control signal of the control circuit generates a port output clock Clkr to control the state of the charge domain voltage small signal amplifying circuit to reset; secondly, control The second control signal generation port of the circuit outputs the clock Clks to control the charge domain voltage small signal amplifying circuit to sample the sensor input voltage signal; again, the fourth and fourth control signal generation ports of the control circuit simultaneously output clocks Clk and Clkn to control the charge domain The voltage small signal amplifying circuit amplifies the sampled voltage signal to obtain the output voltage; finally, the fifth control signal of the control circuit generates the port output clock Clkt to control the charge domain voltage small signal amplifying circuit to output the output voltage to the analog-to-digital converter, controlling The fifth control signal generating port of the circuit also outputs a clock Clkt to control the analog-to-digital converter to perform analog-to-digital conversion on the received voltage and output the converted quantization code to the digital code input terminal of the control circuit.

The invention has the advantages that the designed small-signal amplifying circuit does not use a high-gain operational amplifier, and has the characteristics of low power consumption and high speed.

Description of drawings

FIG. 1 is a schematic diagram of the principle of an existing small voltage signal detection and amplification circuit.

Fig. 2 is a schematic diagram of the principle of an existing cascaded voltage small signal detection and amplification circuit.

FIG. 3 is a schematic diagram of a charge-domain voltage small-signal amplifying circuit of the present invention.

Fig. 4 is a working waveform diagram of the charge-domain voltage small-signal amplifying circuit of the present invention.

FIG. 5 is a circuit block diagram of the present invention using a charge-domain voltage small-signal amplifying circuit for signal detection.

detailed description

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 3 is a schematic diagram of a charge-domain voltage small-signal amplifying circuit of the present invention. The charge domain voltage small signal amplifying circuit includes: two charge storage nodes Ni and No, a charge transfer control switch 301 connected between the two charge storage nodes, a first capacitor 302 connected to the first charge storage node Ni, a connection Capacitance programmable capacitor 305 to the second charge storage node No, first voltage transfer switch 303 connected to the first charge storage node Ni, second voltage transfer switch 304 connected to the first charge storage node Ni, connected to the second charge storage node Ni, The third voltage transfer switch 307 of the second charge storage node No and the fourth voltage transfer switch 306 connected to the second charge storage node No.

The connection relationship of the above circuit is: one end of the first capacitor is connected to the first charge storage node, and the other end is connected to the charge transfer control clock Clk; one end of the capacitance programmable capacitor 305 is connected to the second charge storage node, and the other end is connected to the The charge transfer control clock Clkn; the control end of the charge transfer control switch is connected to the transfer signal Clkt, and the two ends of the charge transfer control switch are connected to the first and second charge storage nodes Ni and No; one end of the first voltage transfer switch 303 is connected to the first voltage transfer switch 303 One charge storage node, the other end is connected to the reference voltage 1Vr1, the switch control signal is connected to Clkr; one end of the second voltage transmission switch 304 is connected to the first charge storage node, the other end is connected to the input voltage Vi, and the switch control signal is connected to Clks; One end of the three-voltage transfer switch 307 is connected to the second charge storage node, the other end is connected to the reference voltage 2Vr2, and the switch control signal is connected to Clkr; one end of the fourth voltage transfer switch 306 is connected to the second charge storage node, and the other end is connected to the output Voltage Vo, switch control signal connected to Clkt.

The working waveform schematic diagram of the charge domain voltage small signal amplifier circuit is shown in Fig. 4 . The control clocks Clk and Clkn are clocks with opposite phases, and the switch control signals Clkr, Clks and Clkt are clocks with non-overlapping phases. Before time t0, independent charges are stored on the first and second charge storage nodes Ni and No, all voltage transfer switches and charge transfer control switches are in the off state, and the circuit is inactive.

When time t0 arrives, the state of Clkr changes, Clkr switches from low level to high level, the first voltage transmission switch 303 and the third voltage transmission switch 307 are turned on; the first charge storage node Ni is transmitted by the first voltage The switch is reset to the reference voltage 1Vr1; the second charge storage node No is reset to the reference voltage 2Vr2 by the third voltage transfer switch.

When time t1 arrives, the states of Clkr and Clks change, Clkr becomes low level, and Clks switches from low level to high level; the first voltage transmission switch 303 and the third voltage transmission switch 307 are turned off, and the second The voltage transfer switch 304 is turned on; the first charge storage node Ni is connected to the input voltage Vi by the second voltage transfer switch; the second charge storage node No keeps Vr2 unchanged.

When time t2 arrives, the states of the control clocks Clks, Clk and Clkn change, Clks becomes low level, Clkn switches from low level to high level, and Clk switches from high level to low level. The charge stored on the capacitors 302 and 305 connected to each charge storage node will not change abruptly, the voltages on the first and second charge storage nodes Ni and No will undergo a step change, and the voltage on the first charge storage node Ni will is pulled low, and the voltage on the second charge storage node No is pulled high, because there is no discharge path for the charges on the first and second charge storage nodes Ni and No at this time, the first and second charge storage nodes Ni The voltage on and No will remain constant and there will be a significant voltage difference.

When time t3 arrives, the switch control signal Clkt of the charge transfer control switch becomes high level, the charge transfer control switch 301 is turned on, and a charge discharge path exists between the first and second charge storage nodes Ni and No, Since there is an obvious voltage difference between the voltages on the first and second charge storage nodes Ni and No at this time, that is, V _Ni is smaller than V _No , the existence of this voltage difference will cause the voltage difference between the first and second charge storage nodes Ni and No An induced electric field is generated between the first and second charge storage nodes Ni and No to transfer the charges stored on the first and second charge storage nodes Ni and No under the action of the induced electric field. Assuming that the charges move in the form of electrons, the movement direction of the electrons is determined by the first charge The storage node Ni moves toward the second charge storage node No, causing the voltage of the first charge storage node Ni to increase, and the voltage of the second charge storage node No to decrease, and the voltage difference between the two charge storage nodes continues to increase with the continuous transfer of charges. decreases, causing the induced electric field between the first and second charge storage nodes Ni and No to gradually decrease, the charge transfer speed decreases continuously, and the voltage change rate also decreases accordingly. If the charge transfer control switch 301 is always on, then The charge transfer process will continue until the voltages between the first and second charge storage nodes Ni and No are equal, and the induced electric field is zero.

With the arrival of time t4, Clkt becomes low level, the charge transfer control switch 301 is turned off, the charge discharge path between the first and second charge storage nodes Ni and No is disconnected, and the first and second charge The charge transfer operation between the storage nodes Ni and No ends. Since there is no bleeding path, the voltages on the first and second charge storage nodes Ni and No will remain unchanged. The transfer of charges from the first charge storage node Ni to the second charge storage node No is completed.

In the above process, if there is no loss in the charge transmission process, assuming that the capacitance values of the first capacitor and the programmable capacitor are C ₃₀₂ and C ₃₀₅ respectively, the charge flowing out of the first charge storage node Ni is Q _i =C ₃₀₂ * ΔVi, the charge injected into the second charge storage node No is Q _o =C ₃₀₅ *ΔVo, and Q _i =C ₃₀₂ *ΔVi=Q _o =C ₃₀₅ *ΔVo. According to the principle of charge conservation, charge is effectively transferred between t ₁ and t ₄ , and the charge Q _S sent out on C ₃₀₂ is calculated.

Q _S ＝C ₃₀₅ ·(V _o -V _P )＝[(V _r1 -V _i )-(V _S -V _L )]·C ₃₀₂ (1)

After finishing, we can get:

Q _S ＝-V _i ·C ₃₀₂ +Q _T (2)

Among them, Q _T ＝(V _L +V _r1 -V _S )·C ₃₀₂ , V _L , V _P and V _S are all fixed voltages, V _L is the voltage at Ni point before t3, V _P is the voltage of No before t3 The voltage at point; V _S is the voltage at Ni point at t4. After the circuit is designed, the disturbance caused by the change of the reference voltage is ignored, and Q _T is a constant. Since Q _S =C ₃₀₂ *ΔVi=C ₃₀₅ *ΔVo, then:

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 302</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 305</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}\\ <span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 302</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 305</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 302</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 305</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

The first item in formula (3) is the linear relationship of capacitance ratio, and the last two items are fixed values. It can be seen that after the voltage transmission is completed, the relationship between the output voltage and the input voltage is a linear relationship with an amplification factor of -C ₃₀₂ /C ₃₀₅ . That is, the ratio of the output voltage change to the input voltage change is the ratio of the first capacitor to the capacitance of the programmable capacitor. By setting the ratio of the two capacitors, the amplification factor of the output voltage signal to the input voltage signal can be precisely controlled. And if the charge is transferred in the form of positive charge, it only needs to change the direction of the voltage difference between the charge transfer nodes during the charge transfer process.

After performing differential processing on the circuit shown in Figure 3, QT in formula (2 ₎ will be eliminated, resulting in the following formula:

Q _S,diff ＝-[V _in -V _ip ]·C ₃₀₂ (4)

V _Non -V _Nop ＝-[V _in -V _ip ]·C ₃₀₂ /C ₃₀₅ (5)

After the voltage transmission is completed, the relationship between the output voltage and the input voltage is also a linear relationship with an amplification factor of -C ₃₀₂ /C ₃₀₅ .

The charge transmission control switch described in the present invention can be realized by the implementation method described in the invention patent with the invention number 201010291245.6, and the voltage transmission switch can be realized by a general MOS transistor or a BJT switch.

FIG. 5 is a circuit block diagram of the present invention using a charge-domain voltage small-signal amplifying circuit for signal detection. Its circuit structure includes: sensor, charge domain voltage small signal amplifying circuit, analog-to-digital converter (ADC) and control circuit. The connection relationship of the circuit is: the output voltage Vi of the sensor is connected to the input voltage port of the charge domain voltage small signal amplifying circuit, the output voltage port of the charge domain voltage small signal amplifying circuit is connected to the analog voltage input port of the analog-to-digital converter, and the modulus The quantized code output end of the converter is connected to the digital code input end of the control circuit, the first control signal of the control circuit generates the port output clock Clkr to the Clkr clock input port of the charge domain voltage small signal amplifying circuit, and the second control signal of the control circuit Generate the port output clock Clks to the Clks clock input port of the charge domain voltage small signal amplifying circuit, the third control signal of the control circuit generates the port output clock Clk to the Clk clock input port of the charge domain voltage small signal amplifying circuit, and control the fourth of the circuit Control signal generation port output clock Clkn to the Clkn clock input port of the charge domain voltage small signal amplifying circuit, the fifth control signal generation port output clock Clkt of the control circuit to the Clkt clock input port of the charge domain voltage small signal amplifying circuit and analog-to-digital conversion The data output control terminal of the device.

The working sequence of the circuit shown in Fig. 5 fully adopts the working waveform schematic diagram given in Fig. 4 . The working principle of the circuit is: firstly, the first control signal of the control circuit generates the port output clock Clkr to control the state of the charge domain voltage small signal amplifier circuit to reset; secondly, the second control signal of the control circuit generates the port output clock Clks to control the charge domain voltage The small signal amplifying circuit samples the sensor input voltage signal Vi; again, the third and fourth control signal generation ports of the control circuit simultaneously output clocks Clk and Clkn to control the charge domain voltage small signal amplifying circuit to amplify the sampled voltage signal Vi The output voltage Vo is obtained; finally, the output clock Clkt of the fifth control signal generation port of the control circuit controls the charge domain voltage small signal amplifier circuit to output the output voltage Vo to the analog-to-digital converter, and the fifth control signal generation port of the control circuit also outputs The clock Clkt controls the analog-to-digital converter to perform analog-to-digital conversion on the received voltage Vo and output the converted quantization code to the digital code input terminal of the control circuit.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (4)

1. A charge-domain voltage small-signal amplifying circuit, characterized in that it comprises two charge storage nodes, a charge transfer control switch connected between the two charge storage nodes, and a first capacitor connected to the first charge storage node , a capacity programmable capacitor connected to the second charge storage node, a first voltage transmission switch connected to the first charge storage node, a second voltage transmission switch connected to the first charge storage node, and a second voltage transmission switch connected to the second charge storage node a third voltage transfer switch and a fourth voltage transfer switch connected to the second charge storage node; The connection relationship of the charge domain voltage small signal amplifying circuit is as follows: one end of the first capacitor is connected to the first charge storage node, and the other end is connected to the charge transfer control clock Clk; one end of the capacitance programmable capacitor is connected to the second charge storage node node, the other end is connected to the charge transfer control clock Clkn; the control end of the charge transfer control switch is connected to the transfer signal Clkt, and the two ends of the charge transfer control switch are connected to the first and second charge storage nodes; one end of the first voltage transfer switch is connected to To the first charge storage node, the other end is connected to the reference voltage 1, the switch control signal is connected to Clkr; one end of the second voltage transmission switch is connected to the first charge storage node, the other end is connected to the input voltage Vi, and the switch control signal is connected to Clks; One end of the third voltage transmission switch is connected to the second charge storage node, the other end is connected to the reference voltage 2, and the switch control signal is connected to Clkr; one end of the fourth voltage transmission switch is connected to the second charge storage node, and the other end is connected to the output voltage Vo, switch control signal connected to Clkt. 2. The charge-domain voltage small-signal amplifying circuit as claimed in claim 1 is characterized in that: after completing a voltage amplification, the relationship between the output voltage and the input voltage is a linear relationship in which the amplification factor is -C ₃₀₂ /C ₃₀₅ , wherein: C ₃₀₂ and C ₃₀₅ are capacitance values of the first capacitor and the programmable capacitor, respectively. 3. A signal detection circuit that adopts a charge domain voltage small signal amplifying circuit is characterized in that it includes: a sensor, a charge domain voltage small signal amplifying circuit, an analog-to-digital converter and a control circuit; the described use charge domain voltage small signal amplifying circuit The connection relationship of the circuit for signal detection is as follows: the output voltage of the sensor is connected to the input voltage port of the charge domain voltage small signal amplifying circuit, and the output voltage port of the charge domain voltage small signal amplifying circuit is connected to the analog voltage input port of the analog-to-digital converter , the quantized code output end of the analog-to-digital converter is connected to the digital code input end of the control circuit, the first control signal generation port output clock Clkr of the control circuit is connected to the Clkr clock input port of the charge domain voltage small signal amplifying circuit, the first control circuit of the control circuit The second control signal generation port outputs the clock Clks to the Clks clock input port of the charge domain voltage small signal amplifier circuit, the third control signal generation port of the control circuit outputs the clock Clk to the Clk clock input port of the charge domain voltage small signal amplifier circuit, and the control circuit The fourth control signal generation port output clock Clkn to the Clkn clock input port of the charge domain voltage small signal amplifying circuit, the fifth control signal generation port output clock Clkt of the control circuit to the Clkt clock input port of the charge domain voltage small signal amplifying circuit and The data output control terminal of the analog-to-digital converter. 4. A method for using a signal detection circuit that adopts a charge domain voltage small signal amplifying circuit is characterized in that it comprises the following steps: first the first control signal of the control circuit produces a port output clock Clkr to control the state of the charge domain voltage small signal amplifying circuit Reset; secondly, the second control signal of the control circuit generates port output clock Clks to control the charge domain voltage small signal amplifying circuit to sample the sensor input voltage signal; again, the fourth and fourth control signal of the control circuit generate port output clock simultaneously Clk and Clkn control the charge domain voltage small signal amplifier circuit to amplify the sampled voltage signal to obtain the output voltage; finally, the fifth control signal of the control circuit generates the port output clock Clkt to control the charge domain voltage small signal amplifier circuit to output the output voltage to For the analog-to-digital converter, the fifth control signal generating port of the control circuit also outputs a clock Clkt to control the analog-to-digital converter to perform analog-to-digital conversion on the received voltage and output the converted quantization code to the digital code input terminal of the control circuit.