CN106298963A - SONOS device architecture and the method forming this device - Google Patents
SONOS device architecture and the method forming this device Download PDFInfo
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- CN106298963A CN106298963A CN201610924432.0A CN201610924432A CN106298963A CN 106298963 A CN106298963 A CN 106298963A CN 201610924432 A CN201610924432 A CN 201610924432A CN 106298963 A CN106298963 A CN 106298963A
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 230000003647 oxidation Effects 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 37
- 125000006850 spacer group Chemical group 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 13
- 238000003475 lamination Methods 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
Abstract
The invention provides a kind of SONOS device architecture and the method forming this device.SONOS device architecture according to the present invention includes: silicon substrate, form source electrode in a silicon substrate and the grid of drain electrode, formation multiple structure on a silicon substrate；Wherein said grid includes from bottom to up: tunnel oxide silicon layer, silicon nitride layer, barrier oxidation silicon layer and polysilicon control grid, and described tunnel oxide silicon layer contacts with silicon substrate；Wherein, polysilicon control grid sidewall is formed with first grid side wall, first grid side wall and tunnel oxide silicon layer, silicon nitride layer, barrier oxidation silicon layer sidewall on be formed with second grid side wall.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of improve wiping, write window
SONOS device architecture and the method forming this device.
Background technology
Flash memory (Flash Memory) with the feature of its non-volatile (Non-Volatile) at mobile phone, number
The consumer electronics products such as code-phase machine and portable system are widely used.SONOS(Silicon-Oxide-
Nitride-Oxide-Silicon, silicon/silicon dioxide/silicon nitride/silicon dioxide/silicon) type flash memory is with its technique letter
Singly, voltage is low, data reliability is high and is readily integrated into the medium advantage of standard CMOS process and is regarded as common floating boom in operation
The substitute products of (Floating Gate) type flash memory.
Typical SONOS structure is by silicon substrate (S)-tunnel oxide (O)-charge storage layer silicon nitride (N)-stop oxygen
Change layer (O)-polysilicon gate (S) composition.This structure utilizes the tunnelling of electronics to be compiled, the injection number in hole
According to erasing.
In SONOS, electric charge is stored in ONO (Oxide-Nitride-Oxide, silicon dioxide/silicon nitride/bis-
Silicon oxide) in trapping centre in dielectric layer, thus it is referred to as electric charge capture device.
Along with the progress of Technology node, SONOS device carries out equal proportion micro, advanced work with process node simultaneously
SONOS device channel less under skill node causes reducing of memory area ono dielectric membrane area, thus reduces SONOS device
The wiping of part, write window, or limit the micro ability improving SONOS device cell further.
In prior art, for the SONOS device of reduced size under advanced technology nodes, series of process optimization is to improve
The capture ability of ono dielectric layer, thus improve the wiping of SONOS device, write window, or improve the micro-of SONOS device further
Contracting ability, the emphasis of always research and direction.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one can improve
The SONOS device architecture wipe, write window and the method forming this device.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of SONOS device architecture, including: silicon substrate,
Form source electrode in a silicon substrate and the grid of drain electrode, formation multiple structure on a silicon substrate；Wherein said grid from down to
On include: tunnel oxide silicon layer, silicon nitride layer, barrier oxidation silicon layer and polysilicon control grid, described tunnel oxide silicon layer and silicon
Substrate contacts；Wherein, polysilicon control grid sidewall is formed with first grid side wall, in first grid side wall and tunnelling
Silicon oxide layer, silicon nitride layer, barrier oxidation silicon layer sidewall on be formed with second grid side wall.
Preferably, the material of first grid side wall is silicon oxide.
Preferably, the thickness of first grid side wall is between 50A～200A.
Preferably, second grid side wall contacts with silicon substrate.
Preferably, the material of second grid side wall is silicon nitride, the thickness of second grid side wall between 50A～200A it
Between.
In order to realize above-mentioned technical purpose, according to the present invention, additionally provide a kind of SONOS device architecture forming method, its
It is characterised by including:
First step: be sequentially prepared on a silicon substrate and comprise tunnel oxide silicon layer, silicon nitride layer and barrier oxidation silicon layer
ONO lamination；
Second step: prepare polysilicon control grid in barrier oxidation silicon surface, wherein polysilicon control grid with substrate
It is smaller in size than ONO lamination in the plane that surface is parallel；
Third step: prepare first grid spacer material layer at above-mentioned device surface；
4th step: perform Self-aligned etching, etch described first grid spacer material layer, only leave polysilicon control grid
First grid spacer material layer on sidewall, and etch away beyond the first grid spacer material on polysilicon control grid sidewall
The ONO lamination of layer, forms the first grid side wall being on ONO lamination；
5th step: prepare second grid spacer material layer at above-mentioned device surface, and described in Self-aligned etching second
Grid curb wall material layer is so that at first grid side wall and tunnel oxide silicon layer, silicon nitride layer, the sidewall of barrier oxidation silicon layer
Upper formation second grid side wall；
6th step: form source electrode and drain electrode in a silicon substrate.
Preferably, first grid spacer material layer is silicon oxide layer.
Preferably, the thickness of described first grid spacer material layer is between 50A～200A.
Preferably, second grid spacer material layer is silicon nitride layer.
Preferably, the thickness of described second grid spacer material layer is between 50A～300A.
The SONSO device that the present invention provides has and obtains bigger equivalent channel length under limited areal, size, thus
Improve wiping, write window or the micro ability of SONOS device cell can be improved further.Present invention process is fairly simple, it is easy to
Integrated, may be used for batch production.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the schematic diagram of SONOS device architecture according to the preferred embodiment of the invention.
Fig. 2 schematically shows the first step of SONOS device architecture forming method according to the preferred embodiment of the invention
Rapid device architecture schematic diagram.
Fig. 3 schematically shows the second step of SONOS device architecture forming method according to the preferred embodiment of the invention
Rapid device architecture schematic diagram.
Fig. 4 schematically shows the 3rd step of SONOS device architecture forming method according to the preferred embodiment of the invention
Rapid device architecture schematic diagram.
Fig. 5 schematically shows the 4th step of SONOS device architecture forming method according to the preferred embodiment of the invention
Rapid device architecture schematic diagram.
Fig. 6 schematically shows the 5th step of SONOS device architecture forming method according to the preferred embodiment of the invention
The rapid device architecture schematic diagram with the 6th step.
Reference marker illustrates:
101: silicon substrate；201: source electrode；301: drain electrode；401: polysilicon control grid；402: tunnel oxide silicon layer；403: nitrogen
SiClx layer；404: barrier oxidation silicon layer；501: first grid side wall；502: second grid side wall.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 1 schematically shows the schematic diagram of SONOS device architecture according to the preferred embodiment of the invention.
As it is shown in figure 1, SONOS device architecture includes according to the preferred embodiment of the invention: silicon substrate 101, be formed at silicon
Source electrode in substrate 101 201 and drain electrode 301, the grid of the multiple structure being formed on silicon substrate 101；Wherein said grid from
Under supreme include: tunnel oxide silicon layer 402, silicon nitride layer 403, barrier oxidation silicon layer 404 and polysilicon control grid 401, described
Tunnel oxide silicon layer 402 contacts with silicon substrate 101；Wherein, polysilicon control grid 401 sidewall is formed with first grid side
Wall 501, at first grid side wall 501 and tunnel oxide silicon layer 402, silicon nitride layer 403, the sidewall of barrier oxidation silicon layer 404
On be formed with second grid side wall 502.
Preferably, the material of first grid side wall 501 is silicon oxide.Preferably, the thickness of first grid side wall 501 between
Between 50A～200A.
Preferably, second grid side wall 502 contacts with silicon substrate 101.It is further preferred that second grid side wall 502
Material is silicon nitride.Preferably, the thickness of second grid side wall 502 is between 50A～200A.
At the SONOS device described in manufacture, before grid both sides ONO film etches, increase first grid side wall 501 and deposit,
Then by Self-aligned etching, protect first grid side using the first grid side wall 501501 of silicon dioxide as etching barrier layer
Tunnel oxide silicon layer 402 below wall 501, silicon nitride layer 403, barrier oxidation silicon layer 404 are not etched, thus reach to increase ditch
The effective length of storage film ONO in road.
Fig. 2 to Fig. 6 schematically shows each of SONOS device architecture forming method according to the preferred embodiment of the invention
The device architecture schematic diagram of individual step.
As shown in Figures 2 to 6, SONOS device architecture forming method includes according to the preferred embodiment of the invention:
First step: be sequentially prepared on a silicon substrate and comprise tunnel oxide silicon layer 402, silicon nitride layer 403 and barrier oxidation
The ONO lamination of silicon layer 404；Specifically, the ONO lamination with storage function of described SONOS device, i.e. tunnel are formed by etching
Wear silicon oxide layer 402, silicon nitride layer 403, barrier oxidation silicon layer 404；
Second step: prepare polysilicon control grid 401, wherein polysilicon control grid 401 on barrier oxidation silicon layer 404 surface
The plane parallel with substrate surface be smaller in size than ONO lamination；
Specifically, the polysilicon control grid 401 of described SONOS device is formed by etching, after described polysilicon gate etching
Formed polysilicon control grid 401 be smaller in size than ONO lamination, etching stopping is at the barrier oxidation silicon layer 404 on ONO surface；
Third step: prepare first grid spacer material layer at above-mentioned device surface；
Preferably, first grid spacer material layer is silicon oxide layer；
Preferably, the thickness of described first grid spacer material layer is between 50A～200A.
4th step: perform Self-aligned etching, etch described first grid spacer material layer, only leave polysilicon control grid
First grid spacer material layer on 401 sidewalls, and etch away beyond the first grid side on polysilicon control grid 401 sidewall
The ONO lamination of the walling bed of material, forms the first grid side wall 501 being on ONO lamination；
5th step: prepare second grid spacer material layer at above-mentioned device surface, and described in Self-aligned etching second
Grid curb wall material layer is so that at first grid side wall 501 and tunnel oxide silicon layer 402, silicon nitride layer 403, barrier oxidation silicon
Second grid side wall 502 is formed on the sidewall of layer 404；
Preferably, second grid spacer material layer is silicon nitride layer, the thickness of described second grid spacer material layer between
50A～300A.
6th step: form source electrode 201 and drain electrode 301 in silicon substrate 101.
The present invention is directed to the less wiping of micro SONOS device under advanced technology nodes, write window, disclose a kind of increase by
The deposition of step silicon dioxide side wall, Self-aligned etching forms silicon dioxide side wall, thus obtains higher wiping, writes the SONOS of window
Device.SONSO device provided by the present invention has and obtains bigger equivalent channel length under limited areal, size, improves
Wiping, write window or can improve the micro ability of SONOS device cell further, technique is integrated simple, stable, can be used for advanced person
Produce in batches under processing procedure.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
But also it should be understood that the present invention is not limited to specific method described herein, compound, material, system
Making technology, usage and application, they can change.Should also be understood that term described herein is used merely to describe specific
Embodiment rather than be used for limit the scope of the present invention.Must be noted that herein and in claims use
Singulative " one ", " a kind of " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example
As, the citation to " element " means the citation to one or more elements, and includes known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
Multiple steps or the citation of device, and potentially include secondary step and second unit.Should manage with broadest implication
Solve all conjunctions used.Therefore, word "or" should be understood that definition rather than the logical exclusive-OR with logical "or"
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of this structure
Equivalent.Can be interpreted that the language of approximation should be understood, like that unless context explicitly indicates that contrary.
Claims (10)
1. a SONOS device architecture, it is characterised in that including: silicon substrate, form source electrode in a silicon substrate and drain electrode, formation
The grid of multiple structure on a silicon substrate；Wherein said grid includes from bottom to up: tunnel oxide silicon layer, silicon nitride layer, resistance
Gear silicon oxide layer and polysilicon control grid, described tunnel oxide silicon layer contacts with silicon substrate；Wherein, in polysilicon control grid side
First grid side wall it is formed with, at first grid side wall and tunnel oxide silicon layer, silicon nitride layer, barrier oxidation silicon layer on wall
Second grid side wall it is formed with on sidewall.
SONOS device architecture the most according to claim 1, it is characterised in that the material of first grid side wall is silicon oxide.
SONOS device architecture the most according to claim 1 and 2, it is characterised in that the thickness of first grid side wall between
Between 50A～200A.
SONOS device architecture the most according to claim 1 and 2, it is characterised in that second grid side wall connects with silicon substrate
Touch.
SONOS device architecture the most according to claim 1 and 2, it is characterised in that the material of second grid side wall is nitridation
Silicon, the thickness of second grid side wall is between 50A～200A.
6. a SONOS device architecture forming method, it is characterised in that including:
First step: be sequentially prepared the ONO comprising tunnel oxide silicon layer, silicon nitride layer and barrier oxidation silicon layer on a silicon substrate and fold
Layer；
Second step: prepare polysilicon control grid in barrier oxidation silicon surface, wherein polysilicon control grid with substrate surface
It is smaller in size than ONO lamination in parallel plane；
Third step: prepare first grid spacer material layer at above-mentioned device surface；
4th step: perform Self-aligned etching, etch described first grid spacer material layer, only leave polysilicon control grid sidewall
On first grid spacer material layer, and etch away beyond the first grid spacer material layer on polysilicon control grid sidewall
ONO lamination, forms the first grid side wall being on ONO lamination；
5th step: prepare second grid spacer material layer at above-mentioned device surface, and second grid described in Self-aligned etching
Spacer material layer so as first grid side wall and tunnel oxide silicon layer, silicon nitride layer, barrier oxidation silicon layer sidewall on shape
Become second grid side wall；
6th step: form source electrode and drain electrode in a silicon substrate.
SONOS device architecture forming method the most according to claim 6, it is characterised in that first grid spacer material layer
It it is silicon oxide layer.
8. according to the SONOS device architecture forming method described in claim 6 or 7, it is characterised in that described first grid side wall
The thickness of material layer is between 50A～200A.
9. according to the SONOS device architecture forming method described in claim 6 or 7, it is characterised in that second grid spacer material
Layer is silicon nitride layer.
10. according to the SONOS device architecture forming method described in claim 6 or 7, it is characterised in that described second grid side
The thickness of the walling bed of material is between 50A～300A.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610924432.0A CN106298963A (en) | 2016-10-24 | 2016-10-24 | SONOS device architecture and the method forming this device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610924432.0A CN106298963A (en) | 2016-10-24 | 2016-10-24 | SONOS device architecture and the method forming this device |
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ID=57719354
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| CN201610924432.0A Pending CN106298963A (en) | 2016-10-24 | 2016-10-24 | SONOS device architecture and the method forming this device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107833890A (en) * | 2017-09-19 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | The manufacture method of SONOS grid structure of storage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251719B1 (en) * | 2000-11-16 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Poly gate process that provides a novel solution to fix poly-2 residue under poly-1 oxide for charge coupled devices |
| US20060148172A1 (en) * | 2003-09-09 | 2006-07-06 | Yong-Suk Choi | Local sonos-type nonvolatile memory device and method of manufacturing the same |
| CN1870298A (en) * | 2006-06-09 | 2006-11-29 | 北京大学 | Preparation method of NROM flash control grid and flash unit |
-
2016
- 2016-10-24 CN CN201610924432.0A patent/CN106298963A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251719B1 (en) * | 2000-11-16 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Poly gate process that provides a novel solution to fix poly-2 residue under poly-1 oxide for charge coupled devices |
| US20060148172A1 (en) * | 2003-09-09 | 2006-07-06 | Yong-Suk Choi | Local sonos-type nonvolatile memory device and method of manufacturing the same |
| CN1870298A (en) * | 2006-06-09 | 2006-11-29 | 北京大学 | Preparation method of NROM flash control grid and flash unit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107833890A (en) * | 2017-09-19 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | The manufacture method of SONOS grid structure of storage |
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Application publication date: 20170104 |