CN106298952B - OLED device - Google Patents
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- CN106298952B CN106298952B CN201510306438.7A CN201510306438A CN106298952B CN 106298952 B CN106298952 B CN 106298952B CN 201510306438 A CN201510306438 A CN 201510306438A CN 106298952 B CN106298952 B CN 106298952B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 239000010409 thin film Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims 1
- 108091006146 Channels Proteins 0.000 description 60
- 238000010586 diagram Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention provides an OLED device, which solves the problem that the upper grid electrode and the lower grid electrode of a thin film transistor of the traditional OLED device are difficult to realize the simultaneous conduction of upper and lower conducting channels. The OLED device includes: at least two thin film transistors and V dd An electrode; wherein at least one of the at least two thin film transistors comprises: a lower gate electrode, a lower insulating layer arranged above the lower gate electrode, a semiconductor layer arranged above the lower insulating layer, an upper insulating layer arranged above the semiconductor layer, an upper gate electrode arranged above the upper insulating layer, a source electrode and a drain electrode; wherein the semiconductor layer is overlapped with the source electrode and the drain electrode respectively; a first gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the source electrode on a plane parallel to the conducting channel in the semiconductor layer, and a second gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the drain electrode; wherein the upper grid electrode of the at least one thin film transistor and the V dd The electrodes are connected.
Description
Technical Field
The invention relates to the technical field of photoelectric display, in particular to an OLED device.
Technical Field
The existing OLED device needs to adopt a thin film transistor to realize switch control and drive and adjust the current to adjust the brightness or other functions of the OLED light-emitting unit. In order to improve the mobility of the thin film transistor to improve the working efficiency of the OLED device, the OLED device in the prior art adopts a thin film transistor with an upper and lower dual gate structure to induce dual conduction channels in the semiconductor layer to increase the conduction channel.
Fig. 1 is a schematic structural diagram of a thin film transistor with a dual gate structure according to the prior art. As shown in fig. 1, the upper gate 11 of the thin film transistor overlaps over the source 12 and drain 13. When both the upper gate 11 and the lower gate 14 reach an on voltage (the on voltage is a threshold voltage, and when the voltage of the gate is higher than the on voltage, a conductive channel is induced in the semiconductor layer), an upper conductive channel and a lower conductive channel parallel to each other can be induced in the semiconductor layer 15. Since the upper gate 11 overlaps over the source 12 and drain 13 (on a plane parallel to the conductive channel in the semiconductor layer 15, the orthographic projection of the upper gate 11 overlaps partially with the orthographic projection of the source 12 and the orthographic projection of the drain 13, respectively); thus, the drain electrode 13 can be conducted with the source electrode 12 solely through the upper conductive channel. In addition, the drain electrode 13 can be conducted with the source electrode 12 through an underlying conductive channel alone. However, it is difficult to ensure mobility improvement by simultaneous conduction of upper and lower conductive channels in such a dual gate structure thin film transistor, because:
because of the process technology, the parameters such as the capacitance of the upper insulating layer 16 under the upper gate 11 and the lower insulating layer 17 over the lower gate are difficult to match, which may cause different turn-on voltages of the upper and lower conductive channels formed by the upper gate 11 and the lower gate 14, so that the upper and lower conductive channels are difficult to be formed and turned on simultaneously in the thin film transistor structure in the prior art, which may affect the working efficiency of the OLED device.
Disclosure of Invention
In view of the above, the embodiment of the invention provides an OLED device, which solves the problem that the upper gate and the lower gate of the thin film transistor of the existing OLED device are difficult to realize simultaneous conduction of the upper and lower conductive channels.
The OLED device provided by the embodiment of the invention comprises: to the point ofAt least two thin film transistors and V dd An electrode; wherein at least one of the at least two thin film transistors comprises: a lower gate electrode, a lower insulating layer arranged above the lower gate electrode, a semiconductor layer arranged above the lower insulating layer, an upper insulating layer arranged above the semiconductor layer, an upper gate electrode arranged above the upper insulating layer, a source electrode and a drain electrode;
wherein the semiconductor layer is overlapped with the source electrode and the drain electrode respectively; a first gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the source electrode on a plane parallel to the conducting channel in the semiconductor layer, and a second gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the drain electrode;
wherein the upper grid electrode of the at least one thin film transistor and the V dd The electrodes are connected.
In the OLED device provided by the embodiment of the invention, the adopted thin film transistor has the advantages that the first gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the source electrode on the plane parallel to the conducting channel in the semiconductor layer, and the second gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the drain electrode, so that the upper grid electrode cannot independently form the conduction of the upper conducting channel; at the same time, V of the upper grid electrode and OLED device dd The electrode connection can keep the voltage of the upper grid electrode higher than the starting voltage all the time, and when the lower grid electrode reaches the starting voltage, the upper grid electrode can complete the conduction of the upper conducting channel by utilizing the lower conducting channel formed by the induction of the lower grid electrode, so that the simultaneous conduction of the upper conducting channel and the lower conducting channel is realized.
Drawings
Fig. 1 is a schematic structural diagram of a thin film transistor with a dual gate structure according to the prior art.
Fig. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a conductive principle of a thin film transistor according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a conductive principle of a thin film transistor according to an embodiment of the present invention.
Fig. 5 is a diagram showing a conductive experiment result of a thin film transistor according to an embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of an OLED device according to an embodiment of the present invention.
Fig. 7 is a schematic circuit diagram of an OLED device according to another embodiment of the present invention.
Fig. 8 is a schematic diagram illustrating an operation principle of an OLED device according to another embodiment of the present invention.
The reference numerals are as follows:
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
An embodiment of the invention provides an OLED device comprising at least two Thin Film Transistors (TFTs), V dd Electrode, OLED light-emitting unit, capacitor and V ss An electrode, a data signal line, and a scan signal line. The at least two Thin Film Transistors (TFTs) may be used as a switching TFT and a driving TFT, respectively. The scanning signal line is connected to the switching TFT to control switching of the switching TFT. In the on state of the switching TFT, the data signal line transmits a data signal to the driving TFT to control the brightness of the OLED light emitting device. V (V) dd The electrode supplies power to the OLED light-emitting device, V ss The electrode is grounded. And V is dd A capacitor is connected between the electrode and the gate electrode of the driving TFT, and the capacitor maintains the data voltage signal in the timing of one frame scan signal at a voltage at which it operates normally.
Fig. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. As shown in fig. 2, the thin film transistor includes: a lower gate 14, a lower insulating layer 17 provided over the lower gate 14, a semiconductor layer 15 provided over the lower insulating layer 17, an upper insulating layer 16 provided over the semiconductor layer 15, an upper gate 11 provided over the upper insulating layer 16, a source 12, and a drain 13 (drain);
wherein the semiconductor layer 15 is overlapped with the source electrode 12 and the drain electrode 13, respectively; on a plane parallel to the conductive channel in the semiconductor layer 15, a first gap 18 is present between the front projection of the upper gate 11 and the front projection of the source 12, and a second gap 19 is present between the front projection of the upper gate 11 and the front projection of the drain 13. Wherein, the upper grid 11 is connected with V of the OLED device dd The electrode 2 is connected so that the voltage of the upper gate 11 can always be higher than its turn-on voltage.
It will be appreciated by those skilled in the art that the bonding method between the semiconductor layer 15 and the source electrode 12 and the drain electrode 13 can be adjusted according to the actual structural design, so long as conduction between the conductive channel in the semiconductor layer 15 and the source electrode 12 and the drain electrode 13 can be achieved, and the bonding method between the semiconductor layer 15 and the source electrode 12 and the drain electrode 13 is not limited in the present invention.
In an embodiment of the present invention, as shown in fig. 2, the surface of the upper insulating layer 16 includes a source hole 114 and a drain hole 115, and the semiconductor layer 15 is overlapped with the source electrode 12 and the drain electrode 13 in the following manner: the source electrode 12 is overlapped with the surface of the semiconductor layer 15 through the source electrode hole 114 on the surface of the upper insulating layer 16, and the drain electrode 13 is overlapped with the surface of the semiconductor layer 15 through the drain electrode hole 115 on the surface of the upper insulating layer 16. As can be seen from this, unlike the thin film transistor having the vertical double gate structure in the related art, when the above-described bonding method is adopted, the upper gate 11 is not overlapped over the source electrode 12 and the drain electrode 13, but is in the same layer as the source electrode 12 and the drain electrode 13. In addition, on the plane parallel to the conductive channel in the semiconductor layer 15, the front projection of the upper gate 11 and the front projection of the source 12 and the front projection of the drain 13 respectively have a first gap 18 and a second gap 19, and the regions of the semiconductor layer 15 corresponding to the first gap 18 and the second gap 19 are always in a high-resistance state, so that even if the upper gate 11 reaches the turn-on voltage, the semiconductor layer 15 corresponding to the upper gate 11 is induced to form an upper conductive channel in a low-resistance state, the conduction between the upper conductive channel and the source 12 and the drain 13 cannot be realized; and only when the lower gate 14 reaches the opening voltage, the conduction of the upper conducting channel can be indirectly completed by using the lower conducting channel induced by the lower gate 14, so that the simultaneous conduction of the upper conducting channel and the lower conducting channel is realized.
Furthermore, as shown in fig. 1, the upper gate 11 overlaps the source electrode 12 and the drain electrode 13 in the related art, and thus a passivation layer 116 is required to be separately designed for the preparation of the upper gate 11 to perform a mask etching process, which increases the preparation cost. When the thin film transistor structure shown in fig. 2 is adopted, the upper gate 11, the source electrode 12 and the drain electrode 13 are located on the same layer, a mask etching process is not required to be designed for preparing the upper gate 11 separately, and the upper gate 11, the source electrode 12 and the drain electrode 13 can be formed synchronously through one etching process, so that the preparation cost is saved.
In an embodiment of the present invention, the thickness of the semiconductor layer 15 is generally thinner, in order to avoid excessive parasitic resistance when the current of the source 12/drain 13 breaks down the semiconductor layer 15 to reach the conductive channel. However, since the depth of the conductive channel in the on state is about 3nm to 15nm, in order to ensure that the upper and lower conductive channels in the semiconductor layer 15 are simultaneously opened without mutual influence, the thickness of the semiconductor layer 15 may be set between 10nm and 200 nm. In one embodiment, the thickness of the semiconductor layer 5 may be specifically set to 30nm, which may ensure that a sufficiently wide conductive channel is formed on the upper and lower surfaces of the semiconductor layer 15, and may reduce parasitic resistance of the source electrode 12/drain electrode 13 overlapping the conductive channel as much as possible.
As previously described, a first gap 18 exists between the front projection of the upper gate 11 and the front projection of the source 12, and a second gap 19 exists between the front projection of the upper gate 11 and the front projection of the drain 13, in a plane parallel to the conductive channel in the semiconductor layer 15. The width of the first gap 18 corresponds to the first semiconductor material high-resistance region 112, and the width of the second gap 19 corresponds to the second semiconductor material high-resistance region 113. To ensure that a high resistance region of semiconductor material exists between the upper conductive channel 110 and the source 12 and drain 13, and to minimize the volume of the thin film transistor, the widths of the first and second gaps 18 and 19 may be varied according to the semiconductorThe intrinsic resistance of the semiconductor material of layer 15 is tuned to the minimum leakage current that can be tolerated. When the lower gate 14 does not reach the turn-on voltage and the upper gate reaches the turn-on voltage, the leakage current flowing through the semiconductor layer 15 can be expressed as: i leak ＝U d /(2R W/D), where U d For the drain voltage, R is the intrinsic resistance of the semiconductor layer 15, W is the width of the semiconductor layer 15, dur is the width of the first gap 18/second gap 19.
In one embodiment of the present invention, when the semiconductor material (e.g., metal oxide) selected for the semiconductor layer 15 has an intrinsic sheet resistance of R=1e+12Ω, the drain voltage U d When the width w=5um of the semiconductor layer 15 and the width d=1um of the first gap 18/second gap 19 are =10v (1 um is the process limit value of processing the first gap 18/second gap 19 between the upper gate 11 and the source 12/drain 13), the leakage current I is obtained leak =0.5 pA, which can meet OLED device product requirements. The widths of the first and second gaps 18 and 19 between the upper gate 11 and the source and drain electrodes 12 and 13 can be as small as 1um. In an embodiment of the present invention, the widths of the first gap 18 and the second gap 19 may be specifically set to 3um, so that the photolithography machine can be ensured to work under stable process conditions, higher process precision is achieved, and the leakage current of the upper gate 11 can be controlled to be in the order of 1pA, which also meets the product requirement of the OLED device. The width of the first gap 18 and the second gap 19 is not strictly limited in the present invention.
In one embodiment of the present invention, the semiconductor layer 15 may be made of a semiconductor material such as metal oxide (e.g., indium gallium zinc oxide IGZO), amorphous silicon, polysilicon, or microcrystalline silicon. The material for preparing the semiconductor layer 15 is not limited in the present invention.
In an embodiment of the present invention, the upper gate 11, the lower gate 14, the source 12, and the drain 13 may be made of Mo metal material or other conductive material. The materials for preparing the upper gate 11, the lower gate 14, the source electrode 12, and the drain electrode 13 are not limited in the present invention.
The conduction principle of the thin film transistor in the OLED device of the present invention will be described in detail with reference to the following two drawings.
Fig. 3 is a schematic diagram of a conductive principle of a thin film transistor according to an embodiment of the present invention. As shown in fig. 3, the semiconductor layer 15 is overlapped with the source electrode 12 and the drain electrode 13 in the manner shown in fig. 2, and the lower gate 14 has not reached the turn-on voltage of the lower gate 14, so that conduction of the lower conductive channel cannot be formed in the semiconductor layer 15. Although the upper gate 11 passes through the gate V dd The electrode 2 is connected to the turn-on voltage of the upper gate 11, but since the upper gate 11 does not cover the entire upper insulating layer 16, but there are a first gap 18 and a second gap 19 between the upper gate 11 and the source 12 and the drain 13, the upper gate 11 can only induce a shorter upper conductive channel 110 corresponding to the upper gate 11 in the semiconductor layer 15, and there are two high-resistance regions of semiconductor material between the upper conductive channel 110 and the source 12 and the drain 13, corresponding to the first gap 18 and the second gap 19, and thus the upper conductive channel 110 cannot be conducted with the source 12 and the drain 13. It can be seen that when the lower gate 14 does not reach the turn-on voltage of the lower gate 14, the upper conductive channel 110 is still unable to be conducted with the source 12 and the drain 13, although the upper gate 11 is already in the turned-on state.
Fig. 4 is a schematic diagram of a conductive principle of a thin film transistor according to an embodiment of the present invention. As shown in fig. 4, the semiconductor layer 15 is overlapped with the source electrode 12 and the drain electrode 13 in the manner shown in fig. 2, the lower gate 14 has reached the turn-on voltage of the lower gate 14, and the current flows in the transistor as shown by the arrows in the figure. Specifically, since the lower gate 14 has reached the turn-on voltage of the lower gate 14, the lower conductive channel 111 has been formed in the semiconductor layer 15. Due to the thin thickness of the semiconductor layer 15, a current can break down the semiconductor layer 15 from the drain electrode 13 to the lower conductive channel 111 and again break down the semiconductor layer 15 via the lower conductive channel 111 to the source electrode 12. At this time, due to the upper gate 11 and V dd The electrode 2 is connected, the upper conductive channel 110 is always in an on state, and current can flow from the lower conductive channel 111 to the upper conductive channel 110 by breaking down the semiconductor layer 15, and back to the lower conductive channel 111 by breaking down the semiconductor layer 15 again via the upper conductive channel 110, and finally to the source. Thereby realizing the simultaneous conduction of the upper conductive channel 110 and the lower conductive channel 111, and improving the mobilityEffects.
Fig. 5 is a diagram showing a conductive experiment result of a thin film transistor according to an embodiment of the present invention. As shown in fig. 5, vg is the voltage of the lower gate 14, vth is the turn-on voltage of the lower gate 14, id is the magnitude of the on current in the semiconductor layer 15, and the ratio refers to the ratio of the mobility of the thin film transistor used in the present invention to that of the conventional single gate structure, and the test conditions are: drain voltage vd=0.1v, vg= -10-20V. As can be seen from fig. 5, the mobility of the thin film transistor structure provided by the embodiment of the present invention can be more than twice that of the conventional single gate thin film transistor.
It will be appreciated by those skilled in the art that, as described above, an OLED device may include a plurality of thin film transistors 1, and the plurality of thin film transistors 1 may respectively serve as switching transistors of the OLED device, drive the OLED light emitting unit, or perform other control functions, and the number and the functions of the thin film transistors 1 in one OLED device are not limited in the present invention.
Fig. 6 is a schematic circuit diagram of an OLED device according to an embodiment of the present invention. Referring to fig. 6 in combination with fig. 3 or 4, the OLED device includes two thin film transistors 1, respectively denoted as T1 and T2. Wherein T1 is used for realizing the switch control of the OLED device; t2 is used for driving the OLED lighting unit 3, and for adjusting the current to achieve brightness adjustment of the OLED lighting unit 3.
The drain electrode 13 of the T1 is connected with the data signal line 6 of the OLED device, the source electrode 12 is connected with the capacitor 4 of the OLED device, the lower grid electrode 14 is connected with the scanning signal line 7 of the OLED device, and the upper grid electrode 11 is connected with V dd The electrodes 2 are connected.
According to the foregoing description, since the upper gates 11 of T1 and T2 are both connected to V dd The electrode 2 is connected, so that both T1 and T2 can obtain the effect of simultaneously starting up and down conducting channels, and the mobility is twice that of the traditional single gate transistor structure, thereby the working efficiency of the whole OLED device is improvedThe improvement is achieved.
In practical use, after the OLED device is used for a period of time, the turn-on voltage of the lower gate 14 of the thin film transistor 1 may drift negatively, thereby resulting in reduced performance of the product and reduced reliability of the OLED device. To solve this problem, in one embodiment of the present invention, the upper gate 11 may be connected to a negative bias voltage when the performance of the OLED device is deteriorated, as shown in fig. 7. The carrier concentration of the lower conductive channel of the lower gate 14 is reduced by the negative bias field, so that the turn-on voltage of the lower gate 14 is shifted forward. Fig. 8 shows the Vg voltage curve versus the negative bias value of the upper gate 11. As can be seen from fig. 8, when the voltage value of the upper gate 11 is changed from 0V to-3V, the voltage curve of Vg is shifted forward to a normal value.
In an embodiment of the present invention, an automatic on-voltage detection unit may be further added to the circuit structure of the OLED device to automatically compensate when the on-voltage of the lower gate 14 has a negative drift. Of course, the turn-on voltage of the lower gate 14 may be compensated by detecting the turn-on voltage at a later stage. The invention does not limit the detection mode of the starting voltage.
In the OLED device provided by the embodiment of the invention, the adopted thin film transistor has the advantages that the first gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the source electrode on the plane parallel to the conducting channel in the semiconductor layer, and the second gap exists between the orthographic projection of the upper grid electrode and the orthographic projection of the drain electrode, so that the upper grid electrode cannot independently form the conduction of the upper conducting channel; at the same time, V of the upper grid electrode and OLED device dd The electrode connection can keep the voltage of the upper grid electrode higher than the starting voltage all the time, and when the lower grid electrode reaches the starting voltage, the upper grid electrode can indirectly complete the conduction of the upper conducting channel by utilizing the lower conducting channel formed by the induction of the lower grid electrode, so that the simultaneous conduction of the upper conducting channel and the lower conducting channel is realized.
The foregoing is only illustrative of the present invention and is not to be construed as limiting thereof, but rather as presently claimed, and is intended to cover all modifications, alternatives, and equivalents falling within the spirit and scope of the invention.
Claims (10)
1. An OLED device, comprising: at least two thin film transistors (1) and V dd An electrode (2); wherein at least one thin film transistor (1) of the at least two thin film transistors (1) comprises: a lower gate (14), a lower insulating layer (17) provided above the lower gate (14), a semiconductor layer (15) provided above the lower insulating layer (17), an upper insulating layer (16) provided above the semiconductor layer (15), an upper gate (11) provided above the upper insulating layer (16), a source (12), and a drain (13); the upper gate (11) is in the same layer as the source (12) and the drain (13);
wherein the semiconductor layer (15) is overlapped with the source electrode (12) and the drain electrode (13), respectively; -a first gap (18) is present between the orthographic projection of the upper gate (11) and the orthographic projection of the source (12) on a plane parallel to the conducting channel in the semiconductor layer (15), and a second gap (19) is present between the orthographic projection of the upper gate (11) and the orthographic projection of the drain (13);
wherein the upper gate (11) of the at least one thin film transistor (1) and the V dd The electrodes (2) are connected.
2. The OLED device of claim 1, further comprising: an OLED light-emitting unit (3) and a capacitor (4);
when any one of the thin film transistors (1) is used for driving the OLED light-emitting unit (3), further, the drain electrode (13) of the one thin film transistor (1) and the V dd The electrode (2) is connected, the source electrode (12) is connected with the OLED light-emitting unit (3) of the OLED device, and the lower grid electrode (14) is connected with the capacitor (4) of the OLED device.
3. The OLED device of claim 1, further comprising: a data signal line (6), a capacitor (4), and a scanning signal line (7);
when any one of the thin film transistors (1) is used as a switching transistor of an OLED device, further, the drain electrode (13) of the one thin film transistor (1) is connected with the data signal line (6) of the OLED device, the source electrode (12) is connected with the capacitor (4) of the OLED device, and the lower gate electrode (14) is connected with the scanning signal line (7) of the OLED device.
4. An OLED device according to any one of claims 1 to 3, characterized in that the width of the first gap (18) or the second gap (19) is adjusted in accordance with the intrinsic resistance of the semiconductor material of the semiconductor layer (15) and the lowest leakage current that can be tolerated.
5. The OLED device according to claim 4, characterized in that the width of the first gap (18) and/or the second gap (19) is greater than 1um.
6. The OLED device according to claim 5, characterized in that the width of the first gap (18) and/or the second gap (19) is 3um.
7. An OLED device according to any one of claims 1 to 3, characterized in that the thickness of the semiconductor layer (15) is 30nm.
8. An OLED device according to any one of claims 1 to 3, characterized in that the semiconductor layer (15) is made of metal oxide, or amorphous silicon, or polysilicon, or microcrystalline silicon material.
9. The OLED device according to claim 8, characterized in that the metal oxide used for the semiconductor layer (15) is indium gallium zinc oxide.
10. An OLED device according to any one of claims 1 to 3, characterized in that the upper gate (11), and/or the lower gate (14), and/or the source (12), and/or the drain (13) are made of Mo metal material.
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| KR101152575B1 (en) * | 2010-05-10 | 2012-06-01 | 삼성모바일디스플레이주식회사 | Pixel circuit of a flat panel display device and method of driving the same |
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| CN202601619U (en) * | 2012-01-09 | 2012-12-12 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display |
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