CN106298818B

CN106298818B - CMOS image sensor and manufacturing method and operation method thereof

Info

Publication number: CN106298818B
Application number: CN201510255865.7A
Authority: CN
Inventors: 何昭文; 李曼曼; 王奇峰
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2015-05-19
Filing date: 2015-05-19
Publication date: 2020-06-09
Anticipated expiration: 2035-05-19
Also published as: CN106298818A

Abstract

The invention provides a CMOS image sensor and a manufacturing method and an operating method thereof, and relates to the technical field of semiconductors. The CMOS image sensor includes: a semiconductor substrate having a first conductivity type; at least two transmission transistors on the semiconductor substrate and a photodiode region on one side of the transmission transistors, wherein the at least two transmission transistors are connected with the photodiode region; and at least two floating diffusion regions which are arranged in the semiconductor substrate at intervals and are arranged on the other side of the transmission transistor, wherein the at least two floating diffusion regions are respectively connected with a different transmission transistor. The CMOS image sensor of the invention adopts the multi-transmission grid to control the effective capacitance value of the floating diffusion region FD, so that the capacitance value of the floating diffusion region FD can be adjusted according to actual needs, the minimum sensitivity and the saturation sensitivity of the CIS are optimized, and the performance of the CMOS image sensor is improved.

Description

CMOS image sensor and manufacturing method and operation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a CMOS image sensor and a manufacturing method and an operating method thereof.

Background

In the field of semiconductor technology, an image sensor is a semiconductor device that can convert an optical image into an electrical signal. Image sensors can be broadly classified into Charge Coupled Devices (CCDs) and complementary metal oxide semiconductor Image sensors (CIS). The CCD image sensor has advantages of high image sensitivity and low noise, but the integration of the CCD image sensor with other devices is difficult and the power consumption of the CCD image sensor is high. In contrast, CMOS image sensors have gradually replaced the position of CCDs due to their advantages of simple process, easy integration with other devices, small size, light weight, low power consumption, low cost, etc. CMOS image sensors are widely used in the fields of digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), vehicle imaging devices, and the like.

However, the minimum sensitivity and saturation sensitivity of the CMOS image sensor in the related art are mutually hampered. The minimum sensitivity refers to the minimum light intensity that the CMOS image sensor can detect, and the saturation sensitivity refers to the maximum light intensity that the CMOS image sensor can resolve.

A pixel of the CMOS image sensor may include a plurality of photodiodes for receiving light and a plurality of transistors for controlling an input video signal. The CMOS image sensor may be classified into a 3T type, a 4T type, and the like according to the number of transistors. The 3T type CMOS image sensor may include one photodiode and three transistors, and the 4T type CMOS image sensor may include one photodiode and four transistors.

Typically, a 4T PPS type CIS, comprising: a photodiode region PD, a transfer transistor Tx, a reset transistor Rx, a driving transistor Dx, and a selection transistor Sx. Where the photodiode region PD is used to convert light energy into energy charges, the floating diffusion region FD may receive electrons from the photodiode PD and then convert a charge signal into a voltage signal.

After the transfer transistor Tx is turned on, photocarriers in the PD region enter the floating diffusion region FD, and the charge amount of the photocarriers is △ Q, the voltage change △ V generated by the PN junction capacitance of the floating diffusion region FD is △ Q/C, △ V reflects the intensity of external light, as can be seen from the above equation, △ Q generated is small when the light is weak, and C should be reduced to obtain large △ V in order to induce a small change in △ Q, on the other hand, △ Q obtained is large in strong light, and the minimum sensitivity and saturation sensitivity cannot be optimized at the same time in the prior art, in order to increase the upper limit of the FD stored charge to prevent charge saturation and overflow.

Therefore, in order to solve this technical problem, it is necessary to provide a new CMOS image sensor structure.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the deficiencies of the prior art, an embodiment of the present invention provides a CMOS image sensor, including:

a semiconductor substrate having a first conductivity type;

at least two transmission transistors on the semiconductor substrate and a photodiode region on one side of the transmission transistors, wherein the at least two transmission transistors are connected with the photodiode region;

and at least two floating diffusion regions which are arranged in the semiconductor substrate at intervals and are arranged on the other side of the transmission transistor, wherein the at least two floating diffusion regions are respectively connected with a different transmission transistor.

Optionally, the number of transfer transistors is the same as the number of floating diffusion regions.

Optionally, the transfer transistors are connected to the floating diffusion regions in a one-to-one correspondence.

Optionally, a reset transistor is further included, the floating diffusion region being located between the pass transistor and the reset transistor.

Optionally, each of the pass transistors includes a gate structure on the semiconductor substrate.

Optionally, the gate structure includes a gate dielectric layer and a gate material layer sequentially located on the semiconductor substrate.

Optionally, a spacer is also formed on the sidewalls of the gate structure.

Optionally, the display device further comprises a selection transistor and a driving transistor which are formed on the semiconductor substrate.

Optionally, the photodiode region includes a first doped region formed in the semiconductor substrate having a second conductivity type opposite to the first conductivity type.

Optionally, an epitaxial layer covering a portion of the semiconductor substrate, the epitaxial layer being heavily doped to have the first conductivity type, the photodiode region being located within the epitaxial layer.

Optionally, the width of the epitaxial layer is in the range of 2-10 μm.

Optionally, the first conductivity type is a P type, and the second conductivity type is an N type, or the first conductivity type is an N type, and the second conductivity type is a P type.

Optionally, the reset transistor includes a gate structure formed on the semiconductor substrate, and a source region and a drain region of the same doping type as the first doping region are further formed in the semiconductor substrate on both sides of the gate structure.

Optionally, the selection transistor and the driving transistor each include a gate structure formed on the semiconductor substrate, and a source region and a drain region of the same doping type as the first doping region are further formed in the semiconductor substrate on both sides of the gate structure.

The invention also provides an operation method based on the CMOS image sensor, which comprises the following steps:

when external light is weak, only part of the transmission transistors are turned on, and carriers generated in the photodiode area only enter the floating diffusion area connected with the turned-on transmission transistors, so that the capacitance of the floating diffusion area is reduced, and the minimum sensitivity of the CMOS image sensor is improved;

when external light is weak, all the transmission transistors are turned on simultaneously, and carriers generated in the photodiode region enter the floating diffusion region connected with the turned-on transmission transistors, so that the capacitance of the floating diffusion region is increased, and the saturation sensitivity of the CMOS image sensor is improved.

The invention also provides a manufacturing method of the CMOS image sensor, which comprises the following steps:

step A1: providing a semiconductor substrate having a first conductivity type;

step A2: forming at least two pass transistors on the semiconductor substrate, the pass transistors including a gate structure formed on the semiconductor substrate;

step A3: performing an ion implantation process on a part of the semiconductor substrate on one side of the transmission transistor to form a first doped region with a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type, and a photodiode region is formed by the part of the semiconductor substrate and the first doped region;

step A4: forming at least two floating diffusion regions at intervals in the semiconductor substrate on the other side of the transmission transistor, wherein each floating diffusion region is respectively connected with one transmission transistor, each floating diffusion region comprises a second doping region which is formed in the semiconductor substrate and has a second conductivity type, and each floating diffusion region has junction capacitance.

Optionally, in the step a1, an epitaxial layer covering a portion of the semiconductor substrate is further included, and the epitaxial layer is heavily doped with the first conductive type to form the photodiode region.

Optionally, the width of the epitaxial layer is in the range of 2-10 μm.

Optionally, the step a2 further includes: and forming a reset transistor on the semiconductor substrate, wherein the reset transistor and the photodiode region are positioned at different sides of the transmission transistor, the semiconductor substrate region between the transmission transistor and the reset transistor is used for forming the floating diffusion region, and the reset transistor comprises a gate structure formed on the semiconductor substrate.

Optionally, the step a2 further includes: and forming a driving transistor and a selection transistor on the semiconductor substrate, wherein the driving transistor and the selection transistor both comprise gate structures.

Optionally, after the step A3 and before the step a4, a step of forming a spacer on a sidewall of a gate structure of the pass transistor is further included.

Optionally, after the step a4, the following steps are further included:

performing ion implantation on source/drain regions of the reset transistor, the driving transistor and the selection transistor to form a source/drain region with a second conductivity type;

forming an interlayer dielectric layer to cover the semiconductor substrate and the grid structure; and forming a back line layer on the interlayer dielectric layer;

and carrying out back-end packaging.

Optionally, the gate structure includes a gate dielectric layer and a gate material layer sequentially formed on the semiconductor substrate.

The CMOS image sensor of the invention adopts the multi-transmission grid to control the effective capacitance value of the floating diffusion region FD, so that the capacitance value of the floating diffusion region FD can be adjusted according to actual needs, and simultaneously, the minimum sensitivity and the saturation sensitivity of the CIS are optimized, thereby further improving the performance of the CMOS image sensor.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1A is a top view structural diagram of a CMOS image sensor according to an embodiment of the present invention;

FIG. 1B shows a partial cross-sectional view of the CMOS image sensor taken along section line A-A' of FIG. 1A;

FIG. 1C shows a partial cross-sectional view of the CMOS image sensor taken along section line B-B' of FIG. 1A;

fig. 2A to 2D are partial cross-sectional views illustrating a corresponding device based on an operation method of the CMOS image sensor as in fig. 1A;

fig. 3 is a top view structural diagram of a CMOS image sensor according to another embodiment of the present invention;

FIGS. 4, 5A-5B, 6A-6B, 7A-7B, 8A-8B and 9A-9B are schematic diagrams illustrating devices obtained by implementing a method of fabricating a CMOS semiconductor device in sequence according to an embodiment of the present invention

FIG. 4 is a cross-sectional view, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A and FIG. 9A are top view structural diagrams, and FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B and FIG. 9B are partial cross-sectional views of devices obtained along the cross-sectional line A-A' in FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A and FIG. 9A, respectively;

fig. 10 is a flowchart illustrating a method for fabricating a CMOS image sensor according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Example one

Next, the structure of the CMOS image sensor according to the embodiment of the present invention is described with reference to fig. 1A to 1C, fig. 2A to 2D, and fig. 3. Fig. 1A is a top view structural diagram of a CMOS image sensor according to an embodiment of the present invention; FIG. 1B shows a partial cross-sectional view of the CMOS image sensor taken along section line A-A' of FIG. 1A; FIG. 1C shows a partial cross-sectional view of the CMOS image sensor taken along section line B-B' of FIG. 1A; fig. 2A to 2D are partial cross-sectional views illustrating a corresponding device based on an operation method of the CMOS image sensor as in fig. 1A; fig. 3 is a top view structural diagram of a CMOS image sensor according to another embodiment of the present invention.

As shown in fig. 1A to 1C, a CMOS image sensor according to an embodiment of the present invention includes: a semiconductor substrate 100 having a first conductivity type. The semiconductor substrate 100 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. An isolation structure (not shown) is formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. The first conductive type may be N-type or P-type, and the P-type semiconductor substrate 100 is taken as an example in this embodiment.

In one example, the CMOS image sensor may further include an epitaxial layer covering a portion of the semiconductor substrate, the epitaxial layer being heavily doped with the first conductivity type, e.g., being a P + epitaxial layer, the photodiode region being located within the epitaxial layer. Preferably, the width of the epitaxial layer is in the range of 2-10 μm.

As shown in fig. 1A, the CMOS image sensor further includes at least two transfer transistors Tx1 and Tx2 on the semiconductor substrate 100 and a photodiode region PD on one side of the transfer transistors Tx1 and Tx2, wherein at least two transfer transistors Tx1 and Tx2 are connected to the photodiode region PD, and fig. 1A shows only the case of having two transfer transistors, but the present invention is not limited thereto, and more than two transfer transistors, for example, 3, 4, 5, 6, etc., may be included, but it is required to ensure that at least two transfer transistors are connected to the photodiode region. As shown in fig. 1C, the photodiode region PD includes a first doping region 101 having a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate 100, and the semiconductor substrate of the photodiode region and the first doping region 101 therein constitute a PN junction as a photodiode.

In one example, each of the pass transistors Tx1, Tx2 includes a gate structure on the semiconductor substrate 100. Further, the gate structure includes a gate dielectric layer 1021 and a gate material layer 1022 sequentially located on the semiconductor substrate 100. Further, a spacer 1023 is formed on the sidewall of the gate structure.

The gate dielectric layer 1021 may comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer 1021 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). Gate material layer 1022 may include various materials including, but not limited to: certain metals, metal alloys, metal nitrides and metal silicides, and laminates and composites thereof. The gate material layer 1022 may also include doped polysilicon and polysilicon-germanium alloy materials (i.e., having a doping concentration of from about 1e18 to about 1e22 doping atoms per cubic centimeter) and polysilicon metal silicide (polycide) materials (doped polysilicon/metal silicide stack materials). Spacer 1023 the spacer may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The CMOS image sensor further includes at least two floating diffusions FD1, FD2 spaced apart in the semiconductor substrate 100 on the other side of the transfer transistors Tx1, Tx 2. Each of the floating diffusions FD1 and FD2 has a junction capacitance, and the floating diffusions FD1 and FD2 include a second doped region 103 having a second conductivity type opposite to the first conductivity type, for example, when the semiconductor substrate is a P-type semiconductor substrate, the second doped region is an N-type doped region, and the second doped region and the P-type semiconductor substrate form a PN junction, i.e., a PN junction capacitance, as shown in fig. 1B.

The number of the floating diffusion regions may also be greater than two, and the number of the transfer transistors may also be greater than two, but it is required to ensure that at least two of the floating diffusion regions are respectively connected to a different transfer transistor when a plurality of floating diffusion regions are provided. Preferably, the number of the transfer transistors is the same as the number of the floating diffusion regions. For example, when the number of the transfer transistors is 2, the number of the floating diffusion regions is also 2, and the above values are merely for example and do not specifically limit the number of the transfer transistors and the floating diffusion regions. Further, the transfer transistors are connected to the floating diffusion regions in a one-to-one correspondence. For example, as shown in fig. 1A, the floating diffusion FD1 is connected to the transfer transistor Tx1, and the floating diffusion FD2 is connected to the transfer transistor Tx 2.

Illustratively, the CMOS image sensor further includes a reset transistor Rx, and the floating diffusions FD1, FD2 are located between the transfer transistors Tx1, Tx2 and the reset transistor Rx. Further, the CMOS image sensor further includes a selection transistor Sx and a driving transistor Dx formed on the semiconductor substrate.

The reset transistor Rx, the select transistor Sx, and the driving transistor Dx each include a gate structure formed on the semiconductor substrate, and source and drain regions of the same doping type as the first doping region 101 are also formed in the semiconductor substrate on both sides of the gate structure, that is, the source and drain regions are of the second conductivity type.

In the above, the first conductive type is a P type, and the second conductive type is an N type, or the first conductive type is an N type, and the second conductive type is a P type, which are selected according to an actual device type.

The CMOS image sensor based on the above adopts the following operation method to optimize both the minimum sensitivity and the saturation sensitivity of the CIS at the same time.

After the transfer transistor is turned on, photogenerated carriers in the PD region enter the floating diffusion region, and the charge amount of the photogenerated carriers is △ Q, so that the voltage change △ V generated by the PN junction capacitance of each floating diffusion region is △ Q/C, △ V reflects the intensity of external illumination.

From the above equation, when the light irradiation is weak, △ Q generated is small, and C should be reduced to obtain a large △ V in order to sense a small change in △ Q.

When external light is weak, only part of the transfer transistors are turned on, and carriers generated in the photodiode region enter only the floating diffusion region connected to the turned-on transfer transistors, so that the minimum sensitivity of the CMOS image sensor is improved by reducing the capacitance of the floating diffusion region.

Taking the CMOS image sensor shown in fig. 1A as an example, when the external light is weak, only the transfer transistor Tx1 is turned on and the transfer transistor Tx2 is turned off, or only the transfer transistor Tx2 is turned on and the transfer transistor Tx1 is turned off. As shown in fig. 2A and 2B, taking as an example that only the transfer transistor Tx1 is turned on and the transfer transistor Tx2 is turned off, carriers generated by the photodiode region PD enter only the floating diffusion region FD 1. Since the floating diffusion FD2 does not function, the effective area of the floating diffusion FD decreases, the C of the floating diffusion FD decreases, and the minimum sensitivity of the CIS can be improved.

On the other hand, in strong light, △ Q obtained is large, and C should be increased in order to raise the upper limit of the charge stored in the floating diffusion region and prevent the overflow due to charge saturation.

The operation method comprises the following steps: when external light is weak, all the transmission transistors are turned on simultaneously, and carriers generated in the photodiode region enter the floating diffusion region connected with the turned-on transmission transistors, so that the capacitance of the floating diffusion region is increased, and the saturation sensitivity of the CMOS image sensor is improved.

As shown in fig. 2C and 2D, when the external light is strong, the transfer transistor Tx1 and the transfer transistor Tx2 are simultaneously turned on. Carriers generated by the photodiode region PD enter the floating diffusion region FD1 and the floating diffusion region FD 2. Since the floating diffusion FD1 and the floating diffusion FD2 function simultaneously, the effective area of the floating diffusion FD increases, C of the floating diffusion FD increases, and saturation sensitivity of the CIS can be improved.

In another embodiment of the present invention, the floating diffusion FD may also be divided into 2 or more small floating diffusions, e.g., 3, 4, 5, etc. As shown in fig. 3, the floating diffusion FD is divided into floating diffusions FD1, FD2 and FD3 by the gates of transfer transistors Tx1, Tx2 and Tx3, each of which is connected to one transfer transistor.

The operation method comprises the following steps: when external light is weak, only part of the transmission transistors are turned on, for example, any two of the three transistors are turned on, one is turned off, or any one is turned on and the other two are turned off, and carriers generated in the photodiode region enter only the floating diffusion region connected to the turned-on transmission transistor, so that the capacitance of the floating diffusion region is reduced to improve the minimum sensitivity of the CMOS image sensor. When external light is weak, all the transmission transistors are turned on simultaneously, and carriers generated in the photodiode region enter the floating diffusion region connected with the turned-on transmission transistors, so that the capacitance of the floating diffusion region is increased, and the saturation sensitivity of the CMOS image sensor is improved.

In summary, the CMOS image sensor of the present invention uses multiple transfer gates to control the effective capacitance of the floating diffusion FD, so that the capacitance of the floating diffusion FD can be adjusted according to actual needs, and simultaneously, the minimum sensitivity and saturation sensitivity of the CIS are optimized, thereby further improving the performance of the CMOS image sensor.

Example two

Next, a method for manufacturing a CMOS semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 4, fig. 5A to 5B, fig. 6A to 6B, fig. 7A to 7B, fig. 8A to 8B, fig. 9A to 9B, and fig. 10.

First, as shown in fig. 4, a semiconductor substrate 400 having a first conductivity type is provided. The semiconductor substrate 400 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. An isolation structure (not shown) is formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. The first conductive type may be N-type or P-type, and the P-type semiconductor substrate 400 is taken as an example in this embodiment.

In one example, an epitaxial layer is also included overlying a portion of the semiconductor substrate, the epitaxial layer being heavily doped with the first conductivity type for forming the photodiode region. For example, the epitaxial layer is a P + epitaxial layer. Optionally, the width of the epitaxial layer is in the range of 2-10 μm.

Next, as shown in fig. 5A and 5B, at least two transfer transistors Tx1, Tx2 are formed on the semiconductor substrate, the transfer transistors Tx1, Tx2 including a gate structure formed on the semiconductor substrate 400. The gate structure includes a gate dielectric layer 4011 and a gate material layer 4012 sequentially formed on the semiconductor substrate 400.

The gate dielectric layer 4011 may comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer 4011 can comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). The gate dielectric layer may be formed by any of several methods that are suitable for the material of the gate dielectric layer composition. Including but not limited to thermal or plasma oxidation or nitridation processes, chemical vapor deposition processes, and physical vapor deposition processes.

The gate material layer 4012 may comprise various materials including, but not limited to: certain metals, metal alloys, metal nitrides and metal silicides, and laminates and composites thereof. The gate material layer 4012 may also comprise doped polysilicon and polysilicon-germanium alloy materials (i.e., having a dopant concentration of from about 1e18 to about 1e22 dopant atoms per cubic centimeter) and polysilicon metal silicide (polycide) materials (doped polysilicon/metal silicide stack materials). Similarly, any of several methods may be employed to form the foregoing materials. Non-limiting examples include salicide methods, chemical vapor deposition methods, and physical vapor deposition methods, such as but not limited to: evaporation methods and sputtering methods. Typically, the gate material layer 4012 comprises a doped polysilicon material having a thickness from about 50 to about 2000 angstroms.

The size and shape of the gate structure pattern of the transfer transistor can be defined by a photolithography process and an etching process, which are not described herein.

Further, a reset transistor Rx spaced apart from the transfer transistors Tx1, Tx2 is formed on the semiconductor substrate, the reset transistor Rx and a photodiode region PD formed later are located on different sides of the transfer transistors Tx1, Tx2, a region of the semiconductor substrate between the transfer transistors Tx1, Tx2 and the reset transistor Rx is used for forming the floating diffusion region, and the reset transistor Rx includes a gate structure formed on the semiconductor substrate.

In one example, a driving transistor Dx and a selection transistor Sx, both of which include gate structures, may be simultaneously formed on the semiconductor substrate.

The gate structure comprises a gate dielectric layer and a gate material layer which are sequentially formed on the semiconductor substrate.

Next, as shown in fig. 6A and 6B, an ion implantation process is performed on a portion of the semiconductor substrate 400 on the side of the transfer transistors Tx1, Tx2 to form a first doped region 402 having a second conductivity type opposite to the first conductivity type, and a portion of the semiconductor substrate 400 and the first doped region 402 constitute a photodiode region PD.

The second conductive type may be an N type or a P type, and is specifically selected according to the type of the actually fabricated device. In the embodiment, the second conductivity type is N type, and the ion implantation process uses phosphorus implantation with a dose of 1E12cm³～1E16/cm³. The transfer transistor is connected to the photodiode region.

Next, as shown in fig. 7A and 7B, spacers 4013 are formed on the sidewalls of the gate structures of the transmission transistors Tx1 and Tx 2.

Further, spacers may be formed on the sidewalls of the gate structures of the driving transistor Dx, the reset transistor Rx, and the select transistor Sx at the same time.

The spacer 4013 may be made of silicon oxide, silicon nitride, or silicon oxynitride. As a preferred implementation of this embodiment, the spacer is composed of silicon oxide and silicon nitride, and the specific process includes: a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are formed on a semiconductor substrate, and then a spacer is formed by an etching method. It should be noted that the spacer structure is optional and not necessary, and is mainly used to protect the sidewalls of the gate structure from being damaged during the subsequent etching or ion implantation.

Next, as shown in fig. 8A and 8B, at least two floating diffusions FD1 and FD2 are formed in the semiconductor substrate 400 at intervals on the other side of the transfer transistors Tx1 and Tx2, each of the floating diffusions being connected to one of the transfer transistors, respectively, and including a second doped region 403 of the second conductivity type formed in the semiconductor substrate, each of the floating diffusions having a junction capacitance.

In one example, the second diffusion region having the second conductivity type is formed by means of ion implantation.

Each of the floating diffusions is connected to one of the transfer transistors, for example, the floating diffusion FD1 is connected to the transfer transistor Tx1, the floating diffusion FD2 is connected to the transfer transistor Tx2, each of the floating diffusions FD1 and FD2 has a junction capacitance, the floating diffusions FD1 and FD2 include a second doped region 403 having a second conductivity type opposite to the first conductivity type, for example, when the semiconductor substrate is a P-type semiconductor substrate, the second doped region is an N-type doped region, and the second doped region and the P-type semiconductor substrate form a PN junction, that is, a PN junction capacitance, as shown in fig. 1B.

Preferably, the number of the transfer transistors is the same as the number of the floating diffusion regions. For example, when the number of the transfer transistors is 2, the number of the floating diffusion regions is also 2, and the above values are merely for example and do not specifically limit the number of the transfer transistors and the floating diffusion regions. The number of floating diffusion regions should be at least 2 or more, and may be 3, 4, 5, or the like.

Next, as shown in fig. 9A and 9B, source/drain region ion implantation of the reset transistor Rx, the drive transistor Dx, and the selection transistor Sx is performed to form source/drain regions having the second conductivity type. For example, when the floating diffusion region is N-type, the source/drain regions of the reset transistor, the driving transistor, and the selection transistor are also N-type.

Thereafter, conventional processes may be performed, such as continuing to form an interlayer dielectric layer covering the semiconductor substrate and the gate structure; and forming a back line layer (BEOL) on the interlayer dielectric layer, including a dielectric layer, a metal wiring layer, a filter layer, a planarization layer, a microlens layer, etc., which are formed in sequence, and details are not described herein. And finally, performing back-end packaging.

In summary, the CMOS image sensor formed by the manufacturing method of the present invention uses multiple transfer gates to control the effective capacitance of the floating diffusion FD, so that the capacitance of the floating diffusion FD can be adjusted according to actual needs, and meanwhile, the minimum sensitivity and saturation sensitivity of the CIS are optimized, thereby further improving the performance of the CMOS image sensor.

Fig. 10 is a flow chart showing an exemplary method of fabricating a CMOS image sensor according to an embodiment of the present invention, which is used to briefly show the flow of the entire fabrication process. The method specifically comprises the following steps:

step S1001 of providing a semiconductor substrate having a first conductivity type;

step S1002, forming at least two transmission transistors on the semiconductor substrate, the transmission transistors including a gate structure formed on the semiconductor substrate;

step S1003, performing an ion implantation process on a portion of the semiconductor substrate on one side of the transfer transistor to form a first doped region having a second conductivity type, where the second conductivity type is opposite to the first conductivity type, and a portion of the semiconductor substrate and the first doped region form a photodiode region;

step S1004 is to form at least two floating diffusion regions spaced apart in the semiconductor substrate on the other side of the transfer transistor, each floating diffusion region being connected to one of the transfer transistors, the floating diffusion regions including a second doped region having a second conductivity type formed in the semiconductor substrate, each floating diffusion region having a junction capacitance.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A CMOS image sensor, comprising:

a semiconductor substrate having a first conductivity type;

at least two floating diffusion regions spaced apart in the semiconductor substrate and on the other side of the transfer transistor, wherein the at least two floating diffusion regions are respectively connected to a different one of the transfer transistors,

wherein the at least two transmission transistors are located at the same side of the photodiode region;

further comprising a reset transistor, said at least two floating diffusions being located between said at least two pass transistors and said reset transistor,

the at least two pass transistors are connected to the same reset transistor, and only a portion of the pass transistors or all of the pass transistors are turned on by the reset transistor.

2. The CMOS image sensor of claim 1, wherein the number of transfer transistors is the same as the number of floating diffusions.

3. The CMOS image sensor of claim 2, wherein the transfer transistors are connected to the floating diffusions in a one-to-one correspondence.

4. The CMOS image sensor of claim 1, wherein each of the pass transistors comprises a gate structure on the semiconductor substrate.

5. The CMOS image sensor of claim 4, wherein said gate structure comprises a gate dielectric layer and a gate material layer sequentially on said semiconductor substrate.

6. The CMOS image sensor of claim 4, wherein a spacer is further formed on sidewalls of said gate structure.

7. The CMOS image sensor of claim 1, further comprising a select transistor and a drive transistor formed on the semiconductor substrate.

8. The CMOS image sensor of claim 7, wherein the photodiode region comprises a first doped region formed in the semiconductor substrate having a second conductivity type, the second conductivity type being opposite the first conductivity type.

9. The CMOS image sensor of claim 1, further comprising an epitaxial layer overlying a portion of the semiconductor substrate, the epitaxial layer being heavily doped to have the first conductivity type, the photodiode region being located within the epitaxial layer.

10. The CMOS image sensor of claim 9, wherein the epitaxial layer has a width in the range of 2-10 μ ι η.

11. The CMOS image sensor of claim 8, wherein the first conductivity type is P-type and the second conductivity type is N-type, or wherein the first conductivity type is N-type and the second conductivity type is P-type.

12. The CMOS image sensor of claim 8, wherein the reset transistor comprises a gate structure formed on the semiconductor substrate, and source and drain regions of the same doping type as the first doping region are further formed in the semiconductor substrate on both sides of the gate structure.

13. The CMOS image sensor according to claim 8, wherein the selection transistor and the driving transistor each include a gate structure formed on the semiconductor substrate, and source and drain regions of the same doping type as the first doping region are further formed in the semiconductor substrate on both sides of the gate structure.

14. A method of operation based on a CMOS image sensor as claimed in any one of claims 1 to 13, comprising:

15. A method for fabricating a CMOS image sensor includes:

step A1: providing a semiconductor substrate having a first conductivity type;

16. The method of claim 15 further comprising a step a1 of forming an epitaxial layer overlying a portion of the semiconductor substrate, the epitaxial layer being heavily doped to have the first conductivity type to form the photodiode region.

17. The method of claim 16, wherein the epitaxial layer has a width in the range of 2-10 μm.

18. The method of claim 15, wherein step a2 further comprises: and forming a reset transistor on the semiconductor substrate, wherein the reset transistor and the photodiode region are positioned at different sides of the transmission transistor, the semiconductor substrate region between the transmission transistor and the reset transistor is used for forming the floating diffusion region, and the reset transistor comprises a gate structure formed on the semiconductor substrate.

19. The method of claim 18, wherein said step a2 further comprises: and forming a driving transistor and a selection transistor on the semiconductor substrate, wherein the driving transistor and the selection transistor both comprise gate structures.

20. The method of claim 15, further comprising a step of forming spacers on sidewalls of a gate structure of the pass transistor after the step A3 and before the step a 4.

21. The method of claim 19, further comprising, after the step a4, the steps of:

and carrying out back-end packaging.

22. The method of claim 15, 18 or 19, wherein the gate structure comprises a gate dielectric layer and a gate material layer sequentially formed on the semiconductor substrate.

23. The method of claim 15, wherein the first conductivity type is P-type and the second conductivity type is N-type, or wherein the first conductivity type is N-type and the second conductivity type is P-type.