CN106298767A - There is semiconductor device and the manufacture method thereof of electrostatic discharge protection diode - Google Patents
There is semiconductor device and the manufacture method thereof of electrostatic discharge protection diode Download PDFInfo
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- CN106298767A CN106298767A CN201510299757.XA CN201510299757A CN106298767A CN 106298767 A CN106298767 A CN 106298767A CN 201510299757 A CN201510299757 A CN 201510299757A CN 106298767 A CN106298767 A CN 106298767A
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Abstract
The invention discloses a kind of semiconductor device with electrostatic discharge protection diode and manufacture method thereof, this manufacture method includes: S1, subregion to the epitaxial layer of semiconductor device substrates aoxidize, and forms oxide in field；S2, oxide in field is performed etching, make epitaxial layer at the upper surface of oxide in field less than the upper surface in non-oxide in field；S3 and on the first oxide layer and field oxide deposit polycrystalline silicon layer；S4, etches polycrystalline silicon, formed and be positioned at the Electro-static Driven Comb polysilicon of oxide in field and be positioned at the grid polycrystalline silicon in non-oxide region, and makes the upper surface upper surface less than grid polycrystalline silicon of Electro-static Driven Comb polysilicon；S5, step S4 generate structure upper surface deposit the second oxide layer；S6, grind the second oxide layer, for exposing the upper surface of grid polycrystalline silicon；S7, deposition Titanium, and generate titanium silicon.The method of the present invention can realize the effect protecting diode to reduce gate resistance while normally working.
Description
Technical field
Present invention relates particularly to a kind of semiconductor device with electrostatic discharge protection diode and
Its manufacture method.
Background technology
RF power device LDMOS (lateral double diffusion metal oxide semiconductor) is usually used in
The fields such as cellular base station, radio and television and radar.Due to radiofrequency characteristics, it is different from other
Power MOS pipe, RF power device LDMOS is high to the requirement of gate resistance, and
Gate resistance is the least, it is therefore necessary to use grid resistance lowering technique to reduce gate resistance.Typically
In the case of, reduce gate resistance and realize by forming metal silicide on grid.
For ensureing reliable operation, can integrated static release on RF power device LDMOS
(Electro-Static Discharge, ESD) protects diode.Generally ESD protects two poles
Pipe makes face on the polysilicon, and can not form metal silicide above, and otherwise ESD protects
Protect diode by short circuit, do not have ESD protection effect.
The material that the comparison of making metal silicide is feasible has Ti (titanium), Co (cobalt), Ni (nickel).
At present, cmp (Chemical Mechanical Polishing, CMP) side is used
Method, can there is the problem that RF power device LDMOS grid polycrystalline silicon and
Make and concurrently form metal silicide on the polysilicon of ESD protection diode.
Existing CMP method, specifically includes following steps:
The first step, in extension, as it is shown in figure 1, with LOCOS (Local Oxidation of
Silicon, local oxidation of silicon) technique formation field oxide；
Second step, as in figure 2 it is shown, form the first oxide layer, and deposit polycrystalline silicon；
3rd step, forms grid polycrystalline silicon and ESD polysilicon with photoetching and etching technics.As
Shown in Fig. 3, ESD polysilicon is placed on field oxide, and grid polycrystalline silicon is placed on active
On first oxide layer in district；
4th step, as shown in Figure 4, define body district, drift region, and carry out source/drain region injection,
P+ injects；This process also form cathode chamber and the anode region of ESD diode simultaneously；
5th step, as it is shown in figure 5, the oxide layer of deposition thick layer；
6th step, as it is shown in fig. 7, be ground to polysilicon with CMP (cmp)；
7th step, as shown in Figure 8, carries out the processing step of metallic compound.
In above-mentioned process, owing to grid polycrystalline silicon and ESD polysilicon are in same level
On face, so at the end of CMP, the surface of the polysilicon in the two region all can expose
Come.So, metal silicide will all be formed on the polysilicon in the two region.
Metal silicide on ESD polysilicon can cause ESD short circuit, loses the ESD to device
Protection.
In sum, on the one hand, need on RF power device LDMOS grid electrode polysilicon
Form metal silicide；On the other hand, making can not on the polysilicon of ESD protection diode
Forming metal silicide, therefore, above-mentioned two aspects are the formation of contradiction.
Summary of the invention
For defect of the prior art, the present invention provides one to have electrostatic discharge protection two pole
The semiconductor device of pipe and manufacture method thereof, can solve to be formed metallic silicon on grid polycrystalline silicon
Compound is formed without the technical problem of metal silicide on ESD polysilicon simultaneously, it is achieved ESD
Protection diode reduces the effect of gate resistance while normally working.
First aspect, the invention provides a kind of quasiconductor with electrostatic discharge protection diode
The manufacture method of device, comprises the following steps:
S1, subregion to the epitaxial layer of semiconductor device substrates aoxidize, and form field oxygen
Change region；
S2, described oxide in field is performed etching, make epitaxial layer in described oxide in field
Upper surface is less than the upper surface in non-oxide in field；
S3, form the first oxide layer at the upper surface of the epitaxial layer of described non-oxide in field, and
Deposit polycrystalline silicon layer on described first oxide layer with described oxide in field；
S4, etch described polysilicon, form the Electro-static Driven Comb polycrystalline being positioned at described oxide in field
Silicon and be positioned at the grid polycrystalline silicon of described non-oxide in field, and make described Electro-static Driven Comb polycrystalline
The upper surface of silicon is less than the upper surface of described grid polycrystalline silicon；
S5, deposit the second oxide layer at the structure upper surface generated through step S4；
S6, grind described second oxide layer, expose the upper surface of described grid polycrystalline silicon；
S7, through described step 6 formed structure upper surface deposition Titanium, and generate titanium silicon close
Gold.
Alternatively, after described step S7, including:
S8, clean remaining Titanium, and utilize short annealing mode to change described titanium silicon
Alloy phase, to reduce the resistivity of described titanium silicon.
Alternatively, the described field oxide thickness that described step S1 is formed is 8000～30000
Angstrom.
Alternatively, in described step S2, wet-etching technology is used to etch described field oxide,
Etch thicknesses is 55%～65% with the ratio of the thickness of the described oxide in field of formation.
Alternatively, the thickness of the described polysilicon layer formed in described step S3 is 1500～4000
Angstrom.
Alternatively, the thickness of the described oxide regions formed in described step S5 is described step
2～3 times of the described polysilicon layer thicknesses formed in 3.
Alternatively, in described step S7, generate described titanium silicon and use rapid thermal annealing side
Method, temperature is between 650～750 degree, and the persistent period is between 20～40 seconds.
Alternatively, in described step S8, described cleaning medicinal liquid is the mixing of sulphuric acid and hydrogen peroxide
The mixed liquor of liquid or ammonia and hydrogen peroxide.
Alternatively, in described step S8, the temperature of rapid thermal annealing mode is between 850～900
Between degree, persistent period 20～40 seconds.
Second aspect, present invention also offers and a kind of have partly leading of electrostatic discharge protection diode
Body device, uses method as discussed above to make.
As shown from the above technical solution, the present invention is by etching field oxide downwards so that
The ESD polysilicon being placed on field oxide is less than and is placed in the grid polycrystalline silicon in the first oxide layer,
Thus after CMP terminates, grid polycrystalline silicon exposes and ESD polysilicon also has enough oxidations
Layer protection, it is possible to achieve ESD protection diode reduces the effect of gate resistance while normally working
Really.
Accompanying drawing explanation
By being more clearly understood from the features and advantages of the present invention with reference to accompanying drawing, accompanying drawing is to show
Meaning property and should not be construed as the present invention is carried out any restriction, in the accompanying drawings:
Fig. 1 to Fig. 7 is a kind of quasiconductor with electrostatic discharge protection diode in prior art
The sectional view of the structure in the process for making of device；
Fig. 8 is a kind of quasiconductor with electrostatic discharge protection diode in one embodiment of the invention
The manufacture method flow chart of device；
Fig. 9 is in one embodiment of the invention, the method flow diagram of etching field oxide；
Figure 10 to Figure 19 shows have electrostatic discharge protection two pole in one embodiment of the invention
The sectional view of the structure in the process for making of the semiconductor device of pipe.
Detailed description of the invention
Below in conjunction with accompanying drawing, embodiments of the present invention is described in detail.
The invention provides the system of a kind of semiconductor device with electrostatic discharge protection diode
Make method, as shown in Figure 8, specifically include:
S1, subregion to the epitaxial layer of semiconductor device substrates aoxidize, and form field oxygen
Change region；
S2, oxide in field is performed etching, make epitaxial layer low at the upper surface of oxide in field
In the upper surface in non-oxide in field；
S3, form the first oxide layer at the upper surface of the epitaxial layer of non-oxide in field, and
Deposit polycrystalline silicon layer on one oxide layer and oxide in field；
S4, etches polycrystalline silicon, form Electro-static Driven Comb polysilicon and the position being positioned at oxide in field
In the grid polycrystalline silicon of non-oxide in field, and make the upper surface of Electro-static Driven Comb polysilicon less than grid
The upper surface of pole polysilicon；
S5, deposit the second oxide layer at the structure upper surface generated through step S4；
S6, grind the second oxide layer, expose the upper surface of grid polycrystalline silicon；
S7, form structure upper surface deposition Titanium through step 6, and generate titanium silicon.
Visible, the embodiment of the present invention, by etching field oxide, makes field oxide be less than the first oxygen
Change layer, carry out the ESD polysilicon so that being placed on field oxide less than being placed in the first oxide layer
Grid polycrystalline silicon so that chemical mechanical planarization process terminates the upper surface energy of post tensioned unbonded prestressed concrete polysilicon
Enough coming out, ESD polysilicon upper surface also has enough oxide layers to protect, thus only
Form titanium silicon at grid polycrystalline silicon upper surface, thus realize ESD and protect the normal work of diode
The effect of gate resistance can be reduced while work.
Similarly, in the embodiment of the present invention, making metal silicide can also be for having cobalt and nickel etc.
Material.
In the specific implementation, above-mentioned steps S2 can be as it is shown in figure 9, include:
S21, the etch thicknesses of field oxide is set；
S22, employing wet-etching technology etching field oxide.
Optionally, in the present embodiment, this etch thicknesses with the ratio of field oxide thickness is
55%～65% so that the upper surface of field oxide is less than the upper surface of non-field oxide.
Alternatively, the step reducing titanium silicon resistivity is also included when being embodied as after step S7
Suddenly, including:
S8, clean remaining Titanium, and utilize short annealing mode to change the conjunction of titanium silicon
Metallographic, to reduce the resistivity of titanium silicon, meets the requirement that semiconductor device gate resistance is less.
What Figure 10 to Figure 19 showed one embodiment of the invention has electrostatic discharge protection two pole
The sectional view of the structure during the manufacture method of the semiconductor device of pipe.
Figure 10 shows the structural section figure formed after step S1.As shown in Figure 10, partly leading
One surface of the substrate 1 of body device forms epitaxial layer 2, carries out the local of silicon at this epitaxial layer 2
Oxidation, forms oxide in field 3.The thickness of this oxide in field 3 between 8000～30000 angstroms it
Between.Substrate is not construed as limiting with the epitaxial film materials present invention.Additionally, between substrate and extension
Adhesive layer, cushion and other layers (Figure 10 does not marks) can also be included.People in the art
Member is it will be recognized that many change programmes, modification and replacement scheme.
The structural section figure that Figure 11 is formed after showing step S2.As shown in figure 11, the present invention
In one embodiment, use wet-etching technology etching oxide in field 3, alternatively, etching
Thickness is 55%～65% with the thickness ratio of field oxide, so that oxide in field 3 is upper
Surface is less than the upper surface of epitaxial layer 2.
In actual applications, it is also possible to use dry etch process etching oxide in field 3, originally
The technical staff in field can select as the case may be, and the present invention is not construed as limiting.
The structural section figure that Figure 12 is formed after showing step S3.As shown in figure 12, at epitaxial layer
The upper surface of 2 forms the first oxide layer 4, thickness between 150～400 angstroms, oxidation the most on the scene
Region 3 and the upper surface deposit polycrystalline silicon 5 of epitaxial layer 2.The present embodiment when deposit polycrystalline silicon 5,
Owing to oxide in field 3 is identical with the environment residing for epitaxial layer 2, therefore, the polysilicon energy of formation
Enough being uniformly covered on the upper surface of oxide in field 3 and epitaxial layer 2, thickness arrives at 1500 angstroms
Between 4000 angstroms.
The structural section figure that Figure 13 is formed after showing step S4.As shown in figure 13, field oxide region
The ESD polysilicon 52 of territory 3 upper surface and the grid polycrystalline silicon being positioned at the first oxide layer 4 upper surface
51 form for same process deposits, and thickness is identical.
It should be noted that the present invention is positioned at the ESD polysilicon of oxide in field 3 upper surface
52 can differ with the thickness of the grid polycrystalline silicon 51 being positioned at the first oxide layer 4 upper surface.I.e.
Now need point 2 deposit polycrystalline silicon, it is achieved the thickness of polysilicon is different.Such as first first
Oxide layer 4 upper surface deposit polycrystalline silicon, forms grid polycrystalline silicon 51 through photoetching and etching；Again
At oxide in field 3 upper surface deposit polycrystalline silicon, formed in the oxidation of field through photoetching and etching
ESD polysilicon 52.The thickness of ESD polysilicon 52 can be less than the thickness of grid polycrystalline silicon 51.
The thickness of ESD polysilicon 52 can also more than the thickness of grid polycrystalline silicon 51, but remain a need for protecting
The upper surface of card ESD polysilicon 52 is less than the upper surface of grid polycrystalline silicon 51.For deposit polycrystalline
The process of silicon, the present invention is not construed as limiting.
Figure 14 shows formation definition body district, drift region, and carries out the cross section of source/drain region injection
Figure.As shown in figure 14, definition define body district 6, drift region 7 and drain region 81, source region 82,
ESD cathode chamber, anode region 92, P+ district 91 and ESD.The contents of the section is prior art, this reality
Execute example no longer to describe in detail.
The structural section figure that Figure 15 is formed after showing step S5.As shown in figure 15, the second oxidation
Layer 10 is by ESD polysilicon 52, grid polycrystalline silicon 51, oxide in field 3 and the first oxide layer 4
Upper surface covers.Alternatively, the present embodiment uses chemical vapor deposition the
Dioxide layer 10, the second oxide layer 10 is silicon dioxide, and thickness is 2～3 times of polysilicon thickness.
Material to the second oxide layer, the present invention is not construed as limiting.
The structural section figure that Figure 15 is formed after showing step S6.As shown in figure 16, to the second oxygen
Change layer 10 to be ground until exposing grid polycrystalline silicon 51.Upper surface due to ESD polysilicon 52
Less than grid polycrystalline silicon 51, therefore, after process of lapping, the upper surface of ESD polysilicon also covers
There is silicon dioxide.This silicon dioxide can protect ESD polysilicon, prevents it in subsequent technique
Form metal silicide.In the present embodiment, chemical and mechanical grinding method is used to grind this second oxygen
Change layer 10.
The structural section figure that Figure 17 is formed after showing step S7.As shown in figure 17, this Titanium
Layer 11 covers grid polycrystalline silicon 51 and the remainders of the second oxide layer 10, thickness between
Between 200～1000 angstroms.
The structural section figure that Figure 18 is formed after showing step S8.As shown in figure 18 so that metal
Titanium layer 11 reacts with grid polycrystalline silicon 51, generates titanium silicon 12.In the present embodiment, adopt
Using rapid thermal annealing mode, temperature be arranged between 650～750 degree, the persistent period is 20～40
Second so that Titanium can react with polysilicon, and, at this temperature Titanium with
Second oxide layer 10 does not reacts, thus only at upper surface and the metal of grid polycrystalline silicon 51
The part of titanium contact generates titanium silicon.
Figure 19 shows the sectional view reducing titanium silicon resistivity.As shown in figure 19, carrying out
Before titanium silicon reduces resistivity, in addition it is also necessary to remove the Titanium having neither part nor lot in reaction.This enforcement
In example, clean medicinal liquid and can select sulphuric acid (H2SO4) and the mixing of hydrogen peroxide (H2O2)
Liquid, it is also possible to select ammonia (NH4OH) and the mixed liquor of hydrogen peroxide (H2O2).Clean
Titanium only removed by medicinal liquid, without removing the second oxide layer 10.For meeting RF power device
The LDMOS requirement to requiring that gate resistance is the least, also uses grid low-resistance in the present embodiment
Metallization processes reduces gate resistance.Utilize rapid thermal annealing mode, make temperature between 850～900 degree it
Between, time 20～40 seconds so that the alloy of titanium silicon changes mutually, reduce titanium silicon
Resistivity.
It is titanium that the present invention can use, cobalt, and any one of nickel generates metal silicide, for
Different metals, the temperature of twice corresponding rapid thermal annealing is different, and the persistent period also has accordingly
Change.The present embodiment has been described in detail for Titanium, for other metals,
The present invention repeats the most one by one.
For make semiconductor device continuation steps, such as aperture layer, metal line, sheath,
The techniques such as the thinning and back of the body is golden, use prior art to realize, and the present invention is not described in detail in this.
Another embodiment of the present invention provides and obtains based on any one manufacture method above-mentioned
There is the semiconductor device of electrostatic discharge protection diode, the ESD protection two of this semiconductor device
The upper surface of pole pipe is less than the upper surface of grid polycrystalline silicon, and the upper table of ESD protection diode
Face also has oxide layer to protect, thus in generating titanium silicon technique, only at grid polycrystalline
Silicon generates titanium silicon, and is reduced the resistivity of titanium silicon by alloy inversion of phases so that
ESD protection diode reduces gate resistance while normally working, and solves chemistry in prior art
Mechanical grinding method concurrently forms gold on grating of semiconductor element polysilicon and ESD polysilicon
The problem belonging to silicide, it is achieved that the effect that ESD protection diode normally works and gate resistance is less
Really.
In describing the invention it should be noted that term " on ", the side of the instruction such as D score
Position or position relationship are based on orientation shown in the drawings or position relationship, are for only for ease of description
The present invention and simplification describe rather than indicate or imply that the device of indication or element must have spy
Fixed orientation, with specific azimuth configuration and operation, therefore it is not intended that limit to the present invention
System.Unless otherwise clearly defined and limited, term " install ", " being connected ", " connection " should
It is interpreted broadly, connects for example, it may be fixing, it is also possible to be to removably connect, or one
Ground connects；Can be to be mechanically connected, it is also possible to be electrical connection；Can be to be joined directly together, it is possible to
To be indirectly connected to by intermediary, it can be the connection of two element internals.For this area
Those of ordinary skill for, can understand that above-mentioned term is in the present invention as the case may be
Concrete meaning.
Also, it should be noted in this article, the relational terms of such as first and second or the like
It is used merely to separate an entity or operation with another entity or operating space, and differs
Provisioning request or imply these entities or operation between exist any this reality relation or
Sequentially.And, term " includes ", " comprising " or its any other variant are intended to non-
Comprising of exclusiveness, so that include the process of a series of key element, method, article or set
For not only including those key elements, but also include other key elements being not expressly set out, or
Also include the key element intrinsic for this process, method, article or equipment.The most more
In the case of restriction, statement " including ... " key element limited, it is not excluded that at bag
Include and the process of described key element, method, article or equipment there is also other identical element.
Embodiment of above is merely to illustrate the present invention, and not limitation of the present invention, relevant
The those of ordinary skill of technical field, without departing from the spirit and scope of the present invention,
Can also make a variety of changes and modification, the technical scheme of the most all equivalents falls within the present invention
Category, the scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. there is a manufacture method for the semiconductor device of electrostatic discharge protection diode, its
It is characterised by, comprises the following steps:
S1, subregion to the epitaxial layer of semiconductor device substrates aoxidize, and form field oxygen
Change region；
S2, described oxide in field is performed etching, make epitaxial layer in described oxide in field
Upper surface is less than the upper surface in non-oxide in field；
S3, form the first oxide layer at the upper surface of the epitaxial layer of described non-oxide in field, and
Deposit polycrystalline silicon layer on described first oxide layer with described oxide in field；
S4, etch described polysilicon, form the Electro-static Driven Comb polycrystalline being positioned at described oxide in field
Silicon and be positioned at the grid polycrystalline silicon of described non-oxide in field, and make described Electro-static Driven Comb polycrystalline
The upper surface of silicon is less than the upper surface of described grid polycrystalline silicon；
S5, deposit the second oxide layer at the structure upper surface generated through step S4；
S6, grind described second oxide layer, expose the upper surface of described grid polycrystalline silicon；
S7, through described step 6 formed structure upper surface deposition Titanium, and generate titanium silicon close
Gold.
2. manufacture method as claimed in claim 1, it is characterised in that
After described step S7, including:
S8, clean remaining Titanium, and utilize short annealing mode to change described titanium silicon
Alloy phase, to reduce the resistivity of described titanium silicon.
3. manufacture method as claimed in claim 1, it is characterised in that
The described field oxide thickness that described step S1 is formed is 8000～30000 angstroms.
4. the manufacture method as described in claim 1 or 3, it is characterised in that described step
In S2, wet-etching technology is used to etch the institute of described field oxide, etch thicknesses and formation
The ratio of the thickness stating oxide in field is 55%～65%.
5. manufacture method as claimed in claim 1, it is characterised in that
The thickness of the described polysilicon layer formed in described step S3 is 1500～4000 angstroms.
6. manufacture method as claimed in claim 1, it is characterised in that
The thickness of the described oxide regions formed in described step S5 is to be formed in described step 3
2～3 times of described polysilicon layer thicknesses.
7. manufacture method as claimed in claim 1, it is characterised in that
In described step S7, generate described titanium silicon and use quick thermal annealing method, temperature
Between 650～750 degree, the persistent period is between 20～40 seconds.
8. manufacture method as claimed in claim 2, it is characterised in that
In described step S8, described cleaning medicinal liquid is sulphuric acid and the mixed liquor of hydrogen peroxide or ammonia
Water and the mixed liquor of hydrogen peroxide.
9. manufacture method as claimed in claim 2, it is characterised in that
In described step S8, the temperature of rapid thermal annealing mode between 850～900 degree,
Persistent period 20～40 seconds.
10. a semiconductor device with electrostatic discharge protection diode, it is characterised in that
It is made up of the manufacture method described in any one of claim 1～9.
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| CN201510299757.XA CN106298767B (en) | 2015-06-03 | 2015-06-03 | Semiconductor devices and its manufacturing method with electrostatic discharge protection diode |
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| CN201510299757.XA CN106298767B (en) | 2015-06-03 | 2015-06-03 | Semiconductor devices and its manufacturing method with electrostatic discharge protection diode |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112563139A (en) * | 2020-11-17 | 2021-03-26 | 深圳宝铭微电子有限公司 | SGT manufacturing process of MOS (metal oxide semiconductor) tube |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5403759A (en) * | 1992-10-02 | 1995-04-04 | Texas Instruments Incorporated | Method of making thin film transistor and a silicide local interconnect |
| US6063706A (en) * | 1998-01-28 | 2000-05-16 | Texas Instruments--Acer Incorporated | Method to simulataneously fabricate the self-aligned silicided devices and ESD protective devices |
| CN101562151A (en) * | 2008-04-15 | 2009-10-21 | 和舰科技(苏州)有限公司 | Semiconductor structure with metal silicide and method for forming metal silicide |
-
2015
- 2015-06-03 CN CN201510299757.XA patent/CN106298767B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5403759A (en) * | 1992-10-02 | 1995-04-04 | Texas Instruments Incorporated | Method of making thin film transistor and a silicide local interconnect |
| US6063706A (en) * | 1998-01-28 | 2000-05-16 | Texas Instruments--Acer Incorporated | Method to simulataneously fabricate the self-aligned silicided devices and ESD protective devices |
| CN101562151A (en) * | 2008-04-15 | 2009-10-21 | 和舰科技(苏州)有限公司 | Semiconductor structure with metal silicide and method for forming metal silicide |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112563139A (en) * | 2020-11-17 | 2021-03-26 | 深圳宝铭微电子有限公司 | SGT manufacturing process of MOS (metal oxide semiconductor) tube |
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