CN106298736A - Semiconductor integrated circuit spiral inductance - Google Patents
Semiconductor integrated circuit spiral inductance Download PDFInfo
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- CN106298736A CN106298736A CN201610934537.4A CN201610934537A CN106298736A CN 106298736 A CN106298736 A CN 106298736A CN 201610934537 A CN201610934537 A CN 201610934537A CN 106298736 A CN106298736 A CN 106298736A
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- layer
- spiral
- dielectric layer
- integrated circuit
- semiconductor integrated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
Abstract
The present invention provides a kind of semiconductor integrated circuit spiral inductance, including substrate, multilayer dielectricity layer and metal wiring layer, wherein it is formed with multilayer dielectricity layer on substrate, and on every layer of dielectric layer, all it is formed with metal wiring layer, for every layer of dielectric layer, dielectric layer offers spiral helicine groove, tungsten metal it is filled with in groove, overlapped to form tungsten metal wall in tungsten metal wall, and each dielectric layer in the dielectric layer, metal wiring layer is for connecting the tungsten metal wall in each dielectric layer.The present invention has the dielectric layer of helical form tungsten metal wall by design multilamellar, and make the metal wiring layer between dielectric layer be interconnected by the tungsten metal wall in each dielectric layer, the thickness of Meander line inductor can be increased, such that it is able to the loss that the coil metal resistance loss of reduction spiral inductance and Kelvin effect cause, improve the quality factor of spiral inductance.
Description
Technical field
The invention belongs to semiconductor integrated circuit field, be specifically related to a kind of semiconductor integrated circuit spiral inductance.
Background technology
At existing semiconductor integrated circuit muti-layered metallic Wiring technology, such as SiGe BiCMOS, BiCMOS or CMOS technology
In, because radio frequency design and high integration need, it is often necessary to passive inductance on compatible integration slice, in order to improve this upper nothing
Source inductance performance, it is necessary to this inductance has relatively low-loss and higher inductance quality factor.But, existing commonly partly lead
In body integrated circuit, the quality factor of passive inductance is relatively low.
Summary of the invention
The present invention provides a kind of semiconductor integrated circuit spiral inductance, to solve current semiconductor integrated circuit spiral inductance
The problem that quality factor are poor.
First aspect according to embodiments of the present invention, it is provided that a kind of semiconductor integrated circuit spiral inductance, including substrate, many
Layer dielectric layer and metal wiring layer, wherein said substrate is formed on multilayer dielectricity layer, and every layer of dielectric layer and is all formed with gold
Belong to wiring layer, for every layer of dielectric layer, described dielectric layer offers spiral helicine groove, in described groove, be filled with tungsten gold
Belong to, in order in described dielectric layer, form tungsten metal wall in tungsten metal wall, and each dielectric layer overlapped, described metal line
Layer is for connecting the tungsten metal wall in each dielectric layer.
In the optional implementation of one, described substrate include polycrystalline laying and isolation deep trouth layer, wherein said every
On deep trouth layer, it is formed with described polycrystalline laying, and is formed with multilayer dielectricity layer on described polycrystalline laying.
In the optional implementation of another kind, when described isolation deep trouth use undope polysilicon fill time, described every
It is latticed from the flat shape isolating deep trouth described in deep trouth layer；When described isolation deep trouth uses heavily doped polysilicon to fill
Time, isolate described in described isolation deep trouth layer the flat shape of deep trouth be by the latticed of being not communicated with of forming of multiple independent segments or
Zhe You center is to extraradial strip.
In the optional implementation of another kind, the lead-in of described semiconductor integrated circuit spiral inductance is from top-level metallic
With the corresponding position, spiral outer end of described tungsten metal wall on wiring layer, vertically through each layer dielectric layer and metal wiring layer, draw
Enter to described polycrystalline laying.
In the optional implementation of another kind, the center lead-out wire of described semiconductor integrated circuit spiral inductance is from described
With the spiral center end corresponding position of described tungsten metal wall on polycrystalline laying, vertically through each layer dielectric layer and metal line
Layer, draws from top-level metallic wiring layer.
In the optional implementation of another kind, described center lead-out wire draw time its path below outermost layer dielectric layer
On tungsten metal wall be removed, and corresponding with tungsten metal wall on each layer metal wiring layer in addition to described top-level metallic wiring layer
In helical regions, all it is not attached between each spiral layers and spiral center lead-out wire.
In the optional implementation of another kind, helical form district corresponding with described tungsten metal wall on each floor metal wiring layer
In territory, at least two spiral layers interconnection between each spiral layers.
The invention has the beneficial effects as follows:
1, the present invention has the dielectric layer of helical form tungsten metal wall by design multilamellar, and makes the hardware cloth between dielectric layer
Tungsten metal wall in each dielectric layer is interconnected by line layer, can increase the thickness of Meander line inductor, such that it is able to reduce spiral
The loss that the coil metal resistance loss of inductance and Kelvin effect cause, improves the quality factor of spiral inductance；
2, the spiral inductance that the present invention is formed on isolation deep trouth layer by arranging isolation deep trouth layer effectively to block produces
Faradic current, reduce the loss of spiral inductance, and the spiral inductance of formation and each electricity in semiconductor integrated circuit can be made
The integrated technique on road is compatible；
3, the present invention is by when isolating deep trouth conductive capability and being stronger, is designed to be not communicated with by the flat shape of isolation deep trouth
Latticed or by center to extraradial strip, can the most effectively block the faradic current that spiral inductance produces, from
And reduce the loss of spiral inductance further；
4, by the present invention in that the lead-in of semiconductor integrated circuit spiral inductance from described top-level metallic wiring layer with
The corresponding position, spiral outer end of described tungsten metal wall, vertically through each layer dielectric layer and metal wiring layer, is introduced to described many
On brilliant laying, the introducing resistance of spiral inductance can be reduced；
5, by the present invention in that the center lead-out wire of this semiconductor integrated circuit spiral inductance connects up from described top-level metallic
On layer, the spiral center end corresponding position with described tungsten metal wall is drawn, and when center lead-out wire is drawn, and below its path
Outermost layer dielectric layer on tungsten metal wall when being removed, with tungsten gold on each layer metal wiring layer in addition to top-level metallic wiring layer
Belong in the helical regions that wall is corresponding, be all not attached between each spiral layers and spiral center lead-out wire, spiral shell can be reduced further
Inductance center lead-out wire and inductance coil short circuit is not resulted in while the coil resistance of rotation inductance；
6, by the present invention in that in helical regions corresponding with tungsten metal wall on each layer metal wiring layer, each spiral layers it
Between at least two spiral layers interconnection, i.e. make adjacent tungsten metal wall in parallel, adjacent tungsten metal wall carried out short circuit, can increase
The width of Meander line inductor, thus reduce the coil resistance of spiral inductance further, improve the quality factor of spiral inductance.
Accompanying drawing explanation
Fig. 1 is an embodiment sectional view of semiconductor integrated circuit spiral inductance of the present invention；
Fig. 2 is the right of an embodiment sectional view and the spiral tungsten metal wall of semiconductor integrated circuit spiral inductance of the present invention
Answer relational view；
Fig. 3 is the planar graph schematic diagram isolating deep trouth in semiconductor integrated circuit spiral inductance of the present invention；
Fig. 4 is another planar graph schematic diagram isolating deep trouth in semiconductor integrated circuit spiral inductance of the present invention；
Fig. 5 is another planar graph schematic diagram isolating deep trouth in semiconductor integrated circuit spiral inductance of the present invention；
Fig. 6 is another embodiment sectional view of semiconductor integrated circuit spiral inductance of the present invention；
Fig. 7 is another embodiment sectional view and the spiral tungsten metal wall of semiconductor integrated circuit spiral inductance of the present invention
Corresponding relation schematic diagram.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in the embodiment of the present invention, and make the present invention real
Execute the above-mentioned purpose of example, feature and advantage can become apparent from understandable, below in conjunction with the accompanying drawings to technical side in the embodiment of the present invention
Case is described in further detail.
In describing the invention, unless otherwise prescribed and limit, it should be noted that term " connects " should do broad sense manage
Solve, for example, it may be mechanically connected or electrical connection, it is also possible to be the connection of two element internals, can be to be joined directly together, it is possible to
To be indirectly connected to by intermediary, for the ordinary skill in the art, can understand as the case may be above-mentioned
The concrete meaning of term.
In the embodiment of the present invention, this semiconductor integrated circuit spiral inductance can include substrate, multilayer dielectricity layer and hardware cloth
Line layer, wherein said substrate is formed on multilayer dielectricity layer, and every layer of dielectric layer and is all formed with metal wiring layer, for every layer
Dielectric layer, described dielectric layer offers spiral helicine groove, is filled with tungsten metal in described groove, with at described dielectric layer
Middle formation tungsten metal wall, and in each dielectric layer, tungsten metal wall is overlapped, described metal wiring layer is used for connecting each medium
Tungsten metal wall in Ceng.
In the present embodiment, described substrate can include polycrystalline laying and isolation deep trouth layer, wherein said isolation deep trouth layer
On be formed with described polycrystalline laying, and be formed with multilayer dielectricity layer on described polycrystalline laying.Wherein, deep when described isolation
When groove uses the polysilicon that undopes to fill, the flat shape isolating deep trouth described in described isolation deep trouth layer is latticed；Work as institute
When stating isolation deep trouth employing heavily doped polysilicon filling, isolate the flat shape of deep trouth described in described isolation deep trouth layer for by many
Be not communicated with latticed of individual independent segment composition or by center to extraradial strip.
With the compatible 0.35 μm SiGe BiCMOS tungsten plug technique of semiconductor integrated circuit spiral inductance and have 4 layers of dielectric layer
With as a example by 4 layers of metal wiring layer, the present embodiment is described.It should be noted that 0.35 μm SiGe BiCMOS work mentioned below
Skill will be considered well-known about isolation deep trouth technique, polysilicon process, tungsten plug technique, multi-layer C MP metal line technique
Industry pass through mature technology, embodiment mainly illustrates that technical solution of the present invention is deep with existing 0.35 μm SiGe BiCMOS isolation
Technical scheme features different in groove technique, polysilicon process, tungsten plug technique, multi-layer C MP metal line technique.It should be understood that
The detailed description of the invention of the present invention is not limited only to generation type described below.Specifically, shown in Figure 1, partly lead being formed
Can comprise the following steps that during body integrated circuit spiral inductance:
1) be positioned on the place of substrate 8 in general 0.35 μm SiGe BiCMOS technique, with general compatible technology formed every
From deep trouth 6, thus form isolation deep trouth layer.The present invention can effectively block shape on isolation deep trouth layer by arranging isolation deep trouth layer
The faradic current that the spiral inductance become produces, reduces the loss of spiral inductance, and can make the spiral inductance of formation and partly lead
The integrated compatibility of each circuit in body integrated circuit.
Wherein, when the conductive capability of isolation deep trouth 6 is more weak, and such as isolation deep trouth 6 is filled by the polysilicon that undopes, or its
When will be formed with oxide layer or nitration case on sidewall, its flat shape can be the latticed, as shown in Figure 3 of connection.When
The conductive capability of isolation deep trouth 6 is relatively strong, when such as isolation deep trouth 6 is filled by heavily doped polysilicon, its flat shape can be by
Multiple independent segments composition latticed (as shown in Figure 4) that be not communicated with or by center to extraradial strip (as shown in Figure 5).
The present invention by when isolating deep trouth conductive capability and being stronger, be designed to be not communicated with by the flat shape of isolation deep trouth latticed or
Zhe You center, to extraradial strip, can the most effectively be blocked the faradic current that spiral inductance produces, thus drop further
The loss of low spiral inductance.In the present embodiment, the degree of depth of this isolation deep trouth can between 5 μm-9 μm value, width can be
Value between 0.6 μm-1 μm.
2) on isolation deep trouth layer, compatible use 0.35 μm SiGe BiCMOS technique forms polycrystalline laying 9.The present invention
By arranging polycrystalline laying, liner can be provided to the formation of subsequent dielectric layers and metal wiring layer, it is possible to meet and symbol
Close general 0.35 μm SiGe BiCMOS tungsten plug technique to need and requirement.
3) on polycrystalline laying 9, form the first medium layer 7 of compatible universal 0.35 μm SiGe BiCMOS technique.In shape
When becoming the tungsten metal wall 501 in first medium layer 7, make by lithography spiral helicine logical on dielectric layer initially with photoetching technique
Groove, then uses tungsten plug fill process to fill tungsten metal in this groove, and uses tungsten plug CMP planarization technique, to groove outside
Tungsten metal is polished removal and processes, thus forms tungsten metal wall 501 in first medium layer 7.Due to photoetching on dielectric layer
During groove, if design size is equal to tungsten plug contact through hole size in tungsten plug technique, then the size of the groove may being lithographically formed will
More than the size of tungsten plug contact hole, therefore the present invention is by when being designed groove, makes the design width of groove less than tungsten
The 10%～15% of plug contact hole design width, it is ensured that groove formed after developed width equal to the width of tungsten plug contact hole
Degree, thus ensure that groove is formed and the tungsten plug contact hole processing compatibility in circuit.In the present embodiment, the width of groove can take
0.36 μm, and the spiral-shaped circle being not limited only to shown in Fig. 2 of this tungsten metal wall, it is also possible to be square, octagon,
Hexagon, irregular convex polygon, even triangle.
4) in first medium layer, the first metal wiring layer 1 on tungsten metal wall 501, is formed.The present invention is by dielectric layer
Formed and cover metal wiring layer on tungsten metal wall, tungsten metal wall can be played in protective dielectric layer and connect next layer and be situated between
The effect of tungsten metal wall in matter layer.
5) repeated execution of steps 3) and 4), the first metal wiring layer 1 forms second dielectric layer, in second dielectric layer
Form second layer tungsten metal wall 502, second dielectric layer forms the second metal wiring layer 2, shape on the second metal wiring layer 2
Become the 3rd dielectric layer, the 3rd dielectric layer is formed third layer tungsten metal wall 503, the 3rd dielectric layer is formed the 3rd hardware cloth
Line layer 3, forms the 4th dielectric layer on the 3rd metal wiring layer 3, forms the 4th layer of tungsten metal wall 504 in the 4th dielectric layer,
4th dielectric layer is formed the 4th metal wiring layer 4.
In above-described embodiment, the lead-in of this semiconductor integrated circuit spiral inductance can from top-level metallic wiring layer with
The corresponding position, spiral outer end of tungsten metal wall, vertically through each layer dielectric layer and metal wiring layer, is introduced to described polycrystalline lining
On bed course, thus can reduce the introducing resistance of spiral inductance.See Fig. 2, the introducing of this semiconductor integrated circuit spiral inductance
Line can from the 4th metal wiring layer 4 with the corresponding position, spiral outer end of tungsten metal wall 501～504, successively vertically through
4th layer of tungsten metal wall the 504, the 3rd metal wiring layer 3, third layer tungsten metal wall the 503, second metal wiring layer 2, second layer tungsten
Metal wall the 502, first metal wiring layer 1 and ground floor tungsten metal wall 501, be introduced to polycrystalline laying 9.
It addition, the center lead-out wire of this semiconductor integrated circuit spiral inductance can from polycrystalline laying 9 with described tungsten
The spiral center end corresponding position of metal wall, vertically through each layer dielectric layer and metal wiring layer, from top-level metallic wiring layer
Drawing, when center lead-out wire is drawn, the tungsten metal wall on outermost layer dielectric layer below its path is removed, and except top layer is golden
In helical regions corresponding with tungsten metal wall on each layer metal wiring layer outside genus wiring layer, each spiral layers and center lead-out wire
Between be all not attached to, do not result in inductance center lead-out wire while thus can reducing the coil resistance of spiral inductance further
With coil short.Seeing Fig. 2, the center lead-out wire of this semiconductor integrated circuit spiral inductance can be from the 4th metal wiring layer 4
The upper spiral center end corresponding position with tungsten metal wall 504 is drawn, the 4th being situated between below its path when center lead-out wire is drawn
The tungsten metal wall of matter layer is removed, and not with the 3rd metal wiring layer the 3, second metal wiring layer 2 and the first metal wiring layer 1
On, each spiral layers in the helical regions corresponding with tungsten metal wall is connected.Wherein, the present embodiment is by each the first metal line
Layer is designed to 0.4 μm to the thickness of the 3rd metal wiring layer, and the thickness of the 4th metal wiring layer is designed as 0.8 μm, and each is situated between
In matter layer, tungsten metal wall 5 is highly designed to 1 μm, then Meander line inductor maximum aggregate thickness 3 × 0.4 μm+0.8 μm+4 × 1 μm
=6 μm.It is to be noted that being positioned on the downside of top-level metallic wiring layer spiral outer end for removing in outermost layer dielectric layer shown in Fig. 2
Tungsten metal outside, the situation that other tungsten metals are all removed, shown in Fig. 6 for only top-level metallic wiring layer in outermost layer dielectric layer
The situation that tungsten metal below centre of surface lead-out wire is removed.
As seen from the above-described embodiment, the present invention has the dielectric layer of helical form tungsten metal wall by design multilamellar, and makes Jie
Tungsten metal wall in each dielectric layer is interconnected by the metal wiring layer between matter layer, can increase the thickness of Meander line inductor,
Such that it is able to the loss that the coil metal resistance loss of reduction spiral inductance and Kelvin effect cause, improve the quality of spiral inductance
Factor.
In above-described embodiment, although the coil metal resistance loss of spiral inductance and the skin that becomes can be reduced by increasing thickness
The loss that effect causes, improves the quality factor of spiral inductance, but is affected by general 0.35 μm SiGe BiCMOS technique tungsten plug
The impact of gas phase CVD fill process, the width of tungsten plug and tungsten metal wall is to have for general tungsten plug muti-layered metallic Wiring technology
Limiting, this width that may result in Meander line inductor is the least, thus constrain spiral inductance quality factor enter one
Step improves.To this end, see Fig. 7, for another embodiment sectional view of semiconductor integrated circuit spiral inductance of the present invention, itself and figure
The difference of semiconductor integrated circuit spiral inductance shown in 2 is, when making each layer metal wiring layer, and not only top-level metallic wiring
In helical regions corresponding with tungsten metal wall on layer, between each spiral layers, there is interconnection, and on each layer metal wiring layer
In the helical regions corresponding with tungsten metal wall, at least two spiral layers interconnection between each spiral layers, and each layer metal line
On layer, the interconnection between spiral layers is corresponding, thus can realize adjacent tungsten metal wall and be shorted, and makes adjacent tungsten metal wall in parallel,
Such that it is able to reduce the coil resistance of spiral inductance, as shown in Fig. 7 11.Such as, shown in Fig. 2 and Fig. 7, in Fig. 6 the 3rd
With spiral corresponding to tungsten metal wall 503,502,501 on metal wiring layer the 3, second metal wiring layer the 2, first metal wiring layer 1
In shape region, ground floor spiral layers from inside to outside is connected with second layer spiral layers, third layer spiral layers and the 4th helical layer layer
Connect, thus form the interconnection two-by-two of spiral layers.Certainly, although although it is not shown, same mode can be with shape in Fig. 7
Become the interconnection of more spiral layers to reduce the coil resistance of every helical layer layer further.
As seen from the above-described embodiment, the present invention has the dielectric layer of helical form tungsten metal wall by design multilamellar, and makes Jie
Tungsten metal wall in each dielectric layer is interconnected by the metal wiring layer between matter layer, can increase the thickness of Meander line inductor,
Such that it is able to the loss that the coil metal resistance loss of reduction spiral inductance and Kelvin effect cause, improve the quality of spiral inductance
Factor.Additionally, by the present invention in that the helical form that top-level metallic wiring layer is corresponding with tungsten metal wall with on each layer metal wiring layer
In region, between each spiral layers, at least two spiral layers interconnection, even if adjacent tungsten metal wall is in parallel, enter adjacent tungsten metal wall
Row short circuit, can increase the width of Meander line inductor, thus reduce the coil resistance of spiral inductance further, improves spiral electricity
The quality factor of sense.
Those skilled in the art, after considering description and putting into practice invention disclosed herein, will readily occur to its of the present invention
Its embodiment.The application is intended to any modification, purposes or the adaptations of the present invention, these modification, purposes or
Person's adaptations is followed the general principle of the present invention and includes the undocumented common knowledge in the art of the present invention
Or conventional techniques means.Description and embodiments is considered only as exemplary, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be appreciated that the invention is not limited in precision architecture described above and illustrated in the accompanying drawings, and
And various modifications and changes can carried out without departing from the scope.The scope of the present invention is only limited by appended claim.
Claims (7)
1. a semiconductor integrated circuit spiral inductance, it is characterised in that include substrate, multilayer dielectricity layer and metal wiring layer,
It is formed on wherein said substrate on multilayer dielectricity layer, and every layer of dielectric layer and is all formed with metal wiring layer, for every layer of medium
Layer, described dielectric layer offers spiral helicine groove, is filled with tungsten metal in described groove, with shape in described dielectric layer
Becoming tungsten metal wall in tungsten metal wall, and each dielectric layer overlapped, described metal wiring layer is used for connecting in each dielectric layer
Tungsten metal wall.
Semiconductor integrated circuit spiral inductance the most according to claim 1, it is characterised in that described substrate includes that polycrystalline serves as a contrast
Bed course and isolation deep trouth layer, wherein said isolation deep trouth layer is formed described polycrystalline laying, and at described polycrystalline laying
On be formed with multilayer dielectricity layer.
Semiconductor integrated circuit spiral inductance the most according to claim 2, it is characterised in that when described isolation deep trouth uses
When the polysilicon that undopes is filled, the flat shape isolating deep trouth described in described isolation deep trouth layer is latticed；When described isolation
When deep trouth uses heavily doped polysilicon to fill, isolate the flat shape of deep trouth described in described isolation deep trouth layer for by multiple independences
Be not communicated with latticed of Duan Zucheng or by center to extraradial strip.
Semiconductor integrated circuit spiral inductance the most according to claim 2, it is characterised in that described semiconductor integrated circuit
The lead-in of spiral inductance from top-level metallic wiring layer with the corresponding position, spiral outer end of described tungsten metal wall, vertically through
Each layer dielectric layer and metal wiring layer, be introduced on described polycrystalline laying.
Semiconductor integrated circuit spiral inductance the most according to claim 2, it is characterised in that described semiconductor integrated circuit
The center lead-out wire of spiral inductance from described polycrystalline laying with the spiral center end corresponding position of described tungsten metal wall, perpendicular
Straight through each layer dielectric layer and metal wiring layer, draw from top-level metallic wiring layer.
Semiconductor integrated circuit spiral inductance the most according to claim 5, it is characterised in that described center lead-out wire is drawn
Time its path below outermost layer dielectric layer in tungsten metal wall be removed, and in addition to described top-level metallic wiring layer each layer gold
In helical regions corresponding with tungsten metal wall on genus wiring layer, all it is not attached between each spiral layers and described center lead-out wire.
Semiconductor integrated circuit spiral inductance the most according to claim 1, it is characterised in that on each layer metal wiring layer with
In the helical regions that described tungsten metal wall is corresponding, at least two spiral layers interconnection between each spiral layers.
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| WO2023075846A1 (en) * | 2021-10-27 | 2023-05-04 | Microchip Technology Incorporated | Integrated inductor with inductor wire formed in an integrated circuit layer stack |
| WO2023075847A1 (en) * | 2021-10-27 | 2023-05-04 | Microchip Technology Incorporated | Integrated inductor including multi-component via layer inductor element |
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| US20010045616A1 (en) * | 1998-06-29 | 2001-11-29 | Takashi Yoshitomi | Semiconductor device having an inductor and method for manufacturing the same |
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| US7067882B2 (en) * | 2003-08-28 | 2006-06-27 | Lsi Logic Corporation | High quality factor spiral inductor that utilizes active negative capacitance |
| CN101335289A (en) * | 2007-06-26 | 2008-12-31 | 联发科技股份有限公司 | Integrated inductor |
| US20090243034A1 (en) * | 2006-07-21 | 2009-10-01 | X-Fab Semiconductor Foundries Ag | Semiconductor device |
| CN101645445A (en) * | 2009-06-24 | 2010-02-10 | 上海宏力半导体制造有限公司 | Integrated inductor |
| CN101996861A (en) * | 2009-08-17 | 2011-03-30 | 上海宏力半导体制造有限公司 | Inductor and forming method thereof |
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2016
- 2016-10-31 CN CN201610934537.4A patent/CN106298736B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010045616A1 (en) * | 1998-06-29 | 2001-11-29 | Takashi Yoshitomi | Semiconductor device having an inductor and method for manufacturing the same |
| US20020086585A1 (en) * | 2000-12-05 | 2002-07-04 | Benoit Butaye | Insulation device of an electric element |
| US7067882B2 (en) * | 2003-08-28 | 2006-06-27 | Lsi Logic Corporation | High quality factor spiral inductor that utilizes active negative capacitance |
| TW200611283A (en) * | 2004-09-24 | 2006-04-01 | Taiwan Semiconductor Mfg Co Ltd | Inductor energy loss reduction techniques |
| US20090243034A1 (en) * | 2006-07-21 | 2009-10-01 | X-Fab Semiconductor Foundries Ag | Semiconductor device |
| CN101335289A (en) * | 2007-06-26 | 2008-12-31 | 联发科技股份有限公司 | Integrated inductor |
| CN101645445A (en) * | 2009-06-24 | 2010-02-10 | 上海宏力半导体制造有限公司 | Integrated inductor |
| CN101996861A (en) * | 2009-08-17 | 2011-03-30 | 上海宏力半导体制造有限公司 | Inductor and forming method thereof |
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