CN106298635A - The manufacture method of semiconductor device - Google Patents
The manufacture method of semiconductor device Download PDFInfo
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- CN106298635A CN106298635A CN201510264656.9A CN201510264656A CN106298635A CN 106298635 A CN106298635 A CN 106298635A CN 201510264656 A CN201510264656 A CN 201510264656A CN 106298635 A CN106298635 A CN 106298635A
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- semiconductor device
- groove structure
- insulating barrier
- manufacture method
- groove
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 230000004888 barrier function Effects 0.000 claims abstract description 66
- 238000005530 etching Methods 0.000 claims abstract description 47
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 230000006698 induction Effects 0.000 claims description 11
- 230000001939 inductive effect Effects 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 5
- 230000000717 retained effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 46
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000007792 gaseous phase Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000012861 aquazol Substances 0.000 description 1
- 229920006187 aquazol Polymers 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
In the manufacture method of the semiconductor device of present invention offer, the load effect utilizing etching retains the partial insulative layer bottom the first groove structure, bottom can be realized by a photoetching and etching and remain with the first groove structure and second groove structure of bottom naked layer of insulating barrier, thus simplify processing step, reduce manufacturing cost.
Description
Technical field
The present invention relates to IC manufacturing field, particularly to the manufacture method of a kind of semiconductor device.
Background technology
The manufacture process of integrated circuit generally includes front procedure (FEOL) and rear road processing procedure (BEOL),
Front procedure and rear road processing procedure are usually using contact hole (contact) technique as boundary, contact hole technique it
Front is front procedure, and (comprising contact hole technique) after contact hole technique is rear road processing procedure.Etching groove
One of committed step of (trench etch) Shi Hou road processing procedure, for forming the groove of metal interconnection.Due to gold
Belong to the interlayer film arranged between layer and be typically silicon nitride layer, therefore need silicon nitride layer during etching groove
Perform etching, expose silicon nitride layer metal layer below by etching.
At present, some semiconductor device needs member-retaining portion silicon nitride layer after etching groove.Incorporated by reference to ginseng
Examining Fig. 1 to Fig. 6, it is the structural representation of manufacture process of semiconductor device of prior art.Such as Fig. 1 extremely
Shown in Fig. 6, the manufacture method of existing semiconductor device includes:
Step one: as shown in Figure 1, it is provided that semi-conductive substrate 110；
Step 2: as in figure 2 it is shown, first insulating barrier 120, first successively in described Semiconductor substrate 110
Metal level the 130, second insulating barrier the 140, second metal level 150 and the 3rd insulating barrier 160, wherein, institute
The edge at the edge and described the first metal layer 130 of stating the second insulating barrier 140 flushes, described 3rd insulating barrier
The edge of 160 flushes with the edge of described second metal level 150, described the first metal layer 130 and the second metal
Layer 150 is typically each made up of aluminum (AL), described first insulating barrier the 120, second insulating barrier 140 and the 3rd
Insulating barrier 160 is typically each made up of silicon nitride (SiN)；
Step 3: as it is shown on figure 3, in described first insulating barrier the 120, second insulating barrier the 140, the 3rd insulation
Plasma enhanced oxidation film (Plasma Enhanced is formed on layer 160 and Semiconductor substrate 110
Oxide, is called for short PEOX) 170；
Step 4: form patterned on described plasma enhanced oxidation film 170 by photoetching process
One photoresist layer (not shown)；
Step 5: as shown in Figure 4, with described patterned first photoresist layer as mask, by carving for the first time
Described plasma enhanced oxidation film 170 is performed etching by etching technique, with at described plasma enhanced oxidation
Film 170 is formed the first opening 171 and the second opening 172, described first opening 171 and the second opening 172
Opening size same or like, the bottom-exposed of described first opening 171 goes out the first insulating barrier 120, described
The bottom-exposed of the second opening 172 goes out the second insulating barrier 140 and the 3rd insulating barrier 160；
Step 5: as it is shown in figure 5, after removing the first photoresist layer, expose at described first opening 171
The first insulating barrier 120 and plasma enhanced oxidation film 170 on form patterned second photoresist layer 180；
Step 6: as shown in Figure 6, carries out second time with described patterned second photoresist layer 180 for mask
Etching technics, to remove the second insulating barrier 140 and the 3rd insulating barrier 160 in described second opening 172.
Step 7: as it is shown in fig. 7, remove the second photoresist layer 180, so far form semiconductor device 100.
Incorporated by reference to reference to Fig. 4 and Fig. 7, described semiconductor device 100 includes induction region (dashed circle in figure
Shown region) and non-inductive region, described first opening 171 is positioned at described induction region, and described second opens
Mouthfuls 172 are positioned at non-inductive region, described semiconductor device 100 after etching groove, non-inductive region
Groove structure completely eliminated (in the i.e. second opening 172) silicon nitride, and the groove structure of induction region
In (in the i.e. first opening 171) remain silicon nitride.
Above-mentioned manufacture method includes Twi-lithography and etching, i.e. for the first time light blockage coating---exposure for the first time---the
---photoresistance peels off the exposure of---light blockage coating for the second time---second time to once etching (i.e. top layer via etch) for the first time
Peel off for the second time by photoresistance for light---second time etching (i.e. silicon nitride etch)---.Visible, existing manufacture method
Not only need to be used for multiple times photoresist, and need through Twi-lithography and etching, complex process and also become
This is higher.
Summary of the invention
It is an object of the invention to provide the manufacture method of a kind of semiconductor device, to solve ditch in prior art
Manufacturing process complexity and the manufacturing cost of the semiconductor device of member-retaining portion silicon nitride layer is needed after groove etched
High problem.
For solving above-mentioned technical problem, the present invention provides the manufacture method of a kind of semiconductor device, described partly leads
The manufacture method of body device includes:
Semi-conductive substrate is provided；
Sequentially form on the semiconductor substrate the first insulating barrier, the first metal layer, the second insulating barrier,
Two metal levels and the 3rd insulating barrier；
Described first insulating barrier, the second insulating barrier and the 3rd insulating barrier are formed plasma enhanced oxidation film；
On described plasma enhanced oxidation film, patterned photoresist layer, described light is formed by photoetching process
The mask that carving technology uses is provided with the first groove structure and the second groove structure, described first groove knot
The opening size of structure is at more than 15 times of opening size of described second groove structure；And
Etching groove is carried out for mask, to form the first groove structure and second with described patterned photoresist layer
Groove structure.
Optionally, in the manufacture method of described semiconductor device, the bottom of described first groove structure is protected
Leaving the first insulating barrier, the bottom-exposed of described second groove structure goes out described the first metal layer or the second metal
Layer.
Optionally, in the manufacture method of described semiconductor device, described semiconductor device includes induction zone
Territory and non-inductive region, described first groove structure is positioned at the induction region of described semiconductor device, and described
Two groove structures are positioned at the non-inductive region of described semiconductor device.
Optionally, in the manufacture method of described semiconductor device, the bottom institute of described first groove structure
The thickness of the first insulating barrier retained is between 1000 angstroms to 2000 angstroms.
Optionally, in the manufacture method of described semiconductor device, the open-mouth ruler of described second groove structure
Very little between 1 micron to 5 micron.
Optionally, in the manufacture method of described semiconductor device, the technological parameter of described etching groove is:
Upper electrode power is between 1350W to 1650W；Lower electrode power is between 1500W to 1900W；Pressure
Between 25Mt to 35Mt；Reacting gas is C5F8、O2And Ar, wherein, C5F8And O2Flow all exist
Between 14sccm to 18sccm, the flow of Ar is between 600sccm to 1000sccm.
Optionally, in the manufacture method of described semiconductor device, also include: remove described patterned
Photoresist layer.
Optionally, in the manufacture method of described semiconductor device, described first insulating barrier, the second insulation
Layer and the 3rd insulating barrier are made by silicon nitride.
Optionally, in the manufacture method of described semiconductor device, described the first metal layer and the second metal
Layer is each made of aluminum.
Optionally, in the manufacture method of described semiconductor device, described semiconductor device is silicon substrate.
In the manufacture method of the semiconductor device of present invention offer, the load effect of etching is utilized to retain first
Partial insulative layer bottom groove structure, can realize bottom by a photoetching and etching and remain with insulating barrier
The first groove structure and the second groove structure of bottom naked layer, thus simplify processing step, reduce
Manufacturing cost.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is the structural representation of the manufacture process of the semiconductor device of prior art；
Fig. 8 is the schematic flow sheet of the manufacture process of the semiconductor device of the embodiment of the present invention；
Fig. 9 to Figure 13 is the structural representation of the manufacture process of the semiconductor device of the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the manufacture method of the semiconductor device that the present invention proposes is made into one
Step describes in detail.According to following explanation and claims, advantages and features of the invention will be apparent from.Need
Illustrating, accompanying drawing all uses the form simplified very much and all uses non-ratio accurately, only in order to convenient,
Aid in illustrating the purpose of the embodiment of the present invention lucidly.
Refer to Fig. 8, it is the schematic flow sheet of manufacture process of semiconductor device of the embodiment of the present invention.As
Shown in Fig. 8, the manufacture method of described semiconductor device comprises the steps:
Step one: semi-conductive substrate is provided；
Step 2: be sequentially laminated with the first insulating barrier, the first metal layer, second exhausted in described Semiconductor substrate
Edge layer, the second metal level and the 3rd insulating barrier；
Step 3: form plasma on described first insulating barrier, the second insulating barrier and the 3rd insulating barrier and increase
Strong oxdiative film；
Step 4: form patterned photoresistance on described plasma enhanced oxidation film by photoetching process
Layer, is provided with the first groove structure and the second groove structure in the mask that described photoetching process uses, described
The opening size of the first groove structure is at more than 15 times of opening size of described second groove structure；
Step 5: carry out etching groove for mask with described patterned photoresist layer, to form the first groove knot
Structure and the second groove structure.
Below in conjunction with specific embodiments and the drawings 9 to 13, the present invention will be described in detail.
First, as shown in Figure 9, it is provided that semi-conductive substrate 210, described Semiconductor substrate 210 can be silicon
Substrate, germanium silicon substrate, III-group Ⅴ element compound substrate or well known to a person skilled in the art other quasiconductors
Material substrate, uses silicon substrate in the present embodiment.
Then, as shown in Figure 10, described Semiconductor substrate 210 sequentially forms the first insulating barrier 220,
The first metal layer the 230, second insulating barrier the 240, second metal level 250 and and the 3rd insulating barrier 260, institute
The edge at the edge and described the first metal layer 230 of stating the second insulating barrier 240 flushes, described 3rd insulating barrier
The edge of 260 flushes with the edge of described second metal level 250.
Wherein, described the first metal layer 230 and the second metal level 250 all can be by any suitable metal materials
Constituted, including Cu, Ni, Pt, Al or its combination in any, and formed by any suitable technology,
Such as physical vapour deposition (PVD) (PVD), chemical gaseous phase deposition (CVD), electrochemical deposition (electrochemical
Deposition, is called for short ECD), molecular beam epitaxy (molecular beam epitaxy, be called for short MBE), atom
Layer deposition (atomic layer deposition is called for short ALD), plating (electroplating) etc..The present embodiment
In, described the first metal layer 230 and the second metal level 250 are made by aluminum (AL).
Wherein, described first insulating barrier the 220, second insulating barrier 240 and the 3rd insulating barrier 260 can be by any suitable
When insulant constituted, including SiN, SiON, SiO2 or its combination in any, and by any suitably
Technology and formed, such as chemical gaseous phase deposition (CVD) etc..In the present embodiment, described first insulation
Layer the 220, second insulating barrier 240 and the 3rd insulating barrier 260 are made by silicon nitride (SiN).
Then, as shown in figure 11, by chemical gaseous phase deposition (CVD) technique in described Semiconductor substrate 210
Upper formation plasma enhanced oxidation film 270, described plasma enhanced oxidation film 270 is completely covered described half
Conductor substrate 210.Form chemical gaseous phase deposition (CVD) technique of described plasma enhanced oxidation film 270
Process conditions be: power is between 900W to 1300W；Pressure is between 2.1Torr to 2.7Torr；Instead
Answering gas is SiH4And N2O, wherein, SiH4Flow between 250sccm to 350sccm, N2The stream of O
Amount is between 9000sccm to 10000sccm；Process time is between 4min to 8min.
Then, on described plasma enhanced oxidation film 270, patterned photoresistance is formed by photoetching process
Layer, is provided with the first groove structure and the second groove structure in the domain of the mask that described photoetching process uses,
The opening size of described first groove structure require 15 times of opening size of described second groove structure with
On.
As shown in figure 12, after lithography, groove quarter is carried out with described patterned photoresist layer 280 for mask
Erosion, to form the first groove structure 271 and the second groove structure 272.Described etching groove process includes institute
State plasma enhanced oxidation film 270 perform etching and to described plasma enhanced oxidation film 270 below
First insulating barrier the 220, second insulating barrier 240 and the 3rd insulating barrier 260 perform etching, described plasma
Strengthen the etching of oxide-film 270 and described first insulating barrier the 220, second insulating barrier 240 and the 3rd insulating barrier
The etching of 260 completes in same etching technics.
Wherein, the technological parameter of described etching groove is: upper electrode power is between 1350W to 1650W；
Lower electrode power is between 1500W to 1900W；Pressure is between 25Mt to 35Mt；Reacting gas is C5F8、
Oxygen (O2) and argon (Ar), wherein, C5F8Flow between 14sccm to 18sccm, O2Stream
Amount is between 14sccm to 18sccm, and the flow of Ar is between 600sccm to 1000sccm.
Finally, described patterned photoresist layer 280 is removed by stripping technology.As shown in figure 13, groove is carved
After erosion, described semiconductor device defines the first groove structure 271 and the second groove structure 272, described
The opening size CD1 of the first groove structure 271 is at the opening size CD2 of described second groove structure 272
More than 15 times, the bottom of described first groove structure 271 does not exposes described Semiconductor substrate 210, described
The bottom-exposed of the second groove structure 272 goes out described the first metal layer 230 and the second metal level 250.
In etching process, due to opening size CD1 and described second ditch of described first groove structure 271
The opening size CD2 difference of groove structure 272 is very big (more than 15 times), occurs in that the load effect of etching
(loading effect) so that the etching depth of described first groove structure 271 and described second groove structure
The etching depth of 272 is inconsistent, and the etching depth of described first groove structure 271 is than described second groove knot
The etching depth of structure 272 is shallow.As shown in figure 13, at the end of etching in described second groove structure 272
Two insulating barriers 240 and the 3rd insulating barrier 260 are all removed, and in described first groove structure 271
One insulating barrier 220 is retained due to the load effect of etching, and the bottom of described first groove structure 271 is still
So remain certain thickness first insulating barrier 220.
The load effect of etching refers to large scale etch areas in etching technics (such as the first groove structure 271)
Etch-rate is slower than the etch-rate of small size etch areas (such as the second groove structure 272), i.e. etched
The phenomenon that amount (i.e. opening size) increase of material that is etched in journey can cause etching speed to slow down.Groove is carved
During erosion, the size of opening size has a great impact for etch rate, and the difference of opening size is the biggest,
The difference of etch rate is the most prominent.
In the present embodiment, described semiconductor device application agitator in RF radio circuit or wave filter, institute
Stating semiconductor device and include induction region and non-inductive region, wherein, described first groove structure 271 is positioned at
The induction region of described semiconductor device, described second groove structure 272 is positioned at the non-of described semiconductor device
Induction region.As shown in figure 13, after etching groove completes, described first groove structure 271 is positioned at described
The induction region (region shown in dashed circle in figure) of semiconductor device, described second groove structure 272 is positioned at
The non-inductive region of described semiconductor device.
Preferably, the opening size CD1 of described second groove structure 272 is micro-to 51 micron (μm)
Between rice (μm).Accordingly, if the opening size CD1 of described second groove structure 272 is 1 micron,
The opening size CD2 of the most described first groove structure 271 is more than 15 microns (μm)；If described second
The opening size CD1 of groove structure 272 is 5 microns, the opening size of the most described first groove structure 271
CD2 is more than 75 microns (μm).
Preferably, the thickness of the first insulating barrier 220 retained in described first groove structure 271 is at 1000 angstroms
Between 2000 angstroms, such as, the thickness of the first insulating barrier 220 retained in described first groove structure 271
It it is 1500 angstroms.
In the manufacture method of the semiconductor device of the present embodiment offer, etching groove process only includes once light
Carve and etching, i.e. light blockage coating---exposure---etching---photoresistance stripping.And the manufacture of traditional semiconductor device
Process includes Twi-lithography and etching, and light blockage coating is---the most exposed and developed---i.e. for the first time carves for the first time
------light blockage coating for the second time is---the most exposed and developed---in photoresistance stripping for the first time in erosion (top layer via etch)
Second time etching (silicon nitride etch)---photoresistance is peeled off for the second time.
As can be seen here, the manufacture method using described semiconductor device can reduce light blockage coating, once
Exposed and developed, once etching and photoresistance peel off, be not only able to Simplified flowsheet step, improve production capacity and
Yield, and the usage amount of photoresistance can be saved, reduce manufacturing cost.
To sum up, in the manufacture method of the semiconductor device of embodiment of the present invention offer, the load of etching is utilized
Effect retains the partial insulative layer bottom the first groove structure, can realize bottom by a photoetching and etching
Remain with the first groove structure and second groove structure of bottom naked layer of insulating barrier, thus simplify work
Skill step, reduces manufacturing cost.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention,
Any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification, belong to power
The protection domain of profit claim.
Claims (10)
1. the manufacture method of a semiconductor device, it is characterised in that including:
Semi-conductive substrate is provided；
Sequentially form on the semiconductor substrate the first insulating barrier, the first metal layer, the second insulating barrier,
Two metal levels and the 3rd insulating barrier；
Described first insulating barrier, the second insulating barrier and the 3rd insulating barrier are formed plasma enhanced oxidation film；
On described plasma enhanced oxidation film, patterned photoresist layer, described light is formed by photoetching process
The mask that carving technology uses is provided with the first groove structure and the second groove structure, described first groove knot
The opening size of structure is at more than 15 times of opening size of described second groove structure；And
Etching groove is carried out for mask, to form the first groove structure and second with described patterned photoresist layer
Groove structure.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described first ditch
The bottom of groove structure remains with the first insulating barrier, and the bottom-exposed of described second groove structure goes out described first gold medal
Belong to layer or the second metal level.
3. the manufacture method of semiconductor device as claimed in claim 1 or 2, it is characterised in that described half
Conductor device includes that induction region and non-inductive region, described first groove structure are positioned at described semiconductor device
Induction region, described second groove structure is positioned at the non-inductive region of described semiconductor device.
4. the manufacture method of semiconductor device as claimed in claim 3, it is characterised in that described first ditch
The thickness of the first insulating barrier that the bottom of groove structure is retained is between 1000 angstroms to 2000 angstroms.
5. the manufacture method of semiconductor device as claimed in claim 3, it is characterised in that described second ditch
The opening size of groove structure is between 1 micron to 5 micron.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described groove is carved
The technological parameter of erosion is: upper electrode power is between 1350W to 1650W；Lower electrode power arrives at 1500W
Between 1900W；Pressure is between 25Mt to 35Mt；Reacting gas is C5F8、O2And Ar, wherein, C5F8
And O2Flow all between 14sccm to 18sccm, the flow of Ar is between 600sccm to 1000sccm.
7. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that also include: go
Except described patterned photoresist layer.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described first exhausted
Edge layer, the second insulating barrier and the 3rd insulating barrier are made by silicon nitride.
9. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described first gold medal
Belong to layer and the second metal level is each made of aluminum.
10. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described partly lead
Body device is silicon substrate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134456A (en) * | 2017-05-10 | 2017-09-05 | 上海格易电子有限公司 | A kind of semiconductor storage unit and preparation method thereof |
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|---|---|---|---|---|
| US20050116276A1 (en) * | 2003-11-28 | 2005-06-02 | Jing-Horng Gau | Metal-insulator-metal (MIM) capacitor and fabrication method for making the same |
| KR100641536B1 (en) * | 2004-12-15 | 2006-11-01 | 동부일렉트로닉스 주식회사 | method of fabricating the MIM capacitor having high capacitance |
| US20140199815A1 (en) * | 2013-01-17 | 2014-07-17 | Sung-Min Hwang | Methods of manufacturing a semiconductor device |
| CN104392897A (en) * | 2014-04-30 | 2015-03-04 | 上海华力微电子有限公司 | Production method of MIM capacitor |
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2015
- 2015-05-21 CN CN201510264656.9A patent/CN106298635B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050116276A1 (en) * | 2003-11-28 | 2005-06-02 | Jing-Horng Gau | Metal-insulator-metal (MIM) capacitor and fabrication method for making the same |
| KR100641536B1 (en) * | 2004-12-15 | 2006-11-01 | 동부일렉트로닉스 주식회사 | method of fabricating the MIM capacitor having high capacitance |
| US20140199815A1 (en) * | 2013-01-17 | 2014-07-17 | Sung-Min Hwang | Methods of manufacturing a semiconductor device |
| CN104392897A (en) * | 2014-04-30 | 2015-03-04 | 上海华力微电子有限公司 | Production method of MIM capacitor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134456A (en) * | 2017-05-10 | 2017-09-05 | 上海格易电子有限公司 | A kind of semiconductor storage unit and preparation method thereof |
| CN107134456B (en) * | 2017-05-10 | 2019-11-26 | 上海格易电子有限公司 | A kind of semiconductor storage unit and preparation method thereof |
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| CN106298635B (en) | 2019-11-01 |
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