CN106298631A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN106298631A
CN106298631A CN201510237821.1A CN201510237821A CN106298631A CN 106298631 A CN106298631 A CN 106298631A CN 201510237821 A CN201510237821 A CN 201510237821A CN 106298631 A CN106298631 A CN 106298631A
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Prior art keywords
metal
dielectric layer
intermetallic dielectric
cutting road
layer
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CN201510237821.1A
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CN106298631B (zh
Inventor
徐健斌
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201510237821.1A priority Critical patent/CN106298631B/zh
Priority to US14/789,994 priority patent/US9536831B2/en
Publication of CN106298631A publication Critical patent/CN106298631A/zh
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Abstract

本发明公开一种半导体元件及其制作方法，该半导体元件包含一基底，一管芯区以及一切割道区定义于基底上，以及一接触垫设于基底上的管芯区并重叠切割道区。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件，尤其是涉及一种重叠管芯区与切割道区的接触垫结构。
背景技术
由于半导体制作工艺技术的持续进步，使得大量的电路元件可以被制作在单一芯片上，再加上市场上对于复杂度高以及运用功能强的各种电子商品的需求，使得单一芯片的整个电路统整可包括微处理器、存储器、周边及芯片汇流排等功能，以达到低功率、高效能、小体积以及高可靠度等诸多优点。
而随着集成电路在制作工艺上的不断进步，芯片设计的复杂度也跟着提升，造成对产品上市时间的需求更不易满足。系统单芯片(System-on-a-chip,SoC)是整合包含运算功能(如微处理器核心、数字信号处理核心、MPEG核心或绘图核心)，以及存储器、逻辑/类比电路、混合信号电路或RF电路于一个单一芯片上，供作特定用途的集成电路IC。系统单芯片提供了集成电路IC的高度整合，大幅简化系统设计，减少制造成本，并可以缩短产品上市的时间。
在系统单芯片的设计中，芯片与基板间的高度差于后续打线制作工艺中扮演着一关键角色。一般而言，芯片完成后通常会进行另一道步骤将芯片中的线路通过重布线(re-distribution layer,RDL)制作工艺延伸至基板的较低表面来进行后续打线制作工艺。此制作方式不但增加制作工艺的困难度与时间更耗费成本。因此如何提供一种更简化的设计来改善现有架构即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例揭露一种制作半导体元件的方法。首先提供一基底，该基底上具有一管芯区以及一切割道区，然后形成一接触垫于基底上的管芯区并重叠切割道区。
本发明另一实施例揭露一种半导体元件，其包含一基底，该基底上具有一管芯区以及一切割道区，以及一接触垫设于基底上的管芯区并重叠切割道区。
附图说明
图1为本发明优选实施例的一半导体晶片的结构示意图；
图2为本发明图1中接触垫与切割道区的局部示意图；
图3为图2中沿着切线AA’的剖面示意图；
图4为本发明优选实施例的一管芯的立体结构示意图；
图5为本发明另一实施例的一半导体元件的剖面示意图。
主要元件符号说明
12 基底 14 管芯区
16 切割道区 18 金属层
20 第一金属间介电层 22 金属层
24 接触插塞 26 第二金属间介电层
28 接触洞开口 30 接触洞开口
32 金属层 34 第三金属间介电层
36 接触洞开口 38 接触洞开口
40 氧化硅层 42 氮化硅层
44 金属层 46 接触垫
48 保护层 50 氧化硅层
52 氮化硅层 54 切割路线
56 切割工具 58 管芯
具体实施方式
请同时参照图1至图4，图1为本发明优选实施例的一半导体晶片的结构示意图，图2为本发明图1中接触垫与切割道区的局部示意图，图3为图2中沿着切线AA’的剖面示意图，图4为本发明优选实施例的一管芯的立体结构示意图。如图1至图4所示，首先提供一基底12或半导体芯片，例如一由晶片或其他半导体材料所构成的基底12，其中半导体材料可选自由硅、锗、硅锗复合物、硅碳化物(silicon carbide)、砷化镓(gallium arsenide)等所构成的群组。
然后于基底12上定义至少一管芯区14以及一切割道(scribe line)区16，其中各管芯区14中具有集成电路，切割道区16设于管芯区14外围，且切割道区16与管芯区14之间又可依据产品需求设置一管芯封环区(图未示)。
基底12上可包含例如金属氧化物半导体(metal-oxide semiconductor,MOS)晶体管等主动元件、被动元件以及层间介电层(interlayer dielectric,ILD)(图未示)等介电层覆盖于其上。更具体而言，基底12上可包含平面型或非平面型(如鳍状结构晶体管)等MOS晶体管元件，其中MOS晶体管可包含金属栅极、源极/漏极区域、间隙壁、外延层、接触洞蚀刻停止层等晶体管元件。层间介电层可设于基底12上并覆盖MOS晶体管，且层间介电层中可设有多个接触插塞，并通过金属层18等导线电连接MOS晶体管的栅极以及/或源极/漏极区域至更上层线路或外部元件。由于平面型或非平面型晶体管与层间介电层等相关制作工艺均为本领域所熟知技术，在此不另加赘述。
然后形成一第一金属间介电层(inter-metal dielectric,IMD)20于基底上并覆盖层间介电层与金属层18，接着形成另一金属层22于第一金属间介电层20上并利用接触插塞24连接金属层18与金属层22。在本实施例中，第一金属间介电层20优选由氧化硅所构成且其厚度约略10000埃，而金属层18与金属层22的厚度则分别约为5000埃。
随后形成一第二金属间介电层26于第一金属间介电层20上，然后进行一光刻暨蚀刻制作工艺去除部分位于管芯区14以及切割道区16的第二金属间介电层26，以形成一接触洞开口28暴露金属层22表面以及另一接触洞开口30暴露部分位于管芯区14以及切割道区16的第一金属间介电层20。在本实施例中，第二金属间介电层26优选由氧化硅所构成，且其厚度约为50000埃。
接着形成一金属层32于第二金属间介电层26上并填入接触洞开口28及接触洞开口30，其中填入接触洞开口30的金属层32优选由管芯区14的第二金属间介电层26上表面延伸至第二金属间介电层26侧壁以及位于切割道区16的第一金属间介电层20上表面。换句话说，所形成的金属层32图案优选同时重叠部分的管芯区14与切割道区16，其中金属层32的厚度约为8000埃。
然后形成一第三金属间介电层34于第二金属间介电层26与金属层32上，并进行一光刻暨蚀刻制作工艺去除部分位于管芯区14以及切割道区16第三金属间介电层34以形成一接触洞开口36暴露位于管芯区14的金属层32表面以及另一接触洞开口38暴露部分位于管芯区14与切割道区16的金属层32。在本实施例中，第三金属间介电层34优选为一复合层结构，例如由一氧化硅层40与一氮化硅层42所构成，其中氧化硅层40的厚度约为10000埃而氮化硅层42的厚度则约为50000埃。
接着形成一金属层44于第三金属间介电层34上并填入接触洞开口36及接触洞开口38，其中填入接触洞开口38的金属层44优选由管芯区14的第三金属间介电层34上表面延伸至第三金属间介电层34侧壁及位于切割道区16的金属层32上表面。如图中所示，所形成的金属层44图案优选直接接触金属层32图案并同时重叠的管芯区14及切割道区16。在本实施例中，金属层44的厚度约为20000埃，且由管芯区14延伸至切割道区16的金属层44与金属层32优选作为本实施例半导体元件的接触垫46。不局限上述实施例，金属层18与金属层22也可以由管芯区14延伸至切割道区16而与金属层44或金属层32来共同构成接触垫46，此外，接触垫46也可仅包含单一的金属层44、单一的金属层32、单一的金属层22或者是单一的金属层18，然而接触垫46的厚度优选需大于25000埃以上。
随后形成一保护层48于第三金属间介电层34与金属层44上并以光刻暨蚀刻方式去除部分位于金属层44表面，特别是切割道区16及部分管芯区14的保护层48。在本实施例中，保护层48优选为一复合层结构，例如一氧化硅层50与一氮化硅层52，其中氧化硅层50的厚度约略6000埃而氮化硅层52的厚度则约为10000埃。之后可依据制作工艺需求进行一切割制作工艺，利用例如钻石切割刀等切割工具56沿着切割道区16中的切割路线(diesaw path or dicing path)54将基底12分隔为多个管芯后再进行后续封装制作工艺。需注意的是，由于本实施例中作为接触垫46的金属层44与其下的金属层32及第一金属间介电层20均由管芯区14延伸至切割道区16，因此进行前述切割制作工艺时金属层44与其下的金属层32及部分第一金属间介电层20均会与基底12一同被切割而形成所需的管芯58，且各接触垫46的裁切边会切齐于管芯58的切割边，如图4所示。
又如图1至图4所示，本实施例另揭露一种半导体元件，其主要包含一基底12以及一接触垫46设于基底12上并同时重叠基底12上的管芯区14与切割道区16。更具体而言，基底12上包含一第一金属间介电层20覆盖于各种主动元件与层间介电层上、一第二金属间介电层26设于第一金属间介电层20上、一接触洞开口28与接触洞开口30位于第二金属间介电层26中、一金属层32设于第二金属间介电层26上并填入接触洞开口28与30、一第三金属间介电层34设于第二金属间介电层26及金属层32上、一接触洞开口36与接触洞开口38位于第三金属间介电层34中、一金属层44设于第三金属间介电层34上并填入接触洞开口36与38以及一保护层48设于第三金属间介电层34及部分金属层44上。其中金属层32、44优选选自由铝(Al)、钛(Ti)、钽(Ta)、钨(W)、铌(Nb)、钼(Mo)以及铜(Cu)所构成的群组，最佳为铝，但不局限于此。
另外在本实施例中，接触洞开口30与接触洞开口38均重叠部分的管芯区14及切割道区16，使设于接触洞开口30、38内的金属层32及金属层44亦同时重叠管芯区14与切割道区16，其中所暴露出的金属层44优选形成本实施例的半导体元件的接触垫46，而且通过跨设于管芯区14及切割道区16的接触洞开口30、38更可大幅降低切割道区16的金属间介电层的厚度，以有效避免在进行切割制作工艺时发生脱层(delamination)、裂缝(cracking)或裂痕(peeling)等现象。其次，保护层48上表面至重叠切割道区16的接触垫46上表面的垂直距离优选大于15微米，而接触垫46重叠切割道区16的距离则优选大于150微米。
请接着参照图5，图5为本发明另一实施例的一半导体元件的剖面示意图。如同前述实施例，本实施例也于基底12与层间介电层上依序形成第一金属间介电层20、第二金属间介电层26、第三金属间介电层34与保护层48，且于第二金属间介电层26中形成接触洞开口30、于第三金属间介电层34中形成接触洞开口38以及于接触洞开口30、38中形成重叠管芯区14与切割道区16的金属层32与金属层44以构成接触垫46。相较于前述的实施例，本实施例仅于第二金属间介电层26及第三金属间介电层34中各形成一接触洞开口30、38跨过管芯区14与切割道区16的交界，由此提供一种更简化的线路走向。
综上所述，本发明优选揭露一种改良式的接触垫结构，其主要于制作金属内连线制作工艺，亦即于MOS晶体管与层间介电层等元件上形成金属间介电层与金属导线时将原本位于管芯区的金属层或金属图案延伸至切割道区，使金属图案同时重叠管芯区与切割道区并将暴露于切割道区的金属层或金属图案作为后续封装时的接触垫。由于本发明的金属图案或重布线(re-distribution layer,RDL)图案可由原本位置较高的管芯区直接延伸至较低的切割道区而直接形成接触垫，后续进行封装时便可省略一道重布线(re-distribution layer,RDL)制作工艺来连接芯片中的线路，不但降低制作工艺的复杂性又可大幅节省制作成本。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (19)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上具有一管芯区以及一切割道区；以及
形成一接触垫于该基底上的该管芯区并重叠该切割道区。
2.如权利要求1所述的方法，还包含：
形成一第一金属间介电层于该基底上；
形成一第二金属间介电层于该第一金属间介电层上；
形成一第一接触洞开口于该第二金属间介电层中；
形成一第一金属层于该第二金属间介电层上并填入该第一接触洞开口；
形成一第三金属间介电层于该第二金属间介电层及该第一金属层上；
形成一第二接触洞开口于该第三金属间介电层中；
形成一第二金属层于该第三金属间介电层上并填入该第二接触洞开口；以及
形成一保护层于该第三金属间介电层及部分该第二金属层上。
3.如权利要求2所述的方法，还包含形成该第一接触洞开口于该管芯区及该切割道区。
4.如权利要求3所述的方法，其中该切割道区的该第一接触洞开口暴露该第一金属间介电层。
5.如权利要求2所述的方法，其中该第一金属层重叠该管芯区及该切割道区。
6.如权利要求2所述的方法，还包含形成该第二接触洞开口于该管芯区及该切割道区。
7.如权利要求2所述的方法，其中该切割道区的该第二接触洞开口暴露该第一金属层。
8.如权利要求2所述的方法，其中该第二金属层重叠该管芯区及该切割道区以形成该接触垫。
9.如权利要求8所述的方法，其中该切割道区的该第二金属层直接接触该第一金属层。
10.如权利要求2所述的方法，还包含对该第二金属层、该第一金属层及该第一金属间介电层进行一切割制作工艺。
11.一种半导体元件，包含：
基底，该基底上具有一管芯区以及一切割道区；以及
接触垫设于该基底上的该管芯区并重叠该切割道区。
12.如权利要求11所述的半导体元件，还包含：
第一金属间介电层设于该基底上；
第二金属间介电层设于该第一金属间介电层上；
第一接触洞开口位于该第二金属间介电层中；
第一金属层设于该第二金属间介电层上并填入该第一接触洞开口；
第三金属间介电层设于该第二金属间介电层及该第一金属层上；
第二接触洞开口位于该第三金属间介电层中；
第二金属层设于该第三金属间介电层上并填入该第二接触洞开口；以及
保护层设于该第三金属间介电层及部分该第二金属层上。
13.如权利要求12所述的半导体元件，其中该第一接触洞开口位于该管芯区及该切割道区上。
14.如权利要求12所述的半导体元件，其中该第一金属层重叠该管芯区及该切割道区。
15.如权利要求12所述的半导体元件，其中该第二接触洞开口位于该管芯区及该切割道区。
16.如权利要求12所述的半导体元件，其中该第二金属层重叠该管芯区及该切割道区以形成该接触垫。
17.如权利要求16所述的半导体元件，其中该切割道区的该第二金属层直接接触该第一金属层。
18.如权利要求12所述的半导体元件，其中该保护层上表面至重叠该切割道的该接触垫上表面的距离大于15微米。
19.如权利要求12所述的半导体元件，其中该接触垫重叠该切割道的距离大于150微米。
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