CN106298484B - The forming method of MOS transistor - Google Patents
The forming method of MOS transistor Download PDFInfo
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- CN106298484B CN106298484B CN201510292970.8A CN201510292970A CN106298484B CN 106298484 B CN106298484 B CN 106298484B CN 201510292970 A CN201510292970 A CN 201510292970A CN 106298484 B CN106298484 B CN 106298484B
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- 230000004888 barrier function Effects 0.000 claims abstract description 172
- 238000010849 ion bombardment Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 238000004544 sputter deposition Methods 0.000 claims abstract description 24
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- 238000000231 atomic layer deposition Methods 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 14
- 230000008569 process Effects 0.000 description 13
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- 229910052782 aluminium Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
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- 150000002500 ions Chemical class 0.000 description 9
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- 238000004519 manufacturing process Methods 0.000 description 5
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical group [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
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- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 238000000227 grinding Methods 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- PDKGWPFVRLGFBG-UHFFFAOYSA-N hafnium(4+) oxygen(2-) silicon(4+) Chemical compound [O-2].[Hf+4].[Si+4].[O-2].[O-2].[O-2] PDKGWPFVRLGFBG-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical group O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
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- 239000012212 insulator Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- 238000005477 sputtering target Methods 0.000 description 1
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- 238000007738 vacuum evaporation Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
A kind of forming method of MOS transistor, comprising: semiconductor substrate is provided；Pseudo- grid structure is formed on the semiconductor substrate, and dummy gate structure two sides have the bottom of sufficient shape；The dielectric layer between dummy gate structure pericambium on the semiconductor substrate, the interlayer dielectric layer upper surface are flushed with the upper surface of dummy gate structure；For removal dummy gate structure to form groove, the groove two sides have the base angle of sufficient shape；Boundary layer is formed in the bottom of the groove；High-k dielectric layer is formed in the bottom and side wall of the groove, the high-k dielectric layer covers the boundary layer；The first diffusion barrier layer is formed in the high-k dielectric layer；Ion bombardment processing is carried out using part of the sputtering method to groove notch described in the first diffusion barrier layer face；After ion bombardment processing, the second diffusion barrier layer is formed on first diffusion barrier layer.The forming method improves the performance of MOS transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of MOS transistor.
Background technique
With the continuous improvement of semiconductor devices integrated level, when making MOS transistor, with high k (high dielectric constant) material
Material is used as gate dielectric layer, and using metal material as grid, has become the mainstream technology of semiconductor devices manufacture.
It is existing to have metal gates-high-k dielectric layer structure MOS transistor be using two kinds of sides of first grid and post tensioned unbonded prestressed concrete
Method is formed.Which kind of, however, no matter method used, can all encounter in metal gates, there is a phenomenon where spread for metal.
Especially when using aluminium as metal gates, the diffusion of aluminium becomes the significant problem of MOS transistor production.The expansion of aluminium
The unfailing performance of breaking up damage effect device, such as damage effect time breakdown performance (time dependent dielectric
Breakdown, TDDB), Negative Bias Temperature Instability can (Negative Bias Temperature Instability,
NBTI) and positive bias temperature instability can (Positive Bias Temperature Instability, PBTI) etc..And
And the carrier mobility of MOS transistor also declines because of the diffusion of aluminium, device performance is greatly affected.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of MOS transistor, to improve the performance of MOS transistor.
To solve the above problems, the present invention provides a kind of forming method of MOS transistor, comprising:
Semiconductor substrate is provided；
Pseudo- grid structure is formed on the semiconductor substrate, and dummy gate structure two sides have the bottom of sufficient shape；
The dielectric layer between dummy gate structure pericambium on the semiconductor substrate, table on the interlayer dielectric layer
Face is flushed with the upper surface of dummy gate structure；
For removal dummy gate structure to form groove, the groove two sides have the base angle of sufficient shape；
Boundary layer is formed in the bottom of the groove；
High-k dielectric layer is formed in the bottom and side wall of the groove, the high-k dielectric layer covers the boundary layer；
The first diffusion barrier layer is formed in the high-k dielectric layer；
It is carried out at ion bombardment using part of the sputtering method to groove notch described in the first diffusion barrier layer face
Reason；
After ion bombardment processing, the second diffusion barrier layer is formed on first diffusion barrier layer.
Optionally, the sputtering method carries out at the ion bombardment first diffusion barrier layer using argon ion
Reason.
Optionally, first diffusion barrier layer is formed using physical gas-phase deposite method.
Optionally, carried out in same reaction chamber first diffusion barrier layer forming step and the ion bombardment
Processing step.
Optionally, second diffusion barrier layer is formed using Atomic layer deposition method.
Optionally, first diffusion barrier layer is identical with second diffusion barrier material.
Optionally, the material of first diffusion barrier layer and second diffusion barrier layer is titanium nitride.
Optionally, the thickness range of first diffusion barrier layer is
Optionally, the thickness range of second diffusion barrier layer is
Optionally, after forming second diffusion barrier layer, further includes:
Workfunction layers are formed on second diffusion barrier layer；
Metal layer is formed in the workfunction layers, the metal layer fills the full groove.
Compared with prior art, technical solution of the present invention has the advantage that
In technical solution of the present invention, there is the pseudo- grid structure of sufficient shape bottom by being initially formed, so that guaranteeing to be formed has
Then the groove of sufficient shape bottom is formed the first diffusion barrier layer in a groove, and is handled using ion bombardment, so that the first diffusion
Barrier layer is located in the part of bottom portion of groove, and interior thickness becomes uniformly, and two-end thickness increases, later on the first diffusion barrier layer
The second diffusion barrier layer is formed, the first diffusion barrier layer and the second diffusion barrier layer form corresponding diffusion barrier layer together, from
And be better protected from metal gates and metal diffusion occurs, improve the performance of MOS transistor.
Further, carried out in same reaction chamber first diffusion barrier layer forming step and the ion bombardment
Processing step, so that the time is saved, save the cost.
Detailed description of the invention
Fig. 1 to Fig. 8 is each step counter structure signal of forming method of MOS transistor provided by the embodiment of the present invention
Figure.
Specific embodiment
Inventors have found that the aluminium in metal gates has two diffused lines, one is by downward below metallic aluminum gate
Diffusion (passes through diffusion downwards above channel region), and another is diffused by metallic aluminum gate two sides.Although existing
The forming method of MOS transistor is initially formed diffusion resistance before making metal gates in the groove for filling metal gates
Barrier still, has big shrinkage stress (spy since the diffusion barrier layer of existing method production usually has to prevent aluminium from spreading
It is not the diffusion barrier layer formed using physical vaporous deposition, stress is larger), under stress, diffusion barrier layer can go out
The case where part now positioned at bottom portion of groove center is thick big, and the thickness of past groove two sides bottom corner portion is gradually reduced, that is, be located at recessed
Thick middle, thinning " bow " shape in both ends (" bow " shape), the diffusion barrier of this shape is presented in the diffusion barrier layer of trench bottom
Layer cannot prevent aluminium from spreading well, easily cause aluminium by groove two sides base angle to the case where external diffusion.In addition, existing method shape
When at diffusion barrier layer, step coverage is usually smaller, causes the diffusion barrier thickness positioned at recess sidewall smaller, therefore,
Aluminium is also easy through groove two sides side wall to external diffusion, i.e. aluminium is easy to be diffused by metallic aluminum gate two sides.
For this purpose, the present invention provides a kind of forming method of new MOS transistor, the forming method has by being initially formed
Then each pseudo- grid structure of sufficient shape bottom forms each the to guarantee to form each groove with sufficient shape bottom in each groove
One diffusion barrier layer, and handled using ion bombardment, so that each first diffusion barrier layer is located in the part of each bottom portion of groove, in
Between thickness become uniformly, two-end thickness increase, each second diffusion barrier layer is correspondingly formed on each first diffusion barrier layer later, respectively
First diffusion barrier layer to corresponding each diffusion barrier layer is just formed together with each second diffusion barrier layer, to be better protected from
Metal diffusion occurs for metal gates, improves the performance of MOS transistor.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of forming method of MOS transistor, incorporated by reference to referring to figs. 1 to Fig. 8.
Referring to FIG. 1, providing semiconductor substrate 100.
In the present embodiment, semiconductor substrate 100 is specially silicon substrate.In other embodiments, semiconductor substrate 100 be can be
Germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates, silicon-on-insulator substrate or Buddha's warrior attendant stone lining
Bottom can also be the substrate of other semiconductor materials known to those skilled in the art.
Isolation structure (not marking) can also be formed in the present embodiment, in semiconductor substrate 100, the isolation structure can
To be fleet plough groove isolation structure or other isolation structures for device isolation or active area isolation.The isolation structure can be with
For separating different active areas.
By the isolation of the isolation structure, there is the first active area in semiconductor substrate 100 provided by the present embodiment
(not marking) and the second active area (not marking), this specification Fig. 1 is into Fig. 8 with dotted line (not marking) by first active area
It is further distinguish with the second active area, the active area on the dotted line left side is first active area, the active area on the right of dotted line
For second active area.
With continued reference to FIG. 1, forming pseudo- grid structure on a semiconductor substrate 100, and formed in dummy gate structure two sides
The bottom of sufficient shape (footing), that is to say, that dummy gate structure two sides have the bottom of sufficient shape.Specifically, described first
Active area forms the first pseudo- grid structure (not marking), and the described first pseudo- grid structure is pseudo- including the first dummy grid 110 and positioned at first
Dielectric layer 101 between grid 110 and semiconductor substrate 100.The second pseudo- grid structure is formed in second active area (not mark
Note), the second pseudo- grid structure includes the second dummy grid 120 and between the second dummy grid 120 and semiconductor substrate 100
Dielectric layer 101.
The bottom of each dummy gate structure foot shape can surround part with reference to each virtual coil (not marking) in Fig. 1.
The process for forming the described first pseudo- grid structure and the second pseudo- grid structure can be with are as follows: in first active area and second
Surfaces of active regions forms dielectric layer 101, and pseudo- gate material layer (not shown) is formed on dielectric layer 101, in the pseudo- gate material layer
The first mask layer (not shown) of upper formation, forms the second mask layer on first mask layer and (does not show
Out), patterned photoresist layer (not shown) is formed on second mask layer, using the photoresist layer as mask,
It is sequentially etched second mask layer, the first mask layer, pseudo- gate material layer, to form the above-mentioned first pseudo- grid structure
With the second pseudo- grid structure, first mask layer and the second material mask layer in the described first pseudo- grid structure retain
For the first mask layer 111 and the second mask layer 112, first mask layer in the described second pseudo- grid structure and the
Two material mask layers are left the first mask layer 121 and the second mask layer 122, as shown in Figure 1.
It should be noted that entire first surfaces of active regions is gone back while being located to dielectric layer 101 in the present embodiment, with
And entire second surfaces of active regions.In other embodiments, the dielectric layer can be only located at dummy grid and semiconductor substrate
(i.e. the dielectric layer is only positioned between the first dummy grid 110 and semiconductor substrate 100 and the second dummy grid at this time between 100
Between 120 and semiconductor substrate 100, there is no the media not covered directly by the first dummy grid 110 or the second dummy grid 120
Layer).To guarantee that the dielectric layer is only located between dummy grid and semiconductor substrate 100, the first pseudo- grid structure and second is being formed
It when pseudo- grid structure, can continue to etch the dielectric layer downwards, not covered by the first pseudo- grid structure and the second pseudo- grid structure with removing
The dielectric layer of lid.It should be noted that eliminating not in other embodiments by the first pseudo- grid structure and the second pseudo- grid knot
After the dielectric layer of structure covering, the new dielectric layer can also be re-formed on exposed semiconductor substrate surface.
It should be strongly noted that in existing forming method, it is undesirable that the described first pseudo- grid structure and the second pseudo- grid
Structure two sides form the bottom of sufficient shape, but in forming method provided by the present invention, exclusively with this foot of pseudo- grid structure
Shape bottom.
In the present embodiment, the material of dielectric layer 101 can be silica.The material of the puppet gate material layer can be polycrystalline
Silicon, the i.e. material of the first dummy grid 110 and the second dummy grid 120 can be polysilicon.The material of first mask layer
It can be silica, the material of second mask layer can be silicon nitride.
Referring to FIG. 2, forming the first offset side wall 113 in 110 two sides of the first dummy grid, and with the first offset side wall 113
For mask, the semiconductor substrate 100 of the described first pseudo- grid structure down either side is carried out that source and drain injection (LDD) is lightly doped, with shape
At the first lightly doped district (not shown).Likewise, forming the second offset side wall 123 in 120 two sides of the second dummy grid, and with described
Second offset side wall 123 is mask, to the semiconductor substrate 100 of the described second pseudo- grid structure down either side carries out that source and drain is lightly doped
Injection, to form the second lightly doped district (not shown).
In the present embodiment, the material of the first offset side wall 113 and the second offset side wall 123 can be silica.
With continued reference to FIG. 2, forming the first main side wall 114 in 110 two sides of the first dummy grid to cover the first offset side wall
113, and be mask with first main side wall 114, the semiconductor substrate 100 of the described first pseudo- grid structure down either side is carried out
The injection of heavy doping source and drain, to form the first heavily doped region (not shown), first heavily doped region is corresponding for the first dummy grid 110
Source region or drain region.Likewise, forming the second main side wall 124 in 120 two sides of the second dummy grid to cover the second offset side wall
123, and be mask with second main side wall 124, the semiconductor substrate 100 of the described second pseudo- grid structure down either side is carried out
The injection of heavy doping source and drain, to form the second heavily doped region (not shown), second heavily doped region is corresponding for the second dummy grid 120
Source region or drain region.
In the present embodiment, the material of the first main side wall 114 and the second main side wall 124 can be silicon nitride.
It should be noted that in other embodiments, it can also be in the described first pseudo- grid structure and the second dummy gate structure
The semiconductor substrate 100 of down either side forms the regions such as pocket (Pocket) doped region.
It, can also be the when second active area forms PMOS transistor with continued reference to FIG. 2, in the present embodiment
Groove (not shown), the i.e. semiconductor substrate in the second pseudo- grid structure down either side are formed in the source region of two active areas and drain region
100 form the groove, and fill the full groove using germanium silicon iso-stress material, form 1201 (i.e. shape of stress germanium silicon structure
At the embedded germanium silicon of source and drain).
It should be noted that although not shown in the drawing, in the present embodiment, the first active area formed NMOS transistor, first
Not formed stress structure in active area.It, can also be when the first active area forms NMOS transistor but in other embodiments
Stress carbon silicon structure is formed in the source region of first active area and drain region.
Referring to FIG. 3, on a semiconductor substrate 100 with the above-mentioned first pseudo- grid structure and the second pseudo- grid structure pericambium
Between dielectric layer 102, and interlayer dielectric layer 102 is planarized, makes 102 upper surface of interlayer dielectric layer and above-mentioned each pseudo- grid structure
Upper surface flush.Specifically, the present embodiment makes 102 upper surface of interlayer dielectric layer and the first dummy grid 110 and the second pseudo- grid
The upper surface of pole 120 flushes.
In the present embodiment, the material of interlayer dielectric layer 102 can be silica or silicon nitride.Forming interlayer dielectric layer
After 102, interlayer dielectric layer 102 and two dummy gate structures can be carried out using chemical mechanical grinding (CMP) method flat
Smoothization, to remove the first mask layer 111, the second mask layer 112, the first mask layer 121 and the second mask layer shown in Fig. 2
122, so that 102 upper surface of interlayer dielectric layer and the upper surface of first dummy grid 110 and the second dummy grid 120 be made to flush.
Referring to FIG. 4, removing dummy gate structure shown in Fig. 3 to form groove, the groove two sides have sufficient shape
Base angle.Specifically, the pseudo- grid structure of removal described first forms the first groove 1100, removes the described second pseudo- grid structure and form second
Groove 1200.
In the present embodiment, can using dry etch process or the pseudo- grid structure of wet-etching technology removal described first and
Second pseudo- grid structure, also, corresponding etching technics can also remove 113 He of the first offset side wall shown in Fig. 3 by etching off in the same time
Second offset side wall 123.
Referring to FIG. 5, the first boundary layer 115 is formed in the bottom of the first groove 1100, in the bottom of the second groove 1200
Form second interface layer 125.
In the present embodiment, the material of each boundary layer can be silica, can use chemical oxidization method or hot oxygen
Change method directly forms each boundary layer on substrate.In other embodiments of the invention, each boundary layer may be
Other materials with low-k are made, such as lanthana (L2O3).The boundary layer can be improved channel
(trench) carrier mobility, and the damage that can be subject to repairing semiconductor substrate 100 in the etching process for forming the groove
Wound.
With continued reference to FIG. 5, the bottom and side wall in the first groove 1100 forms the first high-k dielectric layer 116, the first high k
Dielectric layer 116 covers the first boundary layer 115.The second high-k dielectric layer 126 is formed in the bottom and side wall of the second groove 1200, the
Two high-k dielectric layer 126 cover second interface layer 125.
In the present embodiment, the material of the high-k dielectric layer can be hafnium oxide (HfO2), silicon hafnium oxide (HfSiO), nitrogen oxygen
Change hafnium (HfON), nitrogen oxidation hafnium silicon (HfSiON), lanthana (La2O3), zirconium oxide (ZrO2), silicon zirconium oxide (ZrSiO), oxidation
Titanium (TiO2) and yttrium oxide (Y2O3) one of or a variety of any combination.The high-k dielectric layer can be using sputtering, pulse
Laser deposition (Pulsed Laser Deposition, PLD), metallo-organic compound chemical vapor infiltration (Metal-
Organic Chemical Vapor Deposition, MOCVD), atomic layer deposition method (Atomic layer
Deposition, ALD) or other suitable methods formed.
(there is the first high k to be situated between referring to FIG. 6, forming the first diffusion barrier layer 117 in the first high-k dielectric layer 116
1100 bottom and side wall of the first groove of matter layer 116 forms the first diffusion barrier layer 117), the shape in the second high-k dielectric layer 126
At the first diffusion barrier layer 127 (first is formed in 1200 bottom and side wall of the second groove with the second high-k dielectric layer 126
Diffusion barrier layer 127).
In the present embodiment, the material of the first diffusion barrier layer 117 and the first diffusion barrier layer 127 can be titanium nitride.
In the present embodiment, the thickness range that can control the first diffusion barrier layer 117 and the first diffusion barrier layer 127 isOn the one hand, the first diffusion barrier layer 117 and the first diffusion barrier layer 127 is enable to be completely covered on each groove
Each surface, on the other hand, prevent the first diffusion barrier layer 117 and 127 thickness of the first diffusion barrier layer too big, influence subsequent
The filling of each groove.
In the present embodiment, the first diffusion barrier layer 117 and first can be formed using physical gas-phase deposite method (PVD) and is expanded
Dissipate barrier layer 127.The physical vaporous deposition can use vacuum evaporation, sputter coating (sputtering method), arc plasma
A variety of methods such as body plating, ion film plating and molecular beam epitaxy carry out.In the present embodiment, it can specifically be carried out using sputtering method.
It when physical vaporous deposition is carried out using sputtering method, is made under the conditions of the certain vacuum of filling with inert gas
Inert gas carries out glow discharge, and at this moment intert-gas atoms are ionized into inert gas ion, and inert gas ion is in electric field force
Under the action of, accelerate bombardment to plate the cathode targets (such as titanium nitride target) of material production, target can be sputtered out and deposit
To the bottom and side wall surface of the first groove 1100 and the second groove 1200.If claiming d.c. sputtering using direct current glow discharge,
Using claiming radio-frequency sputtering caused by radio frequency (RF) glow discharge, using claiming magnetron sputtering caused by magnetic-control glow discharge.It sputtered
The conversion of Cheng Hanyou momentum, so the particle sputtered is directive.
Physical vaporous deposition process is simple, and pollution-free to enhancement of environment, consumptive material is few, and form a film even compact and binding force
By force.Also, since physical vaporous deposition step coverage is lower, each first diffusion barrier layer of formation is located at each recessed
The segment thickness of groove sidewall is smaller, therefore, there is no need to each recessed to expand using other techniques (such as anti-reflecting layer formation process)
The opening size (improve the filling capacity of subsequent technique) of slot, to save processing step.
But due to the feature of material and method itself, 117 He of the first diffusion barrier layer of physical vaporous deposition formation
There is biggish shrinkage stress inside first diffusion barrier layer 127, cause to be formed by the first diffusion barrier layer 117 and the first expansion
It dissipates in barrier layer 127, the thin situation in thick middle both ends easily occurs (in general, each first diffusion positioned at the part of corresponding recesses bottom
Barrier layer is located in the part of each bottom portion of groove, middle section can 50~70%) thicker than both ends, as shown in Figure 6.Also, by
It is lower in the step coverage of physical vaporous deposition, therefore, the first diffusion barrier layer 117 and the first diffusion barrier layer 127
It is less than the thickness positioned at corresponding recesses bottom in the thickness of corresponding recesses side wall, causes the metal in subsequent metal grid easily along grid
The case where pole two sides are spread.And since the step coverage of physical gas-phase deposite method is lower, and positioned at each bottom portion of groove
To middle shrinkage, the reason of the two aspects, causes the first diffusion barrier layer 117 and the first diffusion barrier layer 127 jointly for part
Part at each groove base angle is most thin, i.e. the first diffusion barrier layer 117 and the first diffusion barrier layer 127 are located at each bottom portion of groove
Part be in " bow " shape, as shown in fig. 6, therefore, if the gold only by this scheme formation diffusion barrier layer, in subsequent metal grid
Category is easiest to be diffused (while being also easy to be diffused along metal gates two sides) along the base angle of each groove.
In summary it is found that the metal in metal gates is easiest to be diffused along the base angle of each groove, and it is easy edge
The problem of grid two sides are spread.And through this embodiment provided by forming method, can obtain preferably solving described problem,
Concrete reason is please continue to refer to this specification subsequent content.
Referring to FIG. 7, using sputtering method to the part of groove notch shown in described first diffusion barrier layer face Fig. 6 into
The processing of row ion bombardment.Specifically, using sputtering method to the portion of 117 the first groove of face of the first diffusion barrier layer, 1100 notch
Divide and carry out ion bombardment processing, using sputtering method to the part of 127 the second groove of face of the second diffusion barrier layer, 1200 notch
Carry out ion bombardment processing.
Since in ion bombardment processing, being controlled with direction by direction of an electric field for ion (is applied direction control by voltage
System), therefore, ion bombardment processing has directionality (anisotropy).It is short with two in first active region in Fig. 6
Dotted line (not marking) shows the position of 1100 notch face of the first groove, squeezes into 1100 bottom of the first groove downwards from this these position
The ion in portion can cause bombardment to act on the first diffusion barrier layer 127.Likewise, second active region, two short void
Line (not marking) shows the position of 1200 notch face of the second groove, squeezes into 1200 bottom of the second groove downwards from this these position
Ion bombardment can be caused to act on the first diffusion barrier layer 127.
In the present embodiment, the sputtering method can be carried out at ion bombardment the first diffusion barrier layer using argon ion
Reason.The projectile of sputtering is usually positively charged inert gas ion, and with the most use is argon ion.
It has been mentioned hereinbefore that the present embodiment can form the first diffusion barrier layer using physical vaporous deposition, therefore, this
Embodiment can use the sputtering method used in above-mentioned physical vaporous deposition and carry out the ion bombardment processing.Due to this
Embodiment can use the sputtering method in processes of physical vapor deposition and carry out the ion bombardment processing, therefore, the present embodiment
In, the forming step and ion bombardment processing step of first diffusion barrier layer can be carried out in same reaction chamber
Suddenly, to save the time, save the cost.In other embodiments, the forming step of first diffusion barrier layer and the ion
Bombardment processing step can also carry out in different chambers or equipment, at this point, the ion bombardment processing can individually into
Row, but its process and principle can refer to foregoing teachings.
Carrying out the ion bombardment processing using the sputtering method that uses in above-mentioned physical vaporous deposition specifically can be with
Including following operation: corresponding sputtering target material being removed or stopped, changes the condition of the sputtering, including apply and the physics
The opposite voltage of vapor deposition method process makes corresponding ion counter motion, to keep ion direct by each groove notch
The part that each first diffusion barrier layer is located at each bottom portion of groove is bombarded, realizes the ion bombardment processing.Specific mistake
Cheng Zhong, it is adjustable so that the bombardment processing uses lesser sputtering bias-voltage, to make the first diffusion barrier layer 117 and first
Diffusion barrier layer 127 can be made in the first diffusion barrier layer 117 and the first diffusion barrier layer 127 by after corresponding ion bombardment
The corresponding particle in portion migrates, but corresponding particle will not escape again to each groove outside or each recess sidewall, but only
It is migrated to both ends, even and if guaranteeing that the corresponding particle of small part can be after the evolution of each first diffusion barrier layer, also without enough
Energy is mobile to other regions, but equally falls the base angle (sputtering that this process can be considered a kind of low energy) to groove two sides.
Relatively long bombardment time is suitably used with this condition, to guarantee by 117 He of the first diffusion barrier layer of bombardment processing
In first diffusion barrier layer 127, corresponding particle is sufficiently mobile to the base angle of each notch two sides, and then makes each groove in sufficient shape
Finally filled by each first diffusion barrier layer full in base angle.Finally, the present embodiment makes each first diffusion resistance by the sputtering process
The case where barrier is located at the part of each bottom portion of groove, the situation thin from script thick middle both ends, becomes both ends thickness middle flat, such as
Shown in Fig. 7.
After the ion bombardment processing, the first diffusion barrier layer 117 shown in Fig. 6 is converted into the first diffusion barrier shown in Fig. 7
Layer 118, the difference of the first diffusion barrier layer 118 and the first diffusion barrier layer 117 is, 118 face of the first diffusion barrier layer the
The thickness of the part of one groove, 1100 notch is substantially uniform, also, since to be filled up completely full first recessed for the first diffusion barrier layer 118
The base angle of the sufficient shape of slot 1100, therefore the first diffusion barrier layer 118 is located at the thickness maximum of 1100 two sides bottom corner portion of the first groove.
Likewise, the second diffusion barrier layer 127 shown in Fig. 6 is converted into the second diffusion barrier layer shown in Fig. 7 after the ion bombardment processing
128, the difference of the first diffusion barrier layer 128 and the first diffusion barrier layer 127 is, 128 face second of the first diffusion barrier layer
The thickness of the part of 1200 notch of groove is substantially uniform, also, since the first diffusion barrier layer 128 is filled up completely full second groove
The base angle of 1200 sufficient shapes, therefore the first diffusion barrier layer 128 is located at the thickness maximum of 1200 two sides bottom corner portion of the second groove.
In summary, the present embodiment is first with each pseudo- grid structure with sufficient shape bottom, so that guaranteeing to be formed has sufficient shape
Then each groove of bottom is formed each first diffusion barrier layer in each groove, and is handled using ion bombardment, so that each first
Diffusion barrier layer is located in the part of each bottom portion of groove, and interior thickness becomes uniformly, and two-end thickness increases.As it can be seen that just because of shape
At the groove of sufficient shape bottom, therefore, subsequent each first diffusion barrier layer that can form filling groove foot shape bottom, also
Be to say, can guarantee in finally formed each first diffusion barrier layer, be located at bottom portion of groove part two-end thickness it is maximum and in
Between thickness it is uniform.
Referring to FIG. 8, forming the second diffusion barrier layer on the first diffusion barrier layer after ion bombardment processing.Specifically
, the second diffusion barrier layer 119 is formed on the first diffusion barrier layer 118, is formed second on the first diffusion barrier layer 128 and is expanded
Dissipate barrier layer 129.
In the present embodiment, each second diffusion barrier layer can be made identical with each first diffusion barrier material, it therefore, can be with
Making the material of the first diffusion barrier layer and the second diffusion barrier layer is titanium nitride.
In the present embodiment, the second diffusion barrier layer 119 and the second diffusion barrier layer are formed using Atomic layer deposition method
129.Atomic layer deposition method has the step coverage rate close to 100%, therefore, forms the second diffusion using Atomic layer deposition method
Barrier layer can form the second diffusion resistance in homogeneous thickness on the surface of bottom portion of groove and all the first diffusion barrier layers of side wall
Barrier.
In above-mentioned ion bombardment treatment process, corresponding (argon) ion energy is usually in the knot of the first diffusion barrier layer atom
Energy or more is closed, to guarantee that migration and evolution occur for corresponding atom, and is deposited in corresponding base angle position.But this process
Surface damage can be caused to the first diffusion barrier layer simultaneously.Therefore, the present embodiment forms the second expansion on the first diffusion barrier layer
Barrier layer is dissipated, can play the role of repairing above-mentioned damage.Also, in above-mentioned ion bombardment treatment process, finally make each first
Diffusion barrier layer is located at the part of bottom portion of groove in the situation that interior thickness is uniform and two-end thickness is maximum, and middle section
Thickness can control of substantially equal (this is because in above-mentioned ion bombardment to the thickness for being located at each recessed sidewall portions with script
In treatment process, each first diffusion barrier thickness of each recessed sidewall portions is basically unchanged, and each bottom portion of groove part is each
First diffusion barrier thickness totally reduces and becomes uniform).Thus, it is subsequent to form each second using atomic layer deposition method
Diffusion barrier layer, so that final whole diffusion barrier layers be made to be located at bottom portion of groove middle position part and be located at recessed sidewall portions
Thickness it is of substantially equal, solve the problems, such as subsequent metal grid be easy to side spread, raising be formed by MOS transistor
Performance.
As it can be seen that the present embodiment by forming the second diffusion barrier layer on the first diffusion layer, make the first diffusion barrier layer and
Second diffusion barrier layer forms corresponding diffusion barrier layer together, so that being better protected from metal gates occurs metal diffusion.
In the present embodiment, the thickness range that can control the second diffusion barrier layer 119 and the second diffusion barrier layer 129 isIn each active area, corresponding second diffusion barrier layer and ion bombardment treated the first diffusion barrier layer
It is the overall thickness of diffusion barrier layer after thickness, on the one hand, need to guarantee that the overall thickness of diffusion barrier layer can prevent metal from expanding
It dissipates, on the other hand, the overall thickness of diffusion barrier layer is minimized, to be conducive to subsequent filling.
It should be noted that although not shown in the drawing, but the present embodiment it is subsequent can also after forming the second diffusion barrier layer,
Workfunction layers are formed on the second diffusion barrier layer, and form metal layer in workfunction layers, and metal layer filling is full
Groove forms corresponding metal gates, to form complete MOS transistor.In the present embodiment, the metal can be aluminium.
In forming method provided by the present embodiment, by control the first diffusion barrier layer each parameter (such as thickness join
Number), to form the first diffusion barrier layer 117 and the first diffusion barrier layer 127, also, by the first diffusion barrier layer 117
Ion bombardment processing is carried out with the first diffusion barrier layer 127, makes 127 turns of the first diffusion barrier layer 117 and the first diffusion barrier layer
The first diffusion barrier layer 118 and the first diffusion barrier layer 128 are turned to, finally by the second diffusion barrier layer 119 and second of formation
Diffusion barrier layer 129, preferably solves in metal gates, and metal is easiest to be diffused along the base angle of each groove, and holds
The problem of easily spreading along grid two sides, improves the performance of MOS transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of forming method of MOS transistor characterized by comprising
Semiconductor substrate is provided；
Pseudo- grid structure is formed on the semiconductor substrate, and dummy gate structure two sides have the bottom of sufficient shape；It is partly led described
In body substrate between dummy gate structure pericambium dielectric layer, the interlayer dielectric layer upper surface and dummy gate structure
Upper surface flushes；
For removal dummy gate structure to form groove, the groove two sides have the base angle of sufficient shape；
Boundary layer is formed in the bottom of the groove；
High-k dielectric layer is formed in the bottom and side wall of the groove, the high-k dielectric layer covers the boundary layer；
The first diffusion barrier layer is formed in the high-k dielectric layer；
Ion bombardment processing is carried out using part of the sputtering method to groove notch described in the first diffusion barrier layer face, is made
It obtains first diffusion barrier layer to be located in the part of the bottom portion of groove, interior thickness becomes uniformly, and two-end thickness increases；
After ion bombardment processing, the second diffusion barrier layer is formed on first diffusion barrier layer；Wherein, described
The forming step of one diffusion barrier layer and the ion bombardment processing step carry out in same reaction chamber.
2. the forming method of MOS transistor as described in claim 1, which is characterized in that the sputtering method uses argon ion
The ion bombardment processing is carried out to first diffusion barrier layer.
3. the forming method of MOS transistor as claimed in claim 2, which is characterized in that use physical gas-phase deposite method shape
At first diffusion barrier layer.
4. the forming method of MOS transistor as described in claim 1, which is characterized in that formed using Atomic layer deposition method
Second diffusion barrier layer.
5. the forming method of MOS transistor as described in claim 1, which is characterized in that first diffusion barrier layer and institute
It is identical to state the second diffusion barrier material.
6. the forming method of MOS transistor as described in claim 1, which is characterized in that first diffusion barrier layer and institute
The material for stating the second diffusion barrier layer is titanium nitride.
7. the forming method of MOS transistor as described in claim 1, which is characterized in that the thickness of first diffusion barrier layer
Spending range is
8. the forming method of MOS transistor as described in claim 1, which is characterized in that the thickness of second diffusion barrier layer
Spending range is
9. the forming method of MOS transistor as described in claim 1, which is characterized in that forming second diffusion barrier
After layer, further includes:
Workfunction layers are formed on second diffusion barrier layer；
Metal layer is formed in the workfunction layers, the metal layer fills the full groove.
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| US6764940B1 (en) * | 2001-03-13 | 2004-07-20 | Novellus Systems, Inc. | Method for depositing a diffusion barrier for copper interconnect applications |
| CN101558499B (en) * | 2005-06-24 | 2011-12-07 | 飞兆半导体公司 | Structure and method for forming laterally extending dielectric layer in a trench-gate fet |
| CN102386082A (en) * | 2010-08-31 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor device |
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| CN105990145A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
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| US8642424B2 (en) * | 2011-07-12 | 2014-02-04 | International Business Machines Corporation | Replacement metal gate structure and methods of manufacture |
| US9048334B2 (en) * | 2011-08-22 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure |
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| US6764940B1 (en) * | 2001-03-13 | 2004-07-20 | Novellus Systems, Inc. | Method for depositing a diffusion barrier for copper interconnect applications |
| CN101558499B (en) * | 2005-06-24 | 2011-12-07 | 飞兆半导体公司 | Structure and method for forming laterally extending dielectric layer in a trench-gate fet |
| CN102386082A (en) * | 2010-08-31 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor device |
| CN102903742A (en) * | 2011-07-25 | 2013-01-30 | 台湾积体电路制造股份有限公司 | Metal gate electrode of a field effect transistor |
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