CN106297868B - Drive the semiconductor memery device of sub- wordline - Google Patents
Drive the semiconductor memery device of sub- wordline Download PDFInfo
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- CN106297868B CN106297868B CN201510238777.6A CN201510238777A CN106297868B CN 106297868 B CN106297868 B CN 106297868B CN 201510238777 A CN201510238777 A CN 201510238777A CN 106297868 B CN106297868 B CN 106297868B
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- 238000005516 engineering process Methods 0.000 description 2
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Abstract
A kind of semiconductor memery device a, including sub-word line driver and a voltage commutation circuit.The sub-word line driver, which has, to be coupled to an input terminal of a selected main word line, is coupled to an output end, bias and the power end of a selected sub- wordline.The voltage commutation circuit supplies power supply, one second supply one of power supply and the ground voltage to the power end to select to export one first.In an aggressive mode, which exports the first supply power supply to pull up the selected sub- wordline to a logic high.In a precharge mode, which exports the ground voltage, then exports the second supply power supply to the power end, to pull down the selected sub- wordline to a logic low.
Description
Technical field
The present invention relates to a kind of semiconductor memery devices including sub-word line driver.
Background technology
Fig. 1 is painted the circuit diagram of a conventional word line driver 100.The word line driver 100 includes a main word line driver
10 and multiple sub-word line drivers 12 and 14.Each in these sub-word line drivers 12 and 14 includes a PMOS transistor P1
With a NMOS transistor N1.
These sub-word line drivers 12 and 14 are controlled by a main word line MWL.When a memory component operates on one actively
When pattern (active mode), main word line MWL can be selected as logical zero level, and a boost voltage VH can be supplied to and be somebody's turn to do
The source electrode of PMOS transistor P1.Therefore, PMOS transistor P1 can be connected and NMOS transistor N1 can end, and use raising one
Sub- wordline SWL is to 1 level of logic (VH current potentials).
When the memory component operates on a precharge mode (precharge mode), main word line MWL can be chosen
It is selected as 1 level of logic, and a ground voltage GND can be supplied to the source electrode of PMOS transistor P1.Therefore, PMOS transistor P1
It can end and NMOS transistor N1 can be connected, use and pull down the sub- wordline SWL to logical zero level.In this situation, the PMOS
It is poor to source potential that transistor P1 can undergo prodigious grid, and a grid bias induced drain leakage current (Gate Induced
Drain Leakage, GIDL) phenomenon can betide this period.When memory component operates on precharge mode or suspend mode shape
When state (standby) pattern, GIDL phenomenons can impact the semiconductor element of low-power consumption.
Invention content
A kind of semiconductor memery device according to an embodiment of the invention, including one first sub-word line driver and one
One voltage commutation circuit.First sub-word line driver, which has, to be coupled to an input terminal of a selected main word line, is coupled to
One output end of one selected sub- wordline, the reference edge and a power end for being biased into a ground voltage.The first voltage is cut
Change circuit to select output one first supply power supply, one second supply one of power supply and the ground voltage to this first
The power end of sub-word line driver.In an aggressive mode, which exports the first supply power supply extremely
Power end of first sub-word line driver, to pull up the selected sub- wordline to a logic high.In a precharge
When pattern, which exports the ground voltage to the power end of first sub-word line driver, then defeated
Go out the second supply power supply to the power end of first sub-word line driver, to pull down the selected sub- wordline to a logic
Low level.The current potential of the second supply power supply is between the current potential and the current potential of the ground voltage of the first supply power supply.
Description of the drawings
Fig. 1 is painted the circuit diagram of a conventional word line driver.
Fig. 2 shows that the square of the semiconductor memery device with sub-word line driver in conjunction with one embodiment of the invention shows
It is intended to.
Fig. 3 shows the block schematic diagram of the voltage switch unit in conjunction with one embodiment of the invention.
Fig. 4 shows a detailed circuit diagram of the voltage commutation circuit shown in Fig. 3.
Fig. 5 shows oscillogram when sub-word line driver running.
Fig. 6 shows a detailed circuit diagram of the voltage commutation circuit shown in Fig. 3.
Fig. 7 shows oscillogram when sub-word line driver running.
Fig. 8 shows the detailed circuit diagram of these sub-word line drivers shown in Fig. 2.
Fig. 9 shows the oscillogram of these sub-word line drivers and these voltage commutation circuits shown in Fig. 8.
【Accompanying drawings symbol description】
100 word line drivers
10 main word line drivers
12,14 sub-word line drivers
200 word line drivers
20 instruction decoders
21 main word line drivers
23 sub-word line drivers
24 first groups of sub-word line drivers
26 second groups of sub-word line drivers
28 voltage switch units
42,42 ', 42 " source voltage generators
422,422 ', 422 " delay circuits
424,424 ', 424 " or door
44,44 ', 44 " decoders
46,46 ', 46 " level shifters
M1-M10 transistors
M11, M11 ', M11 " transistors
M12, M12 ', M12 " transistors
MWL0, MWL1 main word line
P1 transistors
N1 transistors
SC_0-SC_7 voltage commutation circuits
SD_0-SD_15 sub-word line drivers
The sub- wordline of SWL0-SWL15
Specific implementation mode
Some vocabulary has been used in specification and following claims to censure specific element.Fields
Technical staff is, it is to be appreciated that manufacturer may call same element with different nouns.This specification and claims
Book is used as the standard of differentiation with the difference of element functionally not in such a way that the difference of title is used as and distinguishes element
Then.It is an open term in the "comprising" of specification in the whole text and subsequent claim mentioned in, therefore should be construed to
" including but not limited to ".In addition, " coupling " word includes any direct and indirect electrical connection herein.Therefore, if
One first device of described in the text is coupled to a second device, then second dress can be directly electrically connected in by representing the first device
It sets, or is electrically connected indirectly to the second device by other devices or connection means.
Fig. 2 shows that the square of the semiconductor memery device with sub-word line driver in conjunction with one embodiment of the invention shows
It is intended to.With reference to figure 2, a word line driver 200 includes an instruction decoder 20, a main word line driver 21, a sub- wordline driving
Device 23, one first group of sub-word line driver 24, one second group of sub-word line driver 26 and a voltage switch unit 28.
With reference to figure 2, which generates different output to decode an instruction CMD according to instruction CMD
As a result.For example, when instruction CMD represents aggressive mode instruction, which will produce an active signal
ACT；When instruction CMD represents precharge mode instruction, which will produce a precharging signal PRE.
The main word line driver 21 in the active mode in response to eight higher row address signal ADDR (3-10) with
Drive 128 main word lines.These main word lines include main word line MWL0 and MWL1.With reference to figure 2, main word line MWL0 correspondences are coupled to
The sub- wordline SWL0 to SWL7 of Memory Storage Unit (not drawing).Main word line MWL1 correspondences are coupled to Memory Storage Unit
The sub- wordline SWL8 to SWL15 of (not drawing).
With reference to figure 2, which includes eight sub-word line driver SD_0 to SD_7.The sub- wordline
Driver SD_0, which has, to be coupled to an input terminal of main word line MWL0, is coupled to an output end, the bias of a sub- wordline SWL0
To a reference edge of a ground voltage GND and to receive an electricity of the supply voltage SWH0 from the voltage switch unit 28
Source.Other sub-word line drivers SD_1 to SD_7 has configuration similar with sub-word line driver SD_0.
With reference to figure 2, which includes eight sub-word line driver SD_8 to SD_15.The sub- word
Line drive SD_8, which has, is coupled to an input terminal of main word line MWL1, the output end for being coupled to a sub- wordline SWL8, partially
It is depressed into a reference edge of ground voltage GND and to receive one of the supply voltage SWH0 from the voltage switch unit 28
Power end.Other sub-word line drivers SD_9 to SD_15 has configuration similar with sub-word line driver SD_8.
Fig. 3 shows the block schematic diagram of the voltage switch unit 28 in conjunction with one embodiment of the invention.With reference to figure 3, the electricity
Pressure switching unit 28 is cut comprising the multiple voltages for receiving precharging signal PRE and three relatively low row address signal ADDR (0-2)
Change circuit SC_0 to SC_7.Please also refer to Fig. 2 and Fig. 3, circuit SC_0 to provide output voltage SWDH0 to this first
The sub-word line driver in sub-word line driver SD_0 and second group of sub-word line driver 26 in group sub-word line driver 24
SD_8.Circuit SC_7 drives to provide the sub- wordline in output voltage SWDH7 to first group of sub-word line driver 24
Sub-word line driver SD_15 in device SD_7 and second group of sub-word line driver 26.These voltage commutation circuits SC_0 to SC_
7 have similar circuit configurations.
Fig. 4 shows a detailed circuit diagram of circuit SC_0 shown in Fig. 3.With reference to figure 4, circuit SC_0 includes a source electrode
Voltage generator 42, a decoder 44, a level shifter 46, a PMOS transistor M11 and a NMOS transistor M12.The solution
Code device 44 is by the relatively low row address signal ADDR (0-2) of decoding to generate a signal S1.The level shifter 46 will be will input
The low voltage potential of grade S1 is converted to high voltage potential S2.The source voltage generator 42 is applied to the NMOS crystal to generate
A bias voltage VA of pipe M12.
With reference to figure 4, which includes a delay circuit 422 and one or door 424.The delay circuit 422
To receive precharging signal PRE, and postpone mono- time intervals of precharging signal PRE.The OR circuit 44 is receiving
A postpones signal SDLY and one input signal/S1 (input signal/S1 is the inversion signal of signal S1) from the circuit 42,
To generate the bias voltage VA for being applied to NMOS transistor M12.
It is driven respectively by these sub-word line drivers SD_0 to SD_15 referring now to Fig. 2, this little wordline SWL0 to SWL15
It is dynamic.Each in these sub-word line drivers SD_0 to SD_15 is by one of them defeated of these main word lines MWL0 and MWL1
Go out signal and one of them is controlled from multiple secondary main word line enable signal SE0 to SE7 in the sub-word line driver 23
System.In an embodiment of the present invention, when the aggressive mode operates, the main word line driver 21 is according to higher row address signal
ADDR (3-10) selects driving main word line MWL0 first, and the sub-word line driver 23 is according to relatively low row address signal ADDR
(0-2) selection first drives the sub- wordline SWL0.Illustrate the son below with reference to the circuit diagram of the oscillogram of Fig. 5 and the Fig. 2 and Fig. 4
The function mode of word line driver SD_0.
Referring now to Fig. 5, in time t0, which operates in aggressive mode.Therefore, precharging signal PRE
Will not enable and be located at logical zero level.The decoder 44 signal S1 of the generation with logical zero level, and the level shifter 46
Generate the drive signal S2 with GND current potentials.Therefore, NMOS transistor M12 ends and PMOS transistor M11 conductings.According to
This mode, circuit SC_0 supplies one supply voltage VH to sub-word line driver SD_0 are patrolled with pulling up the sub- wordline SWL0 to one
Collect 1 level.
As shown in figure 5, in time t1, which enters precharge mode.Therefore, all main word lines all will not
It is driven and falls within 1 level of logic.Precharging signal PRE understands enable and is located at 1 level of logic.Receiving being somebody's turn to do from Fig. 2
After the precharging signal PRE of instruction decoder 20, the delay circuit 422 of Fig. 4 postpones mono- time intervals of precharging signal PRE
td.In the present embodiment, time interval td is that a memory bank is precharged to memory bank active time interval (bank
precharge to bank active time interval,tRP).After time interval td, postpones signal SDLY can turn
State is to 1 level of logic.Therefore, the current potential of the bias voltage VA generated by the source voltage generator 42 can be quickly by being grounded
Voltage GND goes to supply voltage VCC.
With reference to figure 4 and Fig. 5, in precharge mode, which exports the driving that current potential is supply voltage VH
Signal S2 makes NMOS transistor M12 be connected and PMOS transistor M11 is made to end, and therefore, circuit SC_0 is for that should be biased
Voltage VA to sub-word line driver SD_0.By the current potential changed supplied to the bias voltage VA of transistor M12, the circuit
SC_0 supplies ground voltage GND as a driving voltage to sub-word line driver SD_0 before time t2.Circuit SC_0 exists
Supply voltage VCC is supplied after time t2 as a driving voltage to sub-word line driver SD_0.
In the present embodiment, the current potential of supply voltage VCC is less than the current potential of supply voltage VH, and the supply voltage
The current potential of VCC is higher than the current potential of ground voltage GND.As described above, after the memory component enters precharge mode, the electricity
Road SC_0 supplies the lower driving voltage of current potential to sub-word line driver SD_0, then supplies the higher driving voltage of current potential extremely
Sub-word line driver SD_0, therefore increase the decrease speed of the sub- wordline SWL0.After time t 2, circuit SC_0 is kept defeated
Go out the current potential that voltage is supply voltage VCC.In this way, since the PMOS transistor M1 in sub-word line driver SD_0 exists
State is off in precharge mode, GIDL electric currents can be reduced effectively.
Fig. 4 and Fig. 5 is shown in active mode if the son of main word line MWL0 and sub- wordline SWL0 selections when being driven
The circuit diagram and oscillogram of word line driver SD_0 and voltage commutation circuit SC_0.Referring now to Fig. 2, which is driven
For device SD_7, corresponding main word line MWL0, which has, to be selected, and the sub- not selected drivings of wordline SWL7.With this condition, in Fig. 3
The voltage switch unit 28 in circuit SC_7 one output voltage SWDH7 to sub-word line driver SD_7 is provided.Join below
The circuit diagram of the oscillogram and the Fig. 2 and Fig. 6 of examining Fig. 7 illustrates the function mode of sub-word line driver SD_7.
In time t0, which operates in aggressive mode.Therefore, precharging signal PRE will not enable and
Positioned at logical zero level.The decoder 44 ' generates the signal S1 ' with 1 level of logic by decoding row address signal ADDR,
So that NMOS transistor M12 ' is connected and PMOS transistor M11 ' is allowed to end.Therefore, circuit SC_7 supplies power supply electricity
Press VA ' to sub-word line driver SD_0.In the active mode, which, which generates, has ground voltage GND
Current potential bias voltage VA '.
In time t1, which enters precharge mode.Therefore, all main word lines will not all be driven and be fallen
In 1 level of logic.Precharging signal PRE understands enable and is located at 1 level of logic.Receiving the instruction decoder from Fig. 2
After 20 precharging signal PRE, the delay circuit 422 ' of Fig. 4 postpones mono- time interval td of precharging signal PRE.At this
Between after the td of interval, postpones signal SDLY ' can transition to 1 level of logic.Therefore, it is somebody's turn to do by what the source voltage generator 42 ' generated
The current potential of bias voltage VA ' can be quickly supply voltage VCC is gone to by ground voltage GND.
In addition, in precharge mode, these master of the sub-word line driver 23 output with 1 level of logic of Fig. 2
Wordline enable signal SE0 to SE7 pulls down corresponding sub- wordline to the current potential of ground voltage GND.When the memory component is by pre-
When charge mode enters aggressive mode, these secondary main word line enable signal SE1 to SE7 keep 1 level of logic, and secondary main word line causes
Energy signal SE0 can be pulled down to the current potential of ground voltage GND before sub- wordline SWL0 enables.
Referring to figure 6 and figure 7, in precharge mode, driving of the level shifter 46 ' output with 1 level of logic is believed
Number S2 ' allows NMOS transistor M12 ' to be connected and PMOS transistor M11 ' is made to end, and therefore, circuit SC_7 is for should
Bias voltage VA ' to sub-word line driver SD_7.The current potential of bias voltage VA ' maintains the supply voltage after time t 2
VCC.Therefore, transistor M3 generated GIDL electric currents in precharge mode can thereby bias fashion decline.
As described above, Fig. 4 to Fig. 7 is shown in active mode if this little wordline when main word line MWL0 is selected is driven
The circuit diagram and oscillogram of dynamic device SD_0, SD_7 and these voltage commutation circuits SC_0, SC_7.Referring now to Fig. 2, of the invention another
In one embodiment, another at this time not selected driving of main word line MWL1.Since the voltage switch unit 28 is according to lower rows
Address signal ADDR (0-2), rather than power supply is supplied to sub-word line driver according to higher row address signal ADDR (3-10).
The supply voltage SWDH0 that the supply voltage SWDH0 of sub-word line driver SD_8 is sub-word line driver SD_0, and the sub- word
The supply voltage SWDH7 that the supply voltage SWDH7 of line drive SD_15 is sub-word line driver SD_7.
Fig. 8 shows the detailed circuit diagram of these sub-word line drivers SD_8 to SD_15 shown in Fig. 2.This little wordline is driven
Dynamic device SD_8 to SD_15 receives the supply voltage SWDH0 to SWDH7 from the voltage switch unit 28 respectively.Fig. 9 shows Fig. 8
Shown in these sub-word line drivers SD_8 and SD_15 and these voltage commutation circuits SC_0 and SC_7 oscillogram.The main word
Line MWL1 is not selected in figs. 8 and 9.
With reference to figure 8 and Fig. 9, for the PMOS transistor M6 in sub-word line driver SD_8, time t2 and when
Between between t3, source bias is in the current potential of supply voltage VCC, and its grid bias is in the current potential of supply voltage VH.Therefore
This period GIDL electric currents of PMOS transistor M6 can reduce.To the PMOS transistor M9 in sub-word line driver SD_15
For, between time t2 and time t3, source bias is in the current potential of the supply voltage VCC, and its grid bias is in the power supply
The current potential of voltage VH.Therefore the GIDL electric currents of this period PMOS transistor M9 can reduce.
The technology contents and technical characterstic of the present invention have been disclosed as above, however those skilled in the art are still potentially based on this hair
Bright teaching and open and make various replacements and modification without departing substantially from spirit of that invention.Therefore, protection scope of the present invention should not
It is limited to embodiment disclosure of that, and should includes various replacements and modification without departing substantially from the present invention, and is the right of the present invention
Claim is covered.
Claims (10)
1. a kind of semiconductor memery device, including：
One first sub-word line driver has and is coupled to that an input terminal of a selected main word line, to be coupled to one selected
One output end of sub- wordline, the reference edge and a power end for being biased into a ground voltage；And
One first voltage switching circuit, to select one first supply power supply of output, one second supply power supply and the ground voltage
One of to first sub-word line driver the power end；
Wherein, in an aggressive mode, which exports the first supply power supply to the first sub- wordline and drives
Power end of dynamic device, to pull up the selected sub- wordline to a logic high；
Wherein, in a precharge mode, which exports the ground voltage to the first sub- wordline driving
The power end of device then exports the second supply power supply to the power end of first sub-word line driver, to pull down the institute
The sub- wordline of selection is to a logic low；With
Wherein, the current potential of the second supply power supply is between the current potential and the current potential of the ground voltage of the first supply power supply.
2. semiconductor memery device according to claim 1, wherein first sub-word line driver include：
One PMOS transistor couples the power end of first sub-word line driver in the aggressive mode to the selected son
Wordline；And
One NMOS transistor, the power end that first sub-word line driver is coupled in the precharge mode are electric to the ground connection
Pressure.
3. semiconductor memery device according to claim 1, further includes：
One second sub-word line driver has and is coupled to that an input terminal of the selected main word line, to be coupled to one first unselected
One output end of the sub- wordline selected, the reference edge and a power end for being biased into the ground voltage；And
One second voltage switching circuit, to select to export the first supply power supply, the second supply power supply and the ground voltage
One of to second sub-word line driver the power end；
Wherein, in the aggressive mode, which exports the ground voltage to second sub-word line driver
The power end；With
Wherein, in the precharge mode, which exports the ground voltage to the second sub- wordline driving
The power end of device then exports the second supply power supply to the power end of second sub-word line driver.
4. semiconductor memery device according to claim 3, wherein second sub-word line driver include：
It is first non-selected to this to couple the power end of second sub-word line driver in the aggressive mode for one PMOS transistor
Sub- wordline；And
One NMOS transistor couples the first non-selected sub- wordline in the precharge mode to the ground voltage.
5. semiconductor memery device according to claim 1, further includes：
One third sub-word line driver has and is coupled to that an input terminal of a non-selected main word line, to be coupled to one second unselected
One output end of the sub- wordline selected, the reference edge and a power end for being biased into the ground voltage；
Wherein, in the aggressive mode, which exports the first supply power supply to the sub- wordline of the third and drives
The power end of dynamic device；With
Wherein, in the precharge mode, which exports the ground voltage to the sub- wordline driving of the third
The power end of device then exports the second supply power supply to the power end of the third sub-word line driver.
6. semiconductor memery device according to claim 5, wherein the third sub-word line driver include：
One first NMOS transistor couples the second non-selected sub- wordline in the aggressive mode to the ground voltage；And
One second NMOS transistor couples the second non-selected sub- wordline in the precharge mode to the ground voltage.
7. semiconductor memery device according to claim 3, further includes：
One the 4th sub-word line driver has and is coupled to that an input terminal of the non-selected main word line, to be coupled to a third unselected
One output end of the sub- wordline selected, the reference edge and a power end for being biased into the ground voltage；
Wherein, in the aggressive mode, which exports the ground voltage to the 4th sub-word line driver
The power end；With
Wherein, in the precharge mode, which exports the ground voltage to the 4th sub- wordline driving
The power end of device then exports the power end of the second supply power supply to the 4th sub-word line driver.
8. semiconductor memery device according to claim 7, wherein the 4th sub-word line driver include：
One third NMOS transistor couples the non-selected sub- wordline of the third in the aggressive mode to the ground voltage；And
One the 4th NMOS transistor couples the non-selected sub- wordline of the third in the precharge mode to the ground voltage.
9. semiconductor memery device according to claim 1, wherein the first voltage switching circuit include：
One delay circuit, to generate one the when the semiconductor memery device enters the precharge mode by the aggressive mode
One time interval；
One PMOS transistor couples the first supply power supply in the aggressive mode to the power supply of first sub-word line driver
End；And
One NMOS transistor couples the ground voltage to the first sub- word in the precharge mode in the first time interval
The power end of line drive, and one second time interval after the first time interval couple the second supply power supply to should
The power end of first sub-word line driver.
10. semiconductor memery device according to claim 3, wherein the second voltage switching circuit include：
One delay circuit, to generate one the when the semiconductor memery device enters the precharge mode by the aggressive mode
One time interval；And
One NMOS transistor, the ground voltage is coupled in the aggressive mode to the power end of second sub-word line driver,
The ground voltage is coupled to the power supply of second sub-word line driver in the first time interval in the precharge mode
It holds, and one second time interval after the first time interval couples the second supply power supply to second sub-word line driver
The power end.
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| CN201510238777.6A CN106297868B (en) | 2015-05-12 | 2015-05-12 | Drive the semiconductor memery device of sub- wordline |
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| CN112349320B (en) * | 2019-08-06 | 2024-08-23 | 长鑫存储技术有限公司 | Word line driving circuit and memory cell |
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| KR100630346B1 (en) * | 2005-07-05 | 2006-10-02 | 삼성전자주식회사 | Circuit and method for driving word line by charge sharing on reading mode |
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|---|---|---|---|---|
| US6067257A (en) * | 1998-03-16 | 2000-05-23 | Hitachi, Ltd. | Semiconductor integrated circuit device having step-down voltage circuit |
| CN1838308A (en) * | 2005-02-02 | 2006-09-27 | 英飞凌科技股份公司 | Method and device for varying an active duty cycle of a wordline |
| CN1892913A (en) * | 2005-07-05 | 2007-01-10 | 三星电子株式会社 | Circuit and method of driving a word line of a memory device |
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