CN106297715A - The GOA circuit of a kind of three rank drivings and liquid crystal display - Google Patents
The GOA circuit of a kind of three rank drivings and liquid crystal display Download PDFInfo
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- CN106297715A CN106297715A CN201610875013.2A CN201610875013A CN106297715A CN 106297715 A CN106297715 A CN 106297715A CN 201610875013 A CN201610875013 A CN 201610875013A CN 106297715 A CN106297715 A CN 106297715A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 24
- 238000012423 maintenance Methods 0.000 claims abstract description 30
- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims description 139
- 230000005611 electricity Effects 0.000 claims description 7
- 239000010408 film Substances 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 3
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 3
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000010408 sweeping Methods 0.000 description 3
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 2
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The GOA circuit of the three rank drivings that the present invention provides and liquid crystal display, it includes multiple GOA unit of cascade, and n-th grade of GOA unit includes: signal source of clock, constant voltage low level source, pull-up control module, pull-up module, lower transmission module, drop-down module, drop-down maintenance module and bootstrap capacitor；The GOA circuit of the three rank drivings of the present invention and liquid crystal display, be integrated in GOA circuit on array base palte, advantageously reduce the production cost of display panels and realize narrow frame；Use the mode that three rank drive, in the scan line down periods, by clock signal, scanning signal is placed in the first high level and the first low level, by constant voltage low level source, scanning signal is placed in the second low level again, such that it is able to effectively solve the impact on display panels of the feed-trough voltage that produces because of parasitic capacitance, improve display quality.
Description
Technical field
The present invention relates to display panels field, particularly relate to GOA circuit and liquid crystal display that a kind of three rank drive.
Background technology
The development of existing liquid crystal indicator presents the development trend of narrow frame, slimming and low cost, Qi Zhongyi
The important technology of item is GOA (Gate Driver On Array, array base palte row cutting) technology.Will scanning by GOA technology
Line drive circuit is integrated on the array base palte of display panels, thus reduces in material cost and processing technology two aspect
Product cost.
And existing GOA circuit typically uses second order drive circuit, and by adjusting the voltage on public electrode, to support
Disappear because of the feed-trough voltage impact on display panels produced by parasitic capacitance.But by adjusting the voltage on public electrode
It is difficult to reach improving the purpose of the quality of display panels.
Therefore, it is necessary to provide GOA circuit and the liquid crystal display of a kind of three rank drivings, to solve asking of prior art existence
Topic.
Summary of the invention
It is an object of the invention to provide GOA circuit and liquid crystal display that a kind of three rank drive, advantageously reduce liquid crystal
The production cost of display floater and realize narrow frame, is applied GOA technology simultaneously on three rank drive, is driven by three rank
GOA circuit can effectively eliminate the feed-trough voltage impact on display panels produced because of parasitic capacitance, improves display quality.
For solving the problems referred to above, the technical scheme that the present invention provides is as follows:
The present invention provides the GOA circuit that a kind of three rank drive, and for liquid crystal display, the GOA circuit that three rank drive includes
Multiple GOA unit of cascade, wherein, n-th grade of GOA unit includes:
Signal source of clock, for providing the clock signal of this grade, clock signal includes the first high level and the first low electricity
Flat；
Constant voltage low level source, for providing the second low level；
Pull-up control module is for receiving the scanning signal of (n-1)th grade and raw by the control of the level number of delivering a letter of (n-1)th grade
The scanning level signal of cost level；
Pull-up module, for being scanned controlling of level signal by this grade, by the first high level of the clock signal of this grade
And first low level output to this grade scanning signal outfan；
Lower transmission module, for receiving the clock signal of this grade, and is scanned the control generation n-th+2 of level signal by this grade
The level number of delivering a letter of level；
Drop-down module, is used for the scanning signal according to the n-th+2 grades, the second low level output provided in constant voltage low level source
Outfan to the scanning signal of this grade；
Drop-down maintenance module, the second low electricity scanning signal of scanning level signal and this grade for maintaining this grade
Flat；And
Bootstrap capacitor, for generating the high level of the scanning level signal of this grade；
The outfan of pull-up control module and pull-up module, lower transmission module, drop-down module, drop-down maintenance module and bootstrapping
Electric capacity connects；Constant voltage low level source is connected with drop-down maintenance module and drop-down module；Signal source of clock with pull-up module and
Lower transmission module connects.
In the GOA circuit that three rank of the present invention drive, pull-up module includes the 21st thin film transistor (TFT), the 21st
The grid of thin film transistor (TFT) is electrically connected at the outfan of pull-up control module, and source electrode accesses the clock signal of this grade, drain electrode electricity
Property be connected to this grade scanning signal outfan.
In the GOA circuit that three rank of the present invention drive, drop-down module includes the 31st thin film transistor (TFT) and the 40th
One thin film transistor (TFT)；
The grid of the 31st thin film transistor (TFT) is electrically connected at the scanning signal output part of the n-th+2 grades, and source electrode electrically connects
Being connected to constant voltage low level source, drain electrode is electrically connected at the outfan of the scanning signal of this grade；
The grid of the 41st thin film transistor (TFT) is electrically connected at the scanning signal output part of the n-th+2 grades, and source electrode electrically connects
Being connected to constant voltage low level source, drain electrode is electrically connected at the outfan of pull-up control module.
In the GOA circuit that three rank of the present invention drive, the first low level is less than the second low level.
In the GOA circuit that three rank of the present invention drive, pull-up control module includes the 11st thin film transistor (TFT), the 11st
The grid of thin film transistor (TFT) is electrically connected at the level of (n-1)th grade and passes signal output part, and source electrode is electrically connected at the scanning of (n-1)th grade
Signal output part, drain electrode is electrically connected at the outfan of pull-up control module.
In the GOA circuit that three rank of the present invention drive, lower transmission module includes the 22nd thin film transistor (TFT), the 22nd
The grid of thin film transistor (TFT) is electrically connected at the outfan of pull-up control module, and source electrode accesses the clock signal of this grade, drain electrode electricity
Property is connected to the outfan of the level number of delivering a letter of the n-th+2 grades.
In the GOA circuit that three rank of the present invention drive, drop-down maintenance module includes the first drop-down maintenance unit and the
Two drop-down maintenance units；
First drop-down maintenance unit includes the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 53rd thin
Film transistor, the 54th thin film transistor (TFT), the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；
Grid and the drain electrode of the 51st thin film transistor (TFT) access the first square-wave signal, and source electrode is electrically connected at the 50th
The drain electrode of two thin film transistor (TFT)s and the grid of the 53rd thin film transistor (TFT)；
The grid of the 52nd thin film transistor (TFT) is electrically connected at the outfan of pull-up control module, and source electrode is electrically connected at
Constant voltage low level source；
The source electrode of the 53rd thin film transistor (TFT) accesses the first square-wave signal, and it is brilliant that drain electrode is electrically connected at the 54th thin film
The drain electrode of body pipe, the grid of the 42nd thin film transistor (TFT) and the grid of the 32nd thin film transistor (TFT)；
The grid of the 54th thin film transistor (TFT) is electrically connected at the outfan of pull-up control module, and source electrode is electrically connected at
Constant voltage low level source；
The source electrode of the 42nd thin film transistor (TFT) is electrically connected at constant voltage low level source, and drain electrode is electrically connected at pull-up control
The outfan of module；
The source electrode of the 32nd thin film transistor (TFT) is electrically connected at constant voltage low level source, and drain electrode is electrically connected at sweeping of this grade
Retouch the outfan of signal；
Second drop-down maintenance unit includes the 61st thin film transistor (TFT), the 62nd thin film transistor (TFT), the 63rd thin
Film transistor, the 64th thin film transistor (TFT), the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)；
Grid and the drain electrode of the 61st thin film transistor (TFT) access the second square-wave signal, and source electrode is electrically connected at the 60th
The drain electrode of two thin film transistor (TFT)s and the grid of the 63rd thin film transistor (TFT)；
The grid of the 62nd thin film transistor (TFT) is electrically connected at the outfan of pull-up control module, and source electrode is electrically connected at
Constant voltage low level source；
The source electrode of the 63rd thin film transistor (TFT) accesses the second square-wave signal, and it is brilliant that drain electrode is electrically connected at the 64th thin film
The drain electrode of body pipe, the grid of the 43rd thin film transistor (TFT) and the grid of the 33rd thin film transistor (TFT)；
The grid of the 64th thin film transistor (TFT) is electrically connected at the outfan of pull-up control module, and source electrode is electrically connected at
Constant voltage low level source；
The source electrode of the 43rd thin film transistor (TFT) is electrically connected at constant voltage low level source, and drain electrode is electrically connected at pull-up control
The outfan of module；
The source electrode of the 33rd thin film transistor (TFT) is electrically connected at constant voltage low level source, and drain electrode is electrically connected at sweeping of this grade
Retouch the outfan of signal.
In the GOA circuit that three rank of the present invention drive, the first square-wave signal and the second square-wave signal are dutycycle and are
The square wave of 1/2,1/2 cycle of phase.
The present invention three rank drive GOA circuit in, bootstrap capacitor be arranged on pull-up control module outfan and
Between the outfan of the scanning signal of this grade.
The present invention also provides for a kind of liquid crystal display, the GOA circuit driven including three above-mentioned rank.
The GOA circuit of the three rank drivings of the present invention and liquid crystal display, be integrated in GOA circuit on array base palte, favorably
In reducing the production cost of display panels and realizing narrow frame；Meanwhile, use the mode that three rank drive, close in scan line
Period, by clock signal, scanning signal is placed in the first high level and the first low level, then will by constant voltage low level source
Scanning signal is placed in the second low level, such that it is able to effectively solve because the feed-trough voltage of parasitic capacitance generation is to display panels
Impact, improve display quality.
For the foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, make
Describe in detail as follows:
Accompanying drawing explanation
Below in conjunction with the accompanying drawings, by the detailed description of the invention of the present invention is described in detail, technical scheme will be made
And other beneficial effect is apparent.
Fig. 1 is the structural representation of the preferred embodiment of the GOA circuit of the three rank drivings of the present invention；
Fig. 2 is the structural representation of the GOA unit of the preferred embodiment of the GOA circuit of the three rank drivings of the present invention；
Fig. 3 is the circuit diagram of the GOA unit of the preferred embodiment of the GOA circuit of the three rank drivings of the present invention；
Fig. 4 is the signal waveforms of the preferred embodiment of the GOA circuit of the three rank drivings of the present invention；
Fig. 5 is the structural representation of the liquid crystal display of the present invention.
Detailed description of the invention
By further illustrating the technological means and effect, being preferable to carry out below in conjunction with the present invention that the present invention taked
Example and accompanying drawing thereof are described in detail.
Refering to Fig. 1, Fig. 4, Fig. 1 is the structural representation of the preferred embodiment of the GOA circuit of the three rank drivings of the present invention；Figure
4 is the signal waveforms of the preferred embodiment of the GOA circuit of the three rank drivings of the present invention；
As it is shown in figure 1, the GOA circuit that three rank of this preferred embodiment drive, for liquid crystal display, it includes cascade
Multiple GOA unit, every one-level GOA unit accesses corresponding clock signal.As shown in Figure 4, three rank of this preferred embodiment drive
GOA circuit be provided with 4 clock signals: the first clock signal clk 1, second clock signal CLK2, the 3rd clock signal clk 3 with
And the 4th clock signal clk, each clock signal all includes the first high level VGH and the first low level VGL, wherein, first
Clock signal clk 1 accesses the 1st, 5,9 ... (4k+1) level GOA unit；Second clock signal CLK2 accesses the 2nd, 6,10 ...
(4k+2) level GOA unit；3rd clock signal clk 3 accesses the 3rd, 7,11 ... (4k+3) level GOA unit；4th clock signal
CLK4 accesses the 4th, 8,12 ... (4k+4) level GOA unit, k is integer.
Specifically, the first clock signal clk 1, second clock signal CLK2, the 3rd clock signal clk 3 and the 4th clock
Signal CLK4 is the square-wave signal that dutycycle is 1/4, and time delay 1/4 cycle successively.
The structure of GOA unit of preferred embodiment refering to the GOA circuit of the three rank drive circuits that Fig. 2, Fig. 2 are the present invention
Schematic diagram；
As in figure 2 it is shown, n-th grade of GOA unit access corresponding clock signal clk, (n-1)th grade scanning signal G (n-1) with
And the level number of delivering a letter ST (n-1) of (n-1)th grade, generate scanning signal G (n) of this grade and the level number of the delivering a letter ST (n+ of the n-th+2 grades
2) level of this grade of scanning signal G (n), and is dragged down by the control of scanning signal G (n+2) of the n-th+2. grades.
The circuit diagram of GOA unit refering to the preferred embodiment of Fig. 3, Fig. 3 are the present invention GOA circuit that three rank drive；
As it is shown on figure 3, the GOA circuit that three rank of the present invention drive includes the GOA unit of cascade, wherein, n-th grade of GOA is mono-
Unit includes: signal source of clock CLK, constant voltage low level source M, pull-up control module 101, pull-up module 102, lower transmission module 103, under
Drawing-die block 104, drop-down maintenance module 105 and bootstrap capacitor Cb；Pull-up control module 101 outfan with pull-up module 102,
Lower transmission module 103, drop-down module 104, drop-down maintenance module 105 and bootstrap capacitor Cb connect；Constant voltage low level source M is with drop-down
Module 105 and drop-down module 104 is maintained to connect；Signal source of clock is connected with pull-up module and lower transmission module.
Wherein, signal source of clock CLK, for providing the clock signal of this grade, clock signal include the first high level and
First level；Constant voltage low level source M, for providing the second low level；Pull-up control module 101, for sweeping of reception (n-1)th grade
Retouch signal G (n-1), and scanning level signal Q (n) controlling this grade of generation of the level number of delivering a letter ST (n-1) by (n-1)th grade；On
Drawing-die block 102, for the control of scanning level signal Q (n) by this grade, by the first high level of the clock signal of this grade and
First low level output is to the outfan of scanning signal G (n) of this grade；Lower transmission module, for receiving the clock signal of this grade, and
The level number of delivering a letter ST (n+2) controlling generation the n-th+2 grades by scanning level signal Q (n) of this grade；Drop-down module 104, for root
According to scanning signal G (n+2) of the n-th+2 grades, the scanning signal of the second low level output that constant voltage low level source M is provided to this grade
The outfan of G (n)；Drop-down maintenance module 105, for maintaining scanning level signal Q (n) of this grade and the scanning signal of this grade
The low level of G (n)；And bootstrap capacitor Cb, for generating the high level of scanning level signal Q (n) of this grade.
Pull-up control module 101 includes the 11st thin film transistor (TFT) T11, and the grid of the 11st thin film transistor (TFT) T11 is electrical
Being connected to the level number of delivering a letter ST (n-1) outfan of (n-1)th grade, scanning signal G (n-1) that source electrode is electrically connected with (n-1)th grade is defeated
Going out end, drain electrode is electrically connected with and the outfan of pull-up control module 101.
Pull-up module 102 includes the 21st thin film transistor (TFT) T21, and the grid of the 21st thin film transistor (TFT) T21 is electrical
Connecting and the outfan of pull-up control module 101, source electrode accesses the clock signal of this grade, and drain electrode is electrically connected at the scanning of this grade
The outfan of signal G (n).
Lower transmission module 103 includes the 22nd thin film transistor (TFT) T22, and the grid of the 22nd thin film transistor (TFT) T22 is electrical
Being connected to pull up the outfan of control module 101, source electrode accesses the clock signal of this grade, and drain electrode is electrically connected at the n-th+2 grades
The outfan of the level number of delivering a letter ST (n+2).
Drop-down module 104 includes the 31st thin film transistor (TFT) T31 and the 41st thin film transistor (TFT) T41；
The grid of the 31st thin film transistor (TFT) T31 is electrically connected at the outfan of scanning signal G (n+2) of the n-th+2 grades,
Source electrode is electrically connected at constant voltage low level source M, and drain electrode is electrically connected at the outfan of scanning signal G (n) of this grade；
The grid of the 41st thin film transistor (TFT) T41 is electrically connected at the outfan of scanning signal G (n+2) of the n-th+2 grades,
Source electrode is electrically connected at constant voltage low level source M, and drain electrode is electrically connected at the outfan of pull-up control module 101.
Drop-down maintenance module 105 includes the first drop-down maintenance unit 1051 and the second drop-down maintenance unit 1052；
First drop-down maintenance unit 1051 include the 51st thin film transistor (TFT) T51, the 52nd thin film transistor (TFT) T52,
53rd thin film transistor (TFT) T53, the 54th thin film transistor (TFT) T54, the 42nd thin film transistor (TFT) T42 and the 32nd
Thin film transistor (TFT) T32；
Grid and the drain electrode of the 51st thin film transistor (TFT) T51 access the first square-wave signal LC1, and source electrode is electrically connected at
The drain electrode of the 52nd thin film transistor (TFT) T52 and the grid of the 53rd thin film transistor (TFT) T53；
The grid of the 52nd thin film transistor (TFT) T52 is electrically connected at the outfan of pull-up control module 101, and source electrode is electrical
It is connected to constant voltage low level source M；
The source electrode of the 53rd thin film transistor (TFT) T53 accesses the first square-wave signal LC1, and drain electrode is electrically connected at the 54th
The drain electrode of thin film transistor (TFT) T54, the grid of the 42nd thin film transistor (TFT) T42 and the grid of the 32nd thin film transistor (TFT) T32
Pole；
The grid of the 54th thin film transistor (TFT) T54 is electrically connected at the outfan of pull-up control module 101, and source electrode is electrical
It is connected to constant voltage low level source M；
The source electrode of the 42nd thin film transistor (TFT) T42 is electrically connected at constant voltage low level source M, and drain electrode is electrically connected at pull-up
The outfan of control module 101；
The source electrode of the 32nd thin film transistor (TFT) T32 is electrically connected at constant voltage low level source M, and drain electrode is electrically connected at this level
The outfan of scanning signal G (n)；
Second drop-down maintenance unit 1052 include the 61st thin film transistor (TFT) T61, the 62nd thin film transistor (TFT) T62,
63rd thin film transistor (TFT) T63, the 64th thin film transistor (TFT) T64, the 43rd thin film transistor (TFT) T43 and the 33rd
Thin film transistor (TFT) T33；
Grid and the drain electrode of the 61st thin film transistor (TFT) T61 access the second square-wave signal LC2, and source electrode is electrically connected at
The drain electrode of the 62nd thin film transistor (TFT) T62 and the grid of the 63rd thin film transistor (TFT) T63；
The grid of the 62nd thin film transistor (TFT) T62 is electrically connected at the outfan of pull-up control module 101, and source electrode is electrical
It is connected to constant voltage low level source M；
The source electrode of the 63rd thin film transistor (TFT) T63 accesses the second square-wave signal LC2, and drain electrode is electrically connected at the 64th
The drain electrode of thin film transistor (TFT) T64, the grid of the 43rd thin film transistor (TFT) T43 and the grid of the 33rd thin film transistor (TFT) T33
Pole；
The grid of the 64th thin film transistor (TFT) T64 is electrically connected at the outfan of pull-up control module 101, and source electrode is electrical
It is connected to constant voltage low level source M；
The source electrode of the 43rd thin film transistor (TFT) T43 is electrically connected at constant voltage low level source M, and drain electrode is electrically connected at pull-up
The outfan of control module 101；
The source electrode of the 33rd thin film transistor (TFT) T33 is electrically connected at constant voltage low level source M, and drain electrode is electrically connected at this level
The outfan of scanning signal G (n).
First square-wave signal LC1 and the second square-wave signal LC2 is the square wave that dutycycle is 1/2,1/2 week of phase
Phase, the first drop-down maintenance unit and the second drop-down maintenance unit alternation so that whole circuit is more stable.
Bootstrap capacitor Cb is arranged on the outfan of pull-up control module 101 and the outfan of scanning signal G (n) of this grade
Between.
Refering to Fig. 3, Fig. 4, Fig. 4 is the signal waveforms of the preferred embodiment of the GOA circuit of the three rank drivings of the present invention；
When the GOA circuit that three rank of this preferred embodiment drive uses, enabling signal STV start scan drive circuit,
When the level number of delivering a letter ST (n-1) of (n-1)th grade is high level, the 11st thin film transistor (TFT) T11 conducting, the scanning letter of (n-1)th grade
The high level of number G (n-1) is charged to bootstrap capacitor Cb by the 11st thin film transistor (TFT) T11 so that reference point Q (n) rises to
One higher level.The level number of delivering a letter ST (n-1) of (n-1)th grade transfers low level to subsequently, and the 11st thin film transistor (TFT) T11 disconnects,
Reference point Q (n) maintains a higher level, and the 21st thin film transistor (TFT) T21 and the 22nd by bootstrap capacitor Cb
Thin film transistor (TFT) T22 turns on.
The clock signal of this grade transfers high level to subsequently, clock signal by the 21st thin film transistor (TFT) T21 continue to
Bootstrap capacitor Cb charges so that reference point Q (n) reaches a higher level, scanning signal G (n) of this grade and the n-th+2 grades
The level number of delivering a letter ST (n+2) also transfers the first high level VGH to.
Then, the clock signal of this grade transfers the first low level VGL to, and clock signal passes through the 21st thin film transistor (TFT)
The level of scanning signal G (n) of this grade is placed in the first low level VGL by T21.
When scanning signal G (n+2) of the n-th+2 grades is high level, the 31st thin film transistor (TFT) T31 and the 41st
Thin film transistor (TFT) T41 turns on, and the level of scanning signal G (n) of this grade is placed in the second low level Vss by constant voltage low level source M, the
One low level VGL is less than the second low level Vss, thus makes up the feed-trough voltage produced because of parasitic capacitance.
Finally, by the drop-down maintenance unit of first in drop-down maintenance module 105 1051 and the second drop-down maintenance unit
The alternating action of 1052, it is ensured that the electronegative potential of reference point Q (n), the scanning signal G to this grade being in the second low level Vss
N () serves maintenance effect.
GOA circuit is integrated on array base palte by the GOA circuit that three rank of this preferred embodiment drive, and advantageously reduces liquid
The production cost of LCD panel and realize narrow frame；Meanwhile, use the mode that three rank drive, in the scan line down periods, logical
Scanning signal is placed in the first high level and the first low level by oversampling clock signal, then will scan signal by constant voltage low level source
It is placed in the second low level, such that it is able to effectively solve the impact on display panels of the feed-trough voltage that produces because of parasitic capacitance,
Improve display quality.
The present invention further provides a kind of liquid crystal display, the GOA circuit driven including three above-mentioned rank, join the most further
Read the structural representation of the liquid crystal display that Fig. 5, Fig. 5 are the present invention.
In the preferred embodiment, liquid crystal display includes liquid crystal panel 1 and three rank being arranged on liquid crystal panel 1 side are driven
Dynamic GOA circuit 2, the structure of GOA circuit 2 and operation principle can refer to being preferable to carry out of the GOA circuit of above-mentioned three rank drivings
Example, does not repeats at this.
GOA circuit is integrated on array base palte by the liquid crystal display of this preferred embodiment, advantageously reduces liquid crystal display
The production cost of panel and realize narrow frame；Meanwhile, the mode using three rank to drive, in the scan line down periods, pass through clock
Scanning signal is placed in the first high level and the first low level by signal, then by constant voltage low level source, scanning signal is placed in
Two low levels, such that it is able to effectively solve the impact on display panels of the feed-trough voltage that produces because of parasitic capacitance, improve aobvious
Show quality.
The GOA circuit of the three rank drivings of the present invention and liquid crystal display, be integrated in GOA circuit on array base palte, favorably
In reducing the production cost of display panels and realizing narrow frame；Meanwhile, use the mode that three rank drive, close in scan line
Period, by clock signal, scanning signal is placed in the first high level and the first low level, then will by constant voltage low level source
Scanning signal is placed in the second low level, such that it is able to effectively solve because the feed-trough voltage of parasitic capacitance generation is to display panels
Impact, improve display quality.
To sum up, although the present invention is disclosed above with preferred embodiment, but above preferred embodiment and be not used to limit this
Invention, those of ordinary skill in the art, without departing from the spirit and scope of the present invention, various change and retouching all can be made,
Therefore protection scope of the present invention defines in the range of standard with claim.
Claims (10)
1. the GOA circuit that three rank drive, for liquid crystal display, it is characterised in that the GOA circuit bag that described three rank drive
Including multiple GOA unit of cascade, wherein, n-th grade of GOA unit includes:
Signal source of clock, for providing the clock signal of this grade, described clock signal includes the first high level and the first low electricity
Flat；
Constant voltage low level source, for providing the second low level；
Pull-up control module, for receiving the scanning signal of (n-1)th grade, and is generated this by the control of the level number of delivering a letter of (n-1)th grade
The scanning level signal of level；
Pull-up module, for being scanned controlling of level signal by described level, by described the of the clock signal of described level
One high level and described first low level output are to the outfan of the scanning signal of this grade；
Lower transmission module, for receiving the clock signal of described level, and the control being scanned level signal by described level generates
The level number of delivering a letter of the n-th+2 grades；
Drop-down module, is used for the scanning signal according to the n-th+2 grades, described second low level provided in described constant voltage low level source
The outfan of the scanning signal of output extremely described level；
Drop-down maintenance module, scans described the of signal for maintain the scanning level signal of described level and described level
Two low levels；And
Bootstrap capacitor, for generating the high level of the scanning level signal of described level；
The outfan of described pull-up control module and described pull-up module, described lower transmission module, described drop-down module, described drop-down
Module and described bootstrap capacitor is maintained to connect；Described constant voltage low level source and described drop-down maintenance module and described lower drawing-die
Block connects；Described signal source of clock is connected with described pull-up module and described lower transmission module.
The GOA circuit that three rank the most according to claim 1 drive, it is characterised in that described pull-up module includes the 20th
One thin film transistor (TFT), the grid of described 21st thin film transistor (TFT) is electrically connected at the outfan of described pull-up control module,
Source electrode accesses the clock signal of described level, and drain electrode is electrically connected at the outfan of the scanning signal of described level.
The GOA circuit that three rank the most according to claim 1 drive, it is characterised in that described drop-down module includes the 30th
One thin film transistor (TFT) and the 41st thin film transistor (TFT)；
The grid of described 31st thin film transistor (TFT) is electrically connected at the scanning signal output part of described the n-th+2 grades, source electrode electricity
Property be connected to described constant voltage low level source, drain electrode is electrically connected at the outfan of the scanning signal of described level；
The grid of described 41st thin film transistor (TFT) is electrically connected at the scanning signal output part of described the n-th+2 grades, source electrode electricity
Property be connected to described constant voltage low level source, drain electrode is electrically connected at the outfan of described pull-up control module.
The GOA circuit that three rank the most according to claim 1 drive, it is characterised in that described first low level is less than described
Second low level.
The GOA circuit that three rank the most according to claim 1 drive, it is characterised in that described pull-up control module includes the
11 thin film transistor (TFT)s, the grid of described 11st thin film transistor (TFT) is electrically connected at the level number of the delivering a letter output of described (n-1)th grade
End, source electrode is electrically connected at the scanning signal output part of described (n-1)th grade, and drain electrode is electrically connected at described pull-up control module
Outfan.
The GOA circuit that three rank the most according to claim 1 drive, it is characterised in that described lower transmission module includes the 20th
Two thin film transistor (TFT)s, the grid of described 22nd thin film transistor (TFT) is electrically connected at the outfan of described pull-up control module,
Source electrode accesses the clock signal of this grade, and drain electrode is electrically connected at the outfan of the level number of delivering a letter of described the n-th+2 grades.
The GOA circuit that the most according to claim 1, three rank drive, it is characterised in that described drop-down maintenance module includes first
Drop-down maintenance unit and the second drop-down maintenance unit；
Described first drop-down maintenance unit includes the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 53rd thin
Film transistor, the 54th thin film transistor (TFT), the 42nd thin film transistor (TFT) and the 32nd thin film transistor (TFT)；
The grid of described 51st thin film transistor (TFT) and drain electrode access the first square-wave signal, and source electrode is electrically connected at described the
The drain electrode of 52 thin film transistor (TFT)s and the grid of described 53rd thin film transistor (TFT)；
The grid of described 52nd thin film transistor (TFT) is electrically connected at the outfan of described pull-up control module, and source electrode electrically connects
It is connected to described constant voltage low level source；
The source electrode of described 53rd thin film transistor (TFT) accesses the first square-wave signal, and drain electrode is electrically connected at described 54th thin
The drain electrode of film transistor, the grid of described 42nd thin film transistor (TFT) and the grid of described 32nd thin film transistor (TFT)；
The grid of described 54th thin film transistor (TFT) is electrically connected at the outfan of described pull-up control module, and source electrode electrically connects
It is connected to described constant voltage low level source；
The source electrode of described 42nd thin film transistor (TFT) is electrically connected at described constant voltage low level source, and drain electrode is electrically connected at described
The outfan of pull-up control module；
The source electrode of described 32nd thin film transistor (TFT) is electrically connected at described constant voltage low level source, and drain electrode is electrically connected at described
The outfan of the scanning signal of this grade；
Described second drop-down maintenance unit includes the 61st thin film transistor (TFT), the 62nd thin film transistor (TFT), the 63rd thin
Film transistor, the 64th thin film transistor (TFT), the 43rd thin film transistor (TFT) and the 33rd thin film transistor (TFT)；
The grid of described 61st thin film transistor (TFT) and drain electrode access the second square-wave signal, and source electrode is electrically connected at described the
The drain electrode of 62 thin film transistor (TFT)s and the grid of described 63rd thin film transistor (TFT)；
The grid of described 62nd thin film transistor (TFT) is electrically connected at the outfan of described pull-up control module, and source electrode electrically connects
It is connected to described constant voltage low level source；
The source electrode of described 63rd thin film transistor (TFT) accesses the second square-wave signal, and drain electrode is electrically connected at described 64th thin
The drain electrode of film transistor, the grid of described 43rd thin film transistor (TFT) and the grid of described 33rd thin film transistor (TFT)；
The grid of described 64th thin film transistor (TFT) is electrically connected at the outfan of described pull-up control module, and source electrode electrically connects
It is connected to described constant voltage low level source；
The source electrode of described 43rd thin film transistor (TFT) is electrically connected at described constant voltage low level source, and drain electrode is electrically connected at described
The outfan of pull-up control module；
The source electrode of described 33rd thin film transistor (TFT) is electrically connected at described constant voltage low level source, and drain electrode is electrically connected at described
The outfan of the scanning signal of this grade.
The GOA circuit that three rank the most according to claim 7 drive, it is characterised in that described first square-wave signal and described
Second square-wave signal is the square wave that dutycycle is 1/2,1/2 cycle of phase.
The GOA circuit that three rank the most according to claim 1 drive, it is characterised in that described bootstrap capacitor is arranged on described
Between the outfan of the outfan of pull-up control module and the scanning signal of described level.
10. a liquid crystal display, it is characterised in that include the GOA circuit that the arbitrary three described rank of claim 1-9 drive.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610875013.2A CN106297715B (en) | 2016-09-30 | 2016-09-30 | A kind of the GOA circuit and liquid crystal display of the driving of three ranks |
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| CN201610875013.2A CN106297715B (en) | 2016-09-30 | 2016-09-30 | A kind of the GOA circuit and liquid crystal display of the driving of three ranks |
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| CN106297715B CN106297715B (en) | 2019-02-26 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107367876A (en) * | 2017-08-01 | 2017-11-21 | 深圳市华星光电技术有限公司 | Anti-static circuit and liquid crystal display panel |
| CN107705761A (en) * | 2017-09-27 | 2018-02-16 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN108461065A (en) * | 2017-02-20 | 2018-08-28 | 三星显示有限公司 | Grade circuit and the scanner driver for using grade circuit |
| CN108831398A (en) * | 2018-07-25 | 2018-11-16 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display device |
| CN109637488A (en) * | 2019-01-30 | 2019-04-16 | 惠科股份有限公司 | Driving method, display panel and driving module |
| CN109709733A (en) * | 2019-01-30 | 2019-05-03 | 惠科股份有限公司 | Display panel, driving method and driving module |
| WO2020019432A1 (en) * | 2018-07-26 | 2020-01-30 | 深圳市华星光电技术有限公司 | Liquid crystal panel |
| US10699659B2 (en) | 2017-09-27 | 2020-06-30 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Gate driver on array circuit and liquid crystal display with the same |
| CN114842786A (en) * | 2022-04-26 | 2022-08-02 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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| CN104167191A (en) * | 2014-07-04 | 2014-11-26 | 深圳市华星光电技术有限公司 | Complementary type GOA circuit used for flat display |
| CN105355176A (en) * | 2015-11-26 | 2016-02-24 | 深圳市华星光电技术有限公司 | Display panel and array gate driving circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108461065A (en) * | 2017-02-20 | 2018-08-28 | 三星显示有限公司 | Grade circuit and the scanner driver for using grade circuit |
| CN108461065B (en) * | 2017-02-20 | 2022-08-23 | 三星显示有限公司 | Stage circuit and scan driver using the same |
| CN107367876A (en) * | 2017-08-01 | 2017-11-21 | 深圳市华星光电技术有限公司 | Anti-static circuit and liquid crystal display panel |
| CN107705761A (en) * | 2017-09-27 | 2018-02-16 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| US10699659B2 (en) | 2017-09-27 | 2020-06-30 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Gate driver on array circuit and liquid crystal display with the same |
| CN108831398A (en) * | 2018-07-25 | 2018-11-16 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display device |
| WO2020019432A1 (en) * | 2018-07-26 | 2020-01-30 | 深圳市华星光电技术有限公司 | Liquid crystal panel |
| CN109637488A (en) * | 2019-01-30 | 2019-04-16 | 惠科股份有限公司 | Driving method, display panel and driving module |
| CN109709733A (en) * | 2019-01-30 | 2019-05-03 | 惠科股份有限公司 | Display panel, driving method and driving module |
| US11386862B2 (en) | 2019-01-30 | 2022-07-12 | HKC Corporation Limited | Drive method, display panel and driving circuit |
| CN114842786A (en) * | 2022-04-26 | 2022-08-02 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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| Publication number | Publication date |
|---|---|
| CN106297715B (en) | 2019-02-26 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |