CN106294143A - The adjustment method of the depositor of chip and device - Google Patents
The adjustment method of the depositor of chip and device Download PDFInfo
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- CN106294143A CN106294143A CN201610629676.6A CN201610629676A CN106294143A CN 106294143 A CN106294143 A CN 106294143A CN 201610629676 A CN201610629676 A CN 201610629676A CN 106294143 A CN106294143 A CN 106294143A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
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Abstract
The present invention provides adjustment method and the device of the depositor of a kind of chip.The embodiment of the present invention debugs the operational order of chip to be debugged by receiving, described operational order comprises the depositor physical address of the chip described to be debugged that user provides, and then call operation system drives the designated equipment node of layer, register logical address with the chip described to be debugged corresponding to the depositor physical address of the described chip to be debugged of acquisition, make it possible to the register logical address according to described chip to be debugged, operate the depositor of described chip to be debugged, owing to no longer adding specific debugging interface individually for certain chip, but all chips are added the unified debugging interface of, make to call unified debugging interface, so that call operation system to drive the designated equipment node of layer, debug whole chips to be debugged, thus improve debugging efficiency.
Description
[technical field]
The present invention relates to hardware debugging technique, particularly relate to adjustment method and the device of the depositor of a kind of chip.
[background technology]
In design, debugging and the application process of chip, the depositor under various states is entered by most work exactly
Row debugging, i.e. adjusts the value of depositor.In prior art, specific debugging interface can be added individually for certain chip,
When debugging, then can call specific debugging interface to debug the depositor of chip.
As a rule, the adjustment to a termination function, need to adjust depositing of the relevant multiple chips of this termination function
The value of device, this is accomplished by the specific debugging interface called respectively corresponding to each chip, debugs each chip, so, make
Obtain debugging work load to be greatly increased, the reduction of debugging efficiency can be caused.
[summary of the invention]
The many aspects of the present invention provide adjustment method and the device of the depositor of a kind of chip, in order to improve debugging effect
Rate.
An aspect of of the present present invention, it is provided that the adjustment method of the depositor of a kind of chip, including:
Receive the operational order debugging chip to be debugged, described operational order comprises the core described to be debugged that user provides
The depositor physical address of sheet；
Call operation system drives the designated equipment node of layer, to obtain the depositor of described chip to be debugged physically
The register logical address of the chip described to be debugged corresponding to location；
According to the register logical address of described chip to be debugged, operate the depositor of described chip to be debugged.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described reception is adjusted
Try the operational order of chip to be debugged, described operational order comprises the depositor physics of the chip described to be debugged that user provides
Before address, also include:
Debugging interface is provided, for described user based on described Debugging interface, it is provided that described core to be debugged to described user
The depositor physical address of sheet.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described operation system
System includes (SuSE) Linux OS or Android operation system.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described appointment sets
Slave node is /dev/mem.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described in call behaviour
Make system drives the designated equipment node of layer, described in obtaining corresponding to the depositor physical address of described chip to be debugged
Before the register logical address of chip to be debugged, also include:
By the depositor physical address of described chip to be debugged, it is mapped to described designated equipment node；
By described designated equipment node, it is mapped to user's space.
Another aspect of the present invention, it is provided that the debugging apparatus of the depositor of a kind of chip, including:
Receiving unit, for receiving the operational order debugging chip to be debugged, comprising user in described operational order provides
The depositor physical address of chip described to be debugged；
Call unit, drives the designated equipment node of layer in call operation system, to obtain described chip to be debugged
The register logical address of the chip described to be debugged corresponding to depositor physical address；
Operating unit, for the register logical address according to described chip to be debugged, operates described chip to be debugged
Depositor.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described reception list
Unit, is additionally operable to
Debugging interface is provided, for described user based on described Debugging interface, it is provided that described core to be debugged to described user
The depositor physical address of sheet.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described operation system
System includes (SuSE) Linux OS or Android operation system.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described appointment sets
Slave node is /dev/mem.
Aspect as above and arbitrary possible implementation, it is further provided a kind of implementation, described device is also
Including map unit, it is used for
By the depositor physical address of described chip to be debugged, it is mapped to described designated equipment node；And
By described designated equipment node, it is mapped to user's space.
As shown from the above technical solution, the embodiment of the present invention debugs the operational order of chip to be debugged by receiving, described
Operational order comprises the depositor physical address of the chip described to be debugged that user provides, and then call operation system drives
The designated equipment node of layer, to obtain chip described to be debugged corresponding to the depositor physical address of described chip to be debugged
Register logical address, enabling according to the register logical address of described chip to be debugged, operates described chip to be debugged
Depositor, due to no longer individually for certain chip add specific debugging interface, but to all chips add one system
One debugging interface so that call unified debugging interface, to drive the designated equipment node of layer in call operation system, debugs complete
The chip to be debugged in portion, thus improve debugging efficiency.
It addition, use technical scheme provided by the present invention, by operating system will drive the designated equipment node of layer
It is mapped to user's space, it becomes possible to realize, by the register address of whole chips to be debugged, being mapped to user's space, so,
Just obtain the register address of the visible described chip to be debugged of user, it is possible to be effectively improved the operability of debugging.
It addition, use technical scheme provided by the present invention, it is not necessary to the relative program of the depositor of chip to be debugged is entered
Row recompilates, but by the register address of whole chips to be debugged, is mapped to user's space, simple to operate, and
And the most flexible, it is possible to effectively it is effectively improved debugging efficiency further.
[accompanying drawing explanation]
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to embodiment or description of the prior art
The accompanying drawing used required in is briefly described, it should be apparent that, the accompanying drawing in describing below is some realities of the present invention
Execute example, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to attached according to these
Figure obtains other accompanying drawing.
The schematic flow sheet of the adjustment method of the depositor of the chip that Fig. 1 provides for one embodiment of the invention；
The structural representation of the debugging apparatus of the depositor of the chip that Fig. 2 provides for another embodiment of the present invention；
The structural representation of the debugging apparatus of the depositor of the chip that Fig. 3 provides for another embodiment of the present invention.
[detailed description of the invention]
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
Other embodiments whole obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
It should be noted that terminal involved in the embodiment of the present invention can include but not limited to mobile phone, individual digital
Assistant (Personal Digital Assistant, PDA), radio hand-held equipment, panel computer (Tablet Computer),
PC (Personal Computer, PC), MP3 player, MP4 player, wearable device (such as, intelligent glasses,
Intelligent watch, Intelligent bracelet etc.) etc..
It addition, the terms "and/or", a kind of incidence relation describing affiliated partner, expression can exist
Three kinds of relations, such as, A and/or B, can represent: individualism A, there is A and B, individualism B these three situation simultaneously.Separately
Outward, character "/" herein, typically represent the forward-backward correlation relation to liking a kind of "or".
The schematic flow sheet of the adjustment method of the depositor of the chip that Fig. 1 provides for one embodiment of the invention, such as Fig. 1 institute
Show.
101, receive the operational order of debugging chip to be debugged, described operational order comprises and waits to adjust described in user's offer
The depositor physical address of examination chip.
102, call operation system drives the designated equipment node of layer, deposits implements with obtain described chip to be debugged
The register logical address of reason chip described to be debugged corresponding to address.
Wherein, described operating system can include but not limited to that (SuSE) Linux OS or Android (Android) operation are
System, this is not particularly limited by the present embodiment.
103, according to the register logical address of described chip to be debugged, the depositor of described chip to be debugged is operated.
It should be noted that the executive agent of 101～103 can be partly or entirely the application being located locally terminal,
Or can also be to be arranged in the plug-in unit in the application of local terminal or SDK (Software
Development Kit, SDK) etc. functional unit, or can also for the process engine that is positioned in network side server, or
Can also be the distributed system being positioned at network side, this be particularly limited by the present embodiment.
It is understood that the local program (nativeApp) that described application can be mounted in terminal, or also may be used
To be a web page program (webApp) of browser in terminal, this is not particularly limited by the present embodiment.
So, by receiving the operational order debugging chip to be debugged, described operational order comprises the institute that user provides
State the depositor physical address of chip to be debugged, and then call operation system drives the designated equipment node of layer, to obtain
State the register logical address of chip described to be debugged corresponding to the depositor physical address of chip to be debugged, enabling root
According to the register logical address of described chip to be debugged, operate the depositor of described chip to be debugged, due to no longer individually for
Certain chip adds specific debugging interface, but all chips add the unified debugging interface of so that call unified tune
Try mouth, so that call operation system to drive the designated equipment node of layer, debug whole chips to be debugged, thus improve
Debugging efficiency.
Alternatively, in a possible implementation of the present embodiment, in 101, user provided described in wait to adjust
The depositor physical address of examination chip, can be a depositor physical address, is used for debugging a depositor, or all right
Being multiple depositor physical address, be used for debugging multiple depositor, this is not particularly limited by the present embodiment.
Alternatively, in a possible implementation of the present embodiment, before 101, it is also possible to further to described
User provides Debugging interface, for described user based on described Debugging interface, it is provided that the depositor physics of described chip to be debugged
Address.
During a concrete implementation, user can be with inquiring technology handbook, to find the depositor of chip to be debugged
Physical address, and the depositor physical address of this chip to be debugged is input to the appointment region of Debugging interface, provide described
The depositor physical address of chip to be debugged, or the functionality controls that can also be provided by Debugging interface, select this debugging
The specified option that interface is given, provides the depositor physical address of described chip to be debugged, and the present embodiment does not carry out spy to this
Do not limit.
Alternatively, in a possible implementation of the present embodiment, the operating system called drives the finger of layer
Locking equipment node, is to patrol for storing the depositor of the depositor physical address of described chip to be debugged and described chip to be debugged
Collect the corresponding relation between address.So-called register logical address, refers to drive in an operating system what layer used to deposit
Device address.
Specifically, described designated equipment node can be/this device node of dev/mem.In operating system such as, class
In Unix system, the access to equipment is all based on document form, will access a hardware device, general general with access one
Logical file is similar.Therefore, the device node under/dev is just existed as such class special file.
Alternatively, in a possible implementation of the present embodiment, before 102, it is also possible to further by described
The depositor physical address of chip to be debugged, is mapped to described designated equipment node.So so that described designated equipment node is deposited
Store up the corresponding pass between the depositor physical address of described chip to be debugged and the register logical address of described chip to be debugged
System.Then, further by described designated equipment node, it is mapped to user's space.
Specifically, can be instructed by mmap, by the register address of chip to be debugged, be mapped to user's space, make
Just must can complete the operation to depositor at user's space, such as, read the value of depositor, or the value of write depositor,
Etc..So, it is mapped to the register address of user's space by operation and is equal to operate the register address of kernel spacing, example
As, the value of depositor that currently be there is a need to check and write can be read in real time, or, then for example, it is also possible to once read
Taking or write the value of multiple depositor, Real-time and Dynamic carries out the debugging of depositor.
Existing adjustment method, it usually needs amendment code, interpolation printf, compiling, programming can perform image file
In Flash, starting operating system, connect the value that serial ports output prints, debugging step is the most loaded down with trivial details, inefficiency, dumb.
Use technical scheme provided by the present invention, can run after operating system is got up, by all of required debugging are posted
The register address of storage, is mapped to user's space, the real-time value checking and revising depositor, and supports that continuous print is deposited
Device is checked and revises, it is possible to effect to chip peripheral hardware after the real-time depositor amendment following the tracks of chip, it is not necessary to amendment is appointed
What code, compiling, programming, the step such as restart.Compare the adjustment method of traditional value by printing depositor in kernel state,
The method substantially increases the debugging efficiency of the depositor of chip.
In the present embodiment, by receiving the operational order debugging chip to be debugged, described operational order comprises user and carries
The depositor physical address of the chip described to be debugged of confession, and then call operation system drives the designated equipment node of layer, with
Obtain the register logical address of chip described to be debugged corresponding to the depositor physical address of described chip to be debugged so that
The depositor of described chip to be debugged can be operated, due to the most single according to the register logical address of described chip to be debugged
Solely add specific debugging interface for certain chip, but all chips are added the unified debugging interface of so that call
Unified debugging interface, to drive the designated equipment node of layer in call operation system, debugs whole chips to be debugged, thus
Improve debugging efficiency.
It addition, use technical scheme provided by the present invention, by operating system will drive the designated equipment node of layer
It is mapped to user's space, it becomes possible to realize, by the register address of whole chips to be debugged, being mapped to user's space, so,
Just obtain the register address of the visible described chip to be debugged of user, it is possible to be effectively improved the operability of debugging.
It addition, use technical scheme provided by the present invention, it is not necessary to the relative program of the depositor of chip to be debugged is entered
Row recompilates, but by the register address of whole chips to be debugged, is mapped to user's space, simple to operate, and
And the most flexible, it is possible to effectively it is effectively improved debugging efficiency further.
It should be noted that for aforesaid each method embodiment, in order to be briefly described, therefore it is all expressed as a series of
Combination of actions, but those skilled in the art should know, the present invention is not limited by described sequence of movement because
According to the present invention, some step can use other orders or carry out simultaneously.Secondly, those skilled in the art also should know
Knowing, embodiment described in this description belongs to preferred embodiment, involved action and the module not necessarily present invention
Necessary.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and does not has the portion described in detail in certain embodiment
Point, may refer to the associated description of other embodiments.
The structural representation of the debugging apparatus of the depositor of the chip that Fig. 2 provides for another embodiment of the present invention, such as Fig. 2 institute
Show.The debugging apparatus of the depositor of the chip of the present embodiment can include receiving unit 21, call unit 22 and operating unit 23.
Wherein, receive unit 21, for receiving the operational order debugging chip to be debugged, described operational order comprises what user provided
The depositor physical address of described chip to be debugged；Call unit 22, drives the designated equipment of layer in call operation system
Node, to obtain the register logical ground of the chip described to be debugged corresponding to the depositor physical address of described chip to be debugged
Location；Operating unit 23, for the register logical address according to described chip to be debugged, operates depositing of described chip to be debugged
Device.
Wherein, described operating system can include but not limited to that (SuSE) Linux OS or Android (Android) operation are
System, this is not particularly limited by the present embodiment.
It should be noted that the debugging apparatus of the depositor of chip that provided of the present embodiment can be partly or entirely
It is located locally the application of terminal, or can also be to be arranged in the plug-in unit in the application of local terminal or SDK
The functional units such as bag (Software Development Kit, SDK), or can also be for the place being positioned in network side server
Reason engine, or can also be the distributed system being positioned at network side, this is not particularly limited by the present embodiment.
It is understood that the local program (nativeApp) that described application can be mounted in terminal, or also may be used
To be a web page program (webApp) of browser in terminal, this is not particularly limited by the present embodiment.
Alternatively, in a possible implementation of the present embodiment, described reception unit 21, it is also possible to use further
In providing Debugging interface to described user, for described user based on described Debugging interface, it is provided that posting of described chip to be debugged
Storage physical address.
Alternatively, in a possible implementation of the present embodiment, the operating system called drives the finger of layer
Locking equipment node, is to patrol for storing the depositor of the depositor physical address of described chip to be debugged and described chip to be debugged
Collect the corresponding relation between address.So-called register logical address, refers to drive in an operating system what layer used to deposit
Device address.
Specifically, described designated equipment node can be/this device node of dev/mem.In operating system such as, class
In Unix system, the access to equipment is all based on document form, will access a hardware device, general general with access one
Logical file is similar.Therefore, the device node under/dev is just existed as such class special file.
Alternatively, in a possible implementation of the present embodiment, as it is shown on figure 3, the core that the present embodiment is provided
The debugging apparatus of the depositor of sheet can further include map unit 31, may be used for depositing described chip to be debugged
Device physical address, is mapped to described designated equipment node；And by described designated equipment node, it is mapped to user's space.
It should be noted that method in embodiment corresponding to Fig. 1, the depositor of the chip that can be provided by the present embodiment
Debugging apparatus realizes.Describing the related content that may refer in embodiment corresponding to Fig. 1 in detail, here is omitted.
In the present embodiment, receive the operational order of debugging chip to be debugged by receiving unit, described operational order wraps
Depositor physical address containing the chip described to be debugged that user provides, and then by call unit call operation system drives layer
Designated equipment node, to obtain posting of chip described to be debugged corresponding to the depositor physical address of described chip to be debugged
Storage logical address so that operating unit can be waited to adjust described in operation according to the register logical address of described chip to be debugged
All chips owing to no longer adding specific debugging interface individually for certain chip, but are added by the depositor of examination chip
The unified debugging interface of one so that call unified debugging interface, to drive the designated equipment node of layer in call operation system, comes
Debug whole chips to be debugged, thus improve debugging efficiency.
It addition, use technical scheme provided by the present invention, by operating system will drive the designated equipment node of layer
It is mapped to user's space, it becomes possible to realize, by the register address of whole chips to be debugged, being mapped to user's space, so,
Just obtain the register address of the visible described chip to be debugged of user, it is possible to be effectively improved the operability of debugging.
It addition, use technical scheme provided by the present invention, it is not necessary to the relative program of the depositor of chip to be debugged is entered
Row recompilates, but by the register address of whole chips to be debugged, is mapped to user's space, simple to operate, and
And the most flexible, it is possible to effectively it is effectively improved debugging efficiency further.
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, and the system of foregoing description,
The specific works process of device and unit, is referred to the corresponding process in preceding method embodiment, does not repeats them here.
In several embodiments provided by the present invention, it should be understood that disclosed system, apparatus and method are permissible
Realize by another way.Such as, device embodiment described above is only schematically, such as, and described unit
Dividing, be only a kind of logic function and divide, actual can have other dividing mode, such as, multiple unit or group when realizing
Part can in conjunction with or be desirably integrated into another system, or some features can be ignored, or does not performs.Another point, shown
Or the coupling each other discussed or direct-coupling or communication connection can be indirect by some interfaces, device or unit
Coupling or communication connection, can be electrical, machinery or other form.
The described unit illustrated as separating component can be or may not be physically separate, shows as unit
The parts shown can be or may not be physical location, i.e. may be located at a place, or can also be distributed to multiple
On NE.Some or all of unit therein can be selected according to the actual needs to realize the mesh of the present embodiment scheme
's.
It addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it is also possible to
It is that unit is individually physically present, it is also possible to two or more unit are integrated in a unit.Above-mentioned integrated list
Unit both can realize to use the form of hardware, it would however also be possible to employ hardware adds the form of SFU software functional unit and realizes.
The above-mentioned integrated unit realized with the form of SFU software functional unit, can be stored in an embodied on computer readable and deposit
In storage media.Above-mentioned SFU software functional unit is stored in a storage medium, including some instructions with so that a computer
Device (can be personal computer, server, or network equipment etc.) or processor (processor) perform the present invention each
The part steps of method described in embodiment.And aforesaid storage medium includes: USB flash disk, portable hard drive, read only memory (Read-
Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disc or CD etc. various
The medium of program code can be stored.
Last it is noted that above example is only in order to illustrate technical scheme, it is not intended to limit；Although
With reference to previous embodiment, the present invention is described in detail, it will be understood by those within the art that: it still may be used
So that the technical scheme described in foregoing embodiments to be modified, or wherein portion of techniques feature is carried out equivalent；
And these amendment or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
1. the adjustment method of the depositor of a chip, it is characterised in that including:
Receive the operational order debugging chip to be debugged, described operational order comprises the chip described to be debugged of user's offer
Depositor physical address；
Call operation system drives the designated equipment node of layer, to obtain the depositor physical address institute of described chip to be debugged
The register logical address of corresponding chip described to be debugged；
According to the register logical address of described chip to be debugged, operate the depositor of described chip to be debugged.
Method the most according to claim 1, it is characterised in that the operational order of chip to be debugged, institute are debugged in described reception
Before stating the depositor physical address of the chip described to be debugged that user's offer is provided in operational order, also include:
Debugging interface is provided, for described user based on described Debugging interface, it is provided that described chip to be debugged to described user
Depositor physical address.
Method the most according to claim 1, it is characterised in that described operating system include (SuSE) Linux OS or
Android operation system.
Method the most according to claim 1, it is characterised in that described designated equipment node is /dev/mem.
5. according to the method described in Claims 1 to 4 any claim, it is characterised in that described call operation system is driven
The designated equipment node of dynamic layer, to obtain the chip described to be debugged corresponding to the depositor physical address of described chip to be debugged
Register logical address before, also include:
By the depositor physical address of described chip to be debugged, it is mapped to described designated equipment node；
By described designated equipment node, it is mapped to user's space.
6. the debugging apparatus of the depositor of a chip, it is characterised in that including:
Receive unit, for receiving the operational order debugging chip to be debugged, described operational order comprises the institute that user provides
State the depositor physical address of chip to be debugged；
Call unit, drives the designated equipment node of layer in call operation system, to obtain posting of described chip to be debugged
The register logical address of the chip described to be debugged corresponding to storage physical address；
Operating unit, for the register logical address according to described chip to be debugged, operates depositing of described chip to be debugged
Device.
Device the most according to claim 6, it is characterised in that described reception unit, is additionally operable to
Debugging interface is provided, for described user based on described Debugging interface, it is provided that described chip to be debugged to described user
Depositor physical address.
Device the most according to claim 6, it is characterised in that described operating system include (SuSE) Linux OS or
Android operation system.
Device the most according to claim 6, it is characterised in that described designated equipment node is /dev/mem.
10. according to the device described in claim 6～9 any claim, it is characterised in that described device also includes mapping list
Unit, is used for
By the depositor physical address of described chip to be debugged, it is mapped to described designated equipment node；And
By described designated equipment node, it is mapped to user's space.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610629676.6A CN106294143B (en) | 2016-08-03 | 2016-08-03 | Debugging method and device for chip register |
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|---|---|---|---|
| CN201610629676.6A CN106294143B (en) | 2016-08-03 | 2016-08-03 | Debugging method and device for chip register |
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| CN106294143B CN106294143B (en) | 2020-03-03 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114564414A (en) * | 2022-04-28 | 2022-05-31 | 武汉慧联无限科技有限公司 | Debugging method, device and storage medium |
| WO2023202148A1 (en) * | 2022-04-20 | 2023-10-26 | 苏州浪潮智能科技有限公司 | Register debugging platform and debugging method |
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| CN102810123A (en) * | 2011-06-02 | 2012-12-05 | 苏州雄立科技有限公司 | Excitation generating method and device |
| CN105159742A (en) * | 2015-07-06 | 2015-12-16 | 北京星网锐捷网络技术有限公司 | Unvarnished transmission method and system for PCI device of virtual machine |
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| CN114564414A (en) * | 2022-04-28 | 2022-05-31 | 武汉慧联无限科技有限公司 | Debugging method, device and storage medium |
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