CN106292996A - Voltage reduction method and system based on multi-core chip - Google Patents

Voltage reduction method and system based on multi-core chip Download PDF

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Publication number
CN106292996A
CN106292996A CN201610600313.XA CN201610600313A CN106292996A CN 106292996 A CN106292996 A CN 106292996A CN 201610600313 A CN201610600313 A CN 201610600313A CN 106292996 A CN106292996 A CN 106292996A
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voltage
core
threads
kernel
running
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CN201610600313.XA
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Chinese (zh)
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李媛媛
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李媛媛
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/329Power saving characterised by the action undertaken by task scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3296Power saving characterised by the action undertaken by lowering the supply or operating voltage

Abstract

The invention provides a voltage reduction method and system based on a multi-core chip. The method comprises the following steps: detecting the voltage of each core and an operated thread; judging whether the voltage of the core exceeds a voltage threshold value or not; and if the voltage of the core exceeds the voltage threshold value, reducing the amount of the threads of the core. The technical scheme provided by the invention has the advantage that the voltage is effectively lowered.

Description

基于多核芯片的电压降低方法及系统 Multicore chip based on the voltage reduction method and system

技术领域 FIELD

[0001]本发明涉及电子领域,尤其涉及一种基于多核芯片的电压降低方法及系统。 [0001] The present invention relates to the field of electronics, in particular, it relates to a multi-core chip based on the voltage reduction method and system.

背景技术 Background technique

[0002]芯片,英文为Chip;芯片组为Chipset。 [0002] chip, English as Chip; chipset Chipset. 芯片一般是指集成电路的载体,也是集成电路经过设计、制造、封装、测试后的结果,通常是一个可以立即使用的独立的整体。 Generally refers to an integrated circuit chip carrier, is the result after the integrated circuit design, manufacture, packaging, testing, usually a whole separate immediate use. “芯片”和“集成电路”这两个词经常混着使用,比如在大家平常讨论话题中,集成电路设计和芯片设计说的是一个意思,芯片行业、集成电路行业、IC行业往往也是一个意思。 "Chip" and "IC" These two terms are often mixed with use, such as we usually discuss topics, integrated circuit design and chip design say is a meaning, the chip industry, IC industry, IC industry is also often a meaning . 实际上,这两个词有联系,也有区别。 In fact, these two words are linked, they are different. 集成电路实体往往要以芯片的形式存在,因为狭义的集成电路,是强调电路本身,比如简单到只有五个元件连接在一起形成的相移振荡器,当它还在图纸上呈现的时候,我们也可以叫它集成电路,当我们要拿这个小集成电路来应用的时候,那它必须以独立的一块实物,或者嵌入到更大的集成电路中,依托芯片来发挥他的作用;集成电路更着重电路的设计和布局布线,芯片更强调电路的集成、生产和封装。 The integrated circuit often in the form of solid chips, since narrow integrated circuit emphasis circuit itself, such as a simple element to be joined together to form a five phase-shift oscillator, when it is presented on the drawing, we integrated circuit can call it, when we bring this to a small integrated circuit applications, then it must be independent of one kind, or embedded into a larger integrated circuit, rely on chips to play his role; more integrated circuit focused on the design and layout of the circuit, more emphasis chip integrated circuit manufacturing and packaging. 而广义的集成电路,当涉及到行业(区别于其他行业)时,也可以包含芯片相关的各种含义。 The broad integrated circuit, when it comes to industry (different from other industries), the chip can also contain a variety of meanings related.

[0003]现有的电子芯片均有多个内核,但是现有的电子芯片无法对多个内核的电压进行控制。 [0003] Existing electronic chip has a plurality of cores, but the existing electronic chip can not control the voltage of the plurality of cores.

发明内容 SUMMARY

[0004]提供一种基于多核芯片的电压降低方法,其解决了现有技术的无法实现多核芯片的电压降低的缺点。 [0004] to provide a multicore chip based on voltage reduction method, which solves the disadvantages of voltage drop can not be achieved in prior art multi-core chips.

[0005] —方面,提供一种基于多核芯片的电压降低方法,所述方法包括如下步骤: [0005] - aspect, a method of reducing the voltage based on a multi-core chips, said method comprising the steps of:

[0006]检测每个内核的电压以及运行的线程; [0006] Each core voltage and the detected running threads;

[0007]判断该内核的电压是否超过电压阈值; [0007] The core is determined whether the voltage exceeds a threshold voltage;

[0008]如该内核的电压超过电压阈值,则减少该内核的线程数量。 [0008] The core of the voltage exceeds a threshold voltage, and decreases the number of threads of the core.

[0009]可选的,所述方法还包括: [0009] Optionally, the method further comprising:

[0010]将减少的该内核的线程分配到其他内核中运行。 [0010] The reduction of the thread assigned to other kernel running in the kernel.

[0011 ]可选的,所述方法还包括: [0011] Optionally, the method further comprising:

[0012]将减少的该内核的线程平均分配到其他内核中运行。 [0012] The reduction of the average core thread assigned to other running in the kernel.

[0013]第二方面,提供一种基于多核芯片的电压降低系统,所述系统包括: [0013] In a second aspect, there is provided a method of reducing the voltage based on a multi-core chip system, the system comprising:

[0014]检测单元,用于检测每个内核的电压以及运行的线程; [0014] detection means for detecting a voltage of each core and running threads;

[0015]判断单元,用于判断该内核的电压是否超过电压阈值; [0015] determination means for determining whether the voltage exceeds the voltage threshold of the core;

[0016]减少单元,用于如该内核的电压超过电压阈值,则减少该内核的线程数量。 [0016] reducing means, such as for the core voltage exceeds the threshold voltage, and decreases the number of threads of the core.

[0017]可选的,所述系统还包括: [0017] Optionally, the system further comprising:

[0018]分配单元,用于将减少的该内核的线程分配到其他内核中运行。 [0018] The dispensing unit, for reducing the thread assigned to other kernel running in the kernel.

[0019]可选的,所述系统还包括: [0019] Optionally, the system further comprising:

[0020]均分单元,用于将减少的该内核的线程平均分配到其他内核中运行。 [0020] sharing means for reducing the average core assigned to other threads running in the kernel.

[0021]本发明具体实施方式提供的技术方案检测每个内核的电压以及运行的线程,如该内核的电压超过电压阈值,则减少该内核的线程数量,所以其具有降低芯片的电压的优点。 Voltage, and the thread running aspect detect each kernel DETAILED DESCRIPTION [0021] The present invention provides, as the voltage of the core exceeds the voltage threshold, and decreases the number of threads of the core, it has the advantage of reducing the voltage of the chip.

附图说明 BRIEF DESCRIPTION

[0022]为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0022] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments the drawings are only some embodiments of the present invention, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings.

[0023]图1为本发明提供的一种基于多核芯片的电压降低方法的流程图; [0023] FIG. 1 is a flowchart of a method for reducing the voltage based on a multi-core chip provided by the present invention;

[0024]图2为本发明提供的一种基于多核芯片的电压降低系统的结构图。 [0024] FIG 2 structural diagram of a multi-core chips based on the voltage reduction system provided by the present invention.

具体实施方式 Detailed ways

[0025]下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0025] below in conjunction with the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described embodiments are merely part of embodiments of the present invention, but not all embodiments example. 基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of ordinary skill in the art without any creative effort shall fall within the scope of the present invention.

[0026]参阅图1,图1为本发明第一较佳实施方式提供的一种基于多核芯片的电压降低方法的流程图,该方法由电子芯片来完成,该方法如图1所示,包括如下步骤: [0026] Referring to FIG. 1, FIG. 1 is a flowchart of a method for reducing the voltage based on a multi-core chip to provide a first preferred embodiment of the process performed by the electronic chip to the invention shown, the method shown in Figure 1, comprising the steps of:

[0027]步骤S101、检测每个内核的电压以及运行的线程; [0027] step S101, the detected voltage of each core and running threads;

[0028]步骤S102、判断该内核的电压是否超过电压阈值; [0028] step S102, the core is determined whether the voltage exceeds a threshold voltage;

[0029]步骤S103、如该内核的电压超过电压阈值,则减少该内核的线程数量。 [0029] Step S103, the core such that the voltage exceeds the threshold voltage, and decreases the number of threads of the core.

[0030 ]本发明具体实施方式提供的技术方案检测每个内核的电压以及运行的线程,如该内核的电压超过电压阈值,则减少该内核的线程数量,所以其具有降低芯片的电压的优点。 Technical Solution Detection [0030] In particular embodiments the present invention provides each core voltage and running threads, such as the voltage of the core exceeds the voltage threshold, and decreases the number of threads of the core, it has the advantage of reducing the voltage of the chip.

[0031] 可选的,上述方法在步骤S103之后还可以包括: [0031] Optionally, the method may further comprise, after step S103:

[0032]将减少的该内核的线程分配到其他内核中运行。 [0032] The reduction of the thread assigned to other kernel running in the kernel.

[0033] 可选的,上述方法在步骤S103之后还可以包括: [0033] Optionally, the method may further comprise, after step S103:

[0034]将减少的该内核的线程平均分配到其他内核中运行。 [0034] The kernel will reduce the average assigned to other threads running in the kernel.

[0035]参阅图2,图2为本发明第二较佳实施方式提供的一种基于多核芯片的电压降低系统,该系统包括: One second preferred embodiment [0035] Referring to FIG. 2, FIG. 2 of the present invention provides a reduction system based on a voltage of the multi-core chips, the system comprising:

[0036]检测单元201,用于检测每个内核的电压以及运行的线程; [0036] The detection unit 201, and a voltage for detecting each core threads running;

[0037]判断单元202,用于判断该内核的电压是否超过电压阈值; [0037] determination unit 202 for determining whether the voltage exceeds the voltage threshold of the core;

[0038]减少单元203,用于如该内核的电压超过电压阈值,则减少该内核的线程数量。 [0038] The reduction unit 203, as for the core voltage exceeds the threshold voltage, and decreases the number of threads of the core.

[0039 ]本发明具体实施方式提供的技术方案检测每个内核的电压以及运行的线程,如该内核的电压超过电压阈值,则减少该内核的线程数量,所以其具有降低芯片的电压的优点。 Technical Solution Detection [0039] In particular embodiments the present invention provides each core voltage and running threads, such as the voltage of the core exceeds the voltage threshold, and decreases the number of threads of the core, it has the advantage of reducing the voltage of the chip.

[0040] 可选的,上述系统还可以包括: [0040] Optionally, the system may further comprise:

[0041]分配单元204,用于将减少的该内核的线程分配到其他内核中运行。 [0041] The distribution unit 204, for reducing the thread assigned to other kernel running in the kernel.

[0042] 可选的,上述系统还可以包括: [0042] Optionally, the system may further comprise:

[0043]均分单元205,用于将减少的该内核的线程平均分配到其他内核中运行。 [0043] The average unit 205 for reducing the average core assigned to other threads running in the kernel.

[0044]需要说明的是,对于前述的各方法实施方式或实施例,为了简单描述,故将其都表述为一系列的动作组合,但是本领域技术人员应该知悉,本发明并不受所描述的动作顺序的限制,因为根据本发明,某些步骤可以采用其他顺序或者同时进行。 [0044] Incidentally, the foregoing method described in the embodiments or examples, for ease of description, it is described as a series combination of actions, those skilled in the art should understand that the present invention is not limited by the order of the operation, since according to the present invention, some steps may be performed simultaneously or in other sequences. 其次,本领域技术人员也应该知悉,说明书中所描述实施方式或实施例均属于优选实施例,所涉及的动作和单元并不一定是本发明所必须的。 Secondly, those skilled in the art should also know that, embodiment or embodiments are exemplary embodiments described in the specification, and the action units involved are not necessarily required by the present invention.

[0045]在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。 [0045] In the above embodiment, the description of the various embodiments have different emphases, certain embodiments not detailed in part, be related descriptions in other embodiments.

[0046]本发明实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。 The method of embodiment The procedure of Example [0046] The present invention may adjust the order, deletion, and combined according to need.

[0047]本发明实施例装置中的单元可以根据实际需要进行合并、划分和删减。 The apparatus unit according to embodiment [0047] The present invention may be combined according to actual needs, division and deletion. 本领域的技术人员可以将本说明书中描述的不同实施例以及不同实施例的特征进行结合或组合。 Those skilled in the art may be various embodiments and features of the different embodiments described in this specification in conjunction with, or be a combination thereof.

[0048]通过以上的实施方式的描述,所属领域的技术人员可以清楚地了解到本发明可以用硬件实现,或固件实现,或它们的组合方式来实现。 [0048] By the above described embodiments, those skilled in the art can understand that the present invention may be implemented in hardware or firmware, or a combination thereof manner. 当使用软件实现时,可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。 When implemented in software, functions described above can be stored in a computer-readable medium or transmitted over as one or more instructions or code on a computer-readable medium. 计算机可读介质包括计算机存储介质和通信介质,其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。 Computer-readable media includes both computer storage media and communication media, wherein communication media includes any medium that facilitates transfer of a computer program from one place to another direction. 存储介质可以是计算机能够存取的任何可用介质。 A storage media may be any available media that can be accessed by a computer. 以此为例但不限于:计算机可读介质可以包括随机存取存储器(Random Access Memory ,RAM)、只读存储器(Read-Only Memory ,ROM)、电可擦可编程只读存储器(ElectricallyErasable Programmable Read-Only Memory,EEPR0M)、只读光盘(Compact Disc Read-Only Memory,⑶-ROM)或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。 As an example, but not limited to: a computer-readable medium may comprise random access memory (Random Access Memory, RAM), read-only memory (Read-Only Memory, ROM), electrically erasable programmable read only memory (ElectricallyErasable Programmable Read -Only memory, EEPR0M), CD-ROM (Compact disc Read-Only memory, ⑶-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or can be used to carry or store instructions or data structures in the form of desired program code in a computer and can be accessed by any other medium. 此外。 In addition. 任何连接可以适当的成为计算机可读介质。 Any suitable connection may be a computer-readable medium. 例如,如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(Digital Subscriber Line,DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的,那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。 For example, if the software is using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (Digital Subscriber Line, DSL), or such as infrared, radio, and microwave wireless technology from a website, server, or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the fixing medium belongs. 如本发明所使用的,盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟,其中盘通常磁性的复制数据,而碟则用激光来光学的复制数据。 As used in the present invention, a disk (Disk) and disc (Disc), includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc, copy data where disks usually magnetically, while discs with lasers reproduce data optically. 上面的组合也应当包括在计算机可读介质的保护范围之内。 Combinations of the above should also be included within the scope of computer-readable media.

[0049]总之,以上所述仅为本发明技术方案的较佳实施例而已,并非用于限定本发明的保护范围。 [0049] In summary, the technical solutions described above are only preferred embodiments of the present invention but are not intended to limit the scope of the present invention. 凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 Any modification within the spirit and principle of the present invention, made, equivalent substitutions, improvements, etc., should be included within the scope of the present invention.

Claims (6)

1.一种基于多核芯片的电压降低方法,其特征在于,所述方法包括如下步骤:检测每个内核的电压以及运行的线程; 判断该内核的电压是否超过电压阈值; 如该内核的电压超过电压阈值,则减少该内核的线程数量。 1. A method of reducing the voltage based on a multicore chip, characterized in that, said method comprising the steps of: detecting a voltage of each core and running threads; core determining whether the voltage exceeds a threshold voltage; if the voltage exceeds a core voltage threshold, and decreases the number of threads of the core.
2.根据权利要求1所述的方法,其特征在于,所述方法还包括: 将减少的该内核的线程分配到其他内核中运行。 2. The method according to claim 1, characterized in that, said method further comprising: reducing the thread assigned to other kernel running in the kernel.
3.根据权利要求1所述的方法,其特征在于,所述方法还包括: 将减少的该内核的线程平均分配到其他内核中运行。 3. The method according to claim 1, characterized in that, said method further comprising: reducing the average core assigned to other threads running in the kernel.
4.一种基于多核芯片的电压降低系统,其特征在于,所述系统包括: 检测单元,用于检测每个内核的电压以及运行的线程; 判断单元,用于判断该内核的电压是否超过电压阈值; 减少单元,用于如该内核的电压超过电压阈值,则减少该内核的线程数量。 A system based on a voltage decrease multicore chip, characterized in that the system comprises: detecting means for detecting a voltage of each core and running threads; determining means for determining whether the voltage exceeds the voltage of the core threshold; reduction unit for the core as the voltage exceeds the threshold voltage, and decreases the number of threads of the core.
5.根据权利要求4所述的系统,其特征在于,所述系统还包括: 分配单元,用于将减少的该内核的线程分配到其他内核中运行。 5. The system according to claim 4, characterized in that, said system further comprising: a dispensing unit, for reducing the thread assigned to other kernel running in the kernel.
6.根据权利要求4所述的系统,其特征在于,所述系统还包括: 均分单元,用于将减少的该内核的线程平均分配到其他内核中运行。 6. The system according to claim 4, characterized in that the system further comprises: sharing unit for reducing the average core assigned to other threads running in the kernel.
CN201610600313.XA 2016-07-27 2016-07-27 Voltage reduction method and system based on multi-core chip CN106292996A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018018449A1 (en) * 2016-07-27 2018-02-01 李媛媛 Multi-core chip-based voltage reduction method and system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030184271A1 (en) * 2000-12-20 2003-10-02 Kazuo Aisaka Eletronic circuit of low power consumption, and power consumption reducing method
CN101076770A (en) * 2004-09-28 2007-11-21 英特尔公司 Method and apparatus for varying energy per instruction according to the amount of available parallelism
CN101341456A (en) * 2005-12-21 2009-01-07 Nxp股份有限公司 Schedule based cache/memory power minimization technique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030184271A1 (en) * 2000-12-20 2003-10-02 Kazuo Aisaka Eletronic circuit of low power consumption, and power consumption reducing method
CN101076770A (en) * 2004-09-28 2007-11-21 英特尔公司 Method and apparatus for varying energy per instruction according to the amount of available parallelism
CN101341456A (en) * 2005-12-21 2009-01-07 Nxp股份有限公司 Schedule based cache/memory power minimization technique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018018449A1 (en) * 2016-07-27 2018-02-01 李媛媛 Multi-core chip-based voltage reduction method and system

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