CN106276777A - The processing method of MEMS substrate - Google Patents
The processing method of MEMS substrate Download PDFInfo
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- CN106276777A CN106276777A CN201510244272.0A CN201510244272A CN106276777A CN 106276777 A CN106276777 A CN 106276777A CN 201510244272 A CN201510244272 A CN 201510244272A CN 106276777 A CN106276777 A CN 106276777A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
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Abstract
A kind of processing method of MEMS substrate; before substrate is corroded; by forming the second mask layer and the 3rd mask layer respectively in the side of substrate and the back side; owing to the side, edge of substrate is effectively protected by the second mask layer; can be prevented effectively from the edge side etch of substrate while substrate is corroded thus cause substrate edge that unfilled corner occurs; in technique subsequently, substrate is not easy fragment, improves the yield rate of product.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly to the processing method of a kind of MEMS substrate.
Background technology
MEMS (Micro Electro Mechanical Systems, microelectromechanical systems) is to utilize integrated electricity
Road manufacturing technology and micro-processing technology process circuit even micro structure, microsensor, microactrator, control
Interface, communication and power supply etc. manufacture the miniature integrated system on one or more chip.MEMS manufactures
Technology depends not only upon IC technique, relys more on micro-processing technology.Micro-processing technology includes the body micro Process of silicon
Technology, surface micro-fabrication technology and special micro-processing.Body micro-processing technology refers to the thickness along silicon substrate
The technique that silicon substrate is performed etching by degree direction, including wet etching and dry etching, is to realize three dimensional structure
Important method.In order to obtain the structure of needs, etching is only carried out at the regional area of silicon chip, non-etched area
Territory must deposit mask layer (barrier layer) protection, and first mask layer is carried out selective etch, makes to be carved
The silicon in erosion region comes out, and then uses wet etching or dry etching to corrode silicon substrate.With
General IC technique is different, and corrosion depth can reach hundreds of micron, even silicon slice corrosion break-through.Right
When mask layer carries out selective etch, the edge sidewall of silicon chip, because photoresist cannot be coated, causes silicon chip limit
The mask layer of edge sidewall is also etched away.So when silicon substrate is carried out body micro Process, the edge side of silicon chip
Wall also can be corroded simultaneously, causes the edge of silicon chip many little unfilled corners occur, compared with entire silicon chip
Relatively, with the silicon chip of little unfilled corner in technique subsequently, it is easy to fragment, the decrease in yield of product is caused.
Summary of the invention
Based on this, it is necessary to provide the processing of the MEMS substrate of a kind of yield rate that can be effectively improved product
Method.
A kind of processing method of MEMS substrate, including step:
Thering is provided substrate, described substrate includes front, side and the back side；
The first mask layer is formed in the front of described substrate；
Described first mask layer is patterned and exposes the partial elevational of described substrate；
Form the second mask layer in the side of described substrate, form the 3rd mask layer at the back side of described substrate；
The partial elevational exposing described substrate corrodes.
Wherein in an embodiment, by plasma enhanced chemical vapor deposition technique at described substrate
Front forms the first mask layer.
Wherein in an embodiment, by plasma enhanced chemical vapor deposition technique at described substrate
Side forms the second mask layer and forms the 3rd mask layer at the back side of described substrate.
Wherein in an embodiment, form described first mask layer, the second mask layer and the 3rd mask layer
Material includes silicon dioxide.
Wherein in an embodiment, the thickness of described first mask layer is 0.5 micron～2 microns.
Wherein in an embodiment, the partial elevational exposing described substrate utilizes potassium hydroxide or tetramethyl
Ammonium hydroxide carries out wet etching.
Wherein in an embodiment, the partial elevational exposing described substrate carries out deep reaction ion etching.
Wherein in an embodiment, the material of described substrate includes semi-conducting material.
The processing method of above-mentioned MEMS substrate, before corroding substrate, by the side of substrate and the back of the body
Face forms the second mask layer and the 3rd mask layer respectively, owing to the side, edge of substrate is carried out by the second mask layer
Effectively protection, can be prevented effectively from the edge side etch of substrate while substrate is corroded thus
Causing substrate edge unfilled corner occur, in technique subsequently, substrate is not easy fragment, improves the yield rate of product.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, describe below
In accompanying drawing be only some embodiments of the present invention, for those of ordinary skill in the art, do not paying
On the premise of going out creative work, it is also possible to obtain the accompanying drawing of other embodiments according to these accompanying drawings.
Fig. 1 is the flow chart of the processing method of MEMS substrate；
Fig. 2 is the schematic diagram of substrate；
Fig. 3 is the schematic diagram forming the first mask layer in substrate front；
Fig. 4 be the first mask layer graphical after schematic diagram；
Fig. 5 is the schematic diagram after forming the second mask layer and the 3rd mask layer；
Fig. 6 is the schematic diagram after the partial elevational etching that substrate exposes.
Detailed description of the invention
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.
Accompanying drawing gives presently preferred embodiments of the present invention.But, the present invention can come real in many different forms
Existing, however it is not limited to embodiment described herein.On the contrary, providing the purpose of these embodiments is to make this
The understanding of disclosure of the invention content is more thorough comprehensively.
Unless otherwise defined, all of technology used herein and scientific terminology and the technology belonging to the present invention
The implication that the technical staff in field is generally understood that is identical.The art used the most in the description of the invention
Language is intended merely to describe the purpose of specific embodiment, it is not intended that limit the present invention.Art used herein
Language "and/or" includes the arbitrary and all of combination of one or more relevant Listed Items.
MEMS (Micro Electro Mechanical Systems, microelectromechanical systems) is to utilize integrated electricity
Road manufacturing technology and micro-processing technology process circuit even micro structure, microsensor, microactrator, control
Interface, communication and power supply etc. manufacture the miniature integrated system on one or more chip (substrate).Along with
The development of MEMS technology, the pressure transducer utilizing MEMS technology to make be widely used in auto industry,
The various fields such as biomedicine, Industry Control, the energy and semi-conductor industry.A kind of MEMS base below
The processing method of sheet.
Below in conjunction with the accompanying drawings, the detailed description of the invention of the present invention is described in detail.
Fig. 1 is the flow chart of the processing method of MEMS substrate.
A kind of processing method of MEMS substrate, including step:
Step S100: providing substrate 100, substrate 100 includes front 110, side 120 and the back side 130.Base
Sheet 100 can be semi-conducting material, such as, can be silicon material.Fig. 2 is the schematic diagram of substrate.
Step S200: form the first mask layer 210 in the front 110 of substrate 100.Thermal oxide side can be used
Method deposits, such as normal pressure thermal oxide, low heat pressuring oxidation and hot high pressure oxidation etc.；Physical deposition can also be used,
Such as vacuum evaporation, sputter coating and molecular beam epitaxy etc.；Can also use chemical vapor deposition (CVD,
Chemical Vapor Deposition), such as Films Prepared by APCVD, low-pressure chemical vapor phase deposition and ion
Body strengthens chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor
Deposition).When using the front 110 of PECVD deposit substrate 100, side 120 also can deposit and enclose
Thin film, the back side 130 is then substantially without enclosing.As used PECVD deposit to form the first mask layer
210, then make the side 120 of substrate 100 also can enclose thin film due to the characteristic of PECVD deposit.
Fig. 3 is the schematic diagram forming the first mask layer in substrate front.
After having deposited the first mask layer 210 on front 110, the first mask layer 210 can be carried out selectivity
Etching is graphically changed.
Step S300: the first mask layer 210 is patterned and exposes the partial elevational 112 of substrate 100.
After the first mask layer 210 on the front 110 of substrate 100 coats photoresist, by exposed and developed,
First mask layer 210 is carried out selective etch and forms figure.First mask layer 210 is being carried out selectivity
During etching, the edge sidewall (side 120) of substrate 100, because photoresist cannot be coated, causes substrate 100
This thin film of edge sidewall (side 120) is also etched away.The thickness of the first mask layer is 0.5 micron～2 micro-
Rice, material can comprise semiconducting compound, such as, can be oxide or the nitride of silicon, can be two
Silicon oxide.Fig. 4 be the first mask layer graphical after schematic diagram.
After the first mask layer 210 on front 110 is graphical, need to be formed sediment in the side 120 of substrate 100
Long-pending thin film work is to protect the edge sidewall (side 120) of substrate 100.
Step S400: form the second mask layer 220 in the side 120 of substrate 100, at the back side of substrate 100
130 form the 3rd mask layer 230.Due to the characteristic of PECVD deposit, PECVD deposit can be used same
Time form the second mask layer 220 and the 3rd mask layer 230.Is formed sediment facing to deposit source in the back side 130 of substrate 100
Long-pending, thin film, the back side 130 and side 120 are enclosed then essentially without deposit in the front 110 of substrate 100
Can deposit and enclose thin film and form the second mask layer 220 and the 3rd mask layer 230 respectively.Second mask layer 220
Can be the same with the first mask layer 210 with the material of the 3rd mask layer 230, material can comprise semiconductor transformation
Compound, such as, can be oxide or the nitride of silicon, can be silicon dioxide.Fig. 5 is to form second to cover
Schematic diagram after film layer and the 3rd mask layer.
The edge sidewall (side 120) of substrate 100 is enclosed after the second mask layer 220 is effectively protected, can
To carry out follow-up substrate 100 pattern etching.
Step S500: partial elevational 112 (the first graphical rear exposure of mask layer 210 that substrate 100 is exposed
Substrate 100 partial elevational) corrode, obtain etch pattern 140.Can be by substrate 100 be exposed
Part 112 front utilize potassium hydroxide (KOH) or Tetramethylammonium hydroxide (TMAH) to carry out wet method
Corrosion, it is also possible to the partial elevational 112 exposing substrate 100 carries out deep reaction ion etching (DRIE).The
The material relationships of one mask layer 210 is to substrate 100 etching technics, if the first mask layer 210 is titanium dioxide
Silicon material, generally uses above-mentioned etching technics to perform etching substrate 100.Fig. 6 is the part that substrate exposes
Schematic diagram after the etching of front.
The processing method being appreciated that above-mentioned MEMS substrate, only describes some key steps, does not represent
The institute of the processing of MEMS substrate or manufacture is in steps.Diagram in Fig. 2～Fig. 6 is also to add MEMS substrate
The simple examples of some primary structures of device in work or manufacture process, does not represent the entire infrastructure of device.
The processing method of above-mentioned MEMS substrate, before corroding substrate, by the side of substrate and the back of the body
Face forms the second mask layer and the 3rd mask layer respectively, owing to the side, edge of substrate is carried out by the second mask layer
Effectively protection, can be prevented effectively from the edge side etch of substrate while substrate is corroded thus
Causing substrate edge unfilled corner occur, in technique subsequently, substrate is not easy fragment, improves the yield rate of product.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed,
But therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for this area
Those of ordinary skill for, without departing from the inventive concept of the premise, it is also possible to make some deformation and
Improving, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended
Claim is as the criterion.
Claims (8)
1. the processing method of a MEMS substrate, it is characterised in that include step:
Thering is provided substrate, described substrate includes front, side and the back side；
The first mask layer is formed in the front of described substrate；
Described first mask layer is patterned and exposes the partial elevational of described substrate；
Form the second mask layer in the side of described substrate, form the 3rd mask layer at the back side of described substrate；
The partial elevational exposing described substrate corrodes.
The processing method of MEMS substrate the most according to claim 1, it is characterised in that pass through
Gas ions strengthens chemical vapor deposition method and forms the first mask layer in the front of described substrate.
The processing method of MEMS substrate the most according to claim 1, it is characterised in that pass through
Gas ions strengthens chemical vapor deposition method and forms the second mask layer in the side of described substrate and at described substrate
The back side formed the 3rd mask layer.
The processing method of MEMS substrate the most according to claim 1, it is characterised in that form institute
The material stating the first mask layer, the second mask layer and the 3rd mask layer includes silicon dioxide.
The processing method of MEMS substrate the most according to claim 1, it is characterised in that described first
The thickness of mask layer is 0.5 micron～2 microns.
The processing method of MEMS substrate the most according to claim 1, it is characterised in that to described base
The partial elevational that sheet exposes utilizes potassium hydroxide or Tetramethylammonium hydroxide to carry out wet etching.
The processing method of MEMS substrate the most according to claim 1, it is characterised in that to described base
The partial elevational that sheet exposes carries out deep reaction ion etching.
The processing method of MEMS substrate the most according to claim 1, it is characterised in that described substrate
Material include semi-conducting material.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510244272.0A CN106276777A (en) | 2015-05-13 | 2015-05-13 | The processing method of MEMS substrate |
| PCT/CN2016/081515 WO2016180310A1 (en) | 2015-05-13 | 2016-05-10 | Processing method for mems substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510244272.0A CN106276777A (en) | 2015-05-13 | 2015-05-13 | The processing method of MEMS substrate |
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| CN106276777A true CN106276777A (en) | 2017-01-04 |
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| WO (1) | WO2016180310A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108083223A (en) * | 2018-01-15 | 2018-05-29 | 杭州臻镭微波技术有限公司 | The radio frequency micro-system and its manufacturing method of a kind of silicon based three-dimensional Manufacturing resource |
| CN111874861A (en) * | 2020-05-20 | 2020-11-03 | 北京协同创新研究院 | Method for enhancing adhesion of parylene film and silicon |
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| CN103373700A (en) * | 2012-04-17 | 2013-10-30 | 英飞凌科技股份有限公司 | Methods for producing a cavity within a semiconductor substrate |
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| CN104450549B (en) * | 2014-07-03 | 2017-03-15 | 甘肃农业大学 | One plant of resistance to matrine Rhizobium strains and its application and the antipollution nitragin prepared with which |
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Patent Citations (5)
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| US6857501B1 (en) * | 1999-09-21 | 2005-02-22 | The United States Of America As Represented By The Secretary Of The Navy | Method of forming parylene-diaphragm piezoelectric acoustic transducers |
| CN102491260A (en) * | 2011-12-31 | 2012-06-13 | 上海先进半导体制造股份有限公司 | Method for manufacturing flow sensor by etch self-stopping technology |
| CN103373700A (en) * | 2012-04-17 | 2013-10-30 | 英飞凌科技股份有限公司 | Methods for producing a cavity within a semiconductor substrate |
| CN102701140A (en) * | 2012-05-06 | 2012-10-03 | 西北工业大学 | Method for processing suspended silicon thermistor |
| CN103972173A (en) * | 2013-01-30 | 2014-08-06 | 中芯国际集成电路制造(上海)有限公司 | CMOS (complementary metal oxide semiconductor) transistor forming method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108083223A (en) * | 2018-01-15 | 2018-05-29 | 杭州臻镭微波技术有限公司 | The radio frequency micro-system and its manufacturing method of a kind of silicon based three-dimensional Manufacturing resource |
| CN111874861A (en) * | 2020-05-20 | 2020-11-03 | 北京协同创新研究院 | Method for enhancing adhesion of parylene film and silicon |
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| Publication number | Publication date |
|---|---|
| WO2016180310A1 (en) | 2016-11-17 |
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Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant before: Wuxi CSMC Semiconductor Co., Ltd. |
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Application publication date: 20170104 |
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