CN106257435A - A kind of SPDIF Asynchronous Reception frequency coupling solution - Google Patents

Abstract

nullThe invention discloses a kind of SPDIF Asynchronous Reception frequency coupling solution，It is applied to the audio processing chip design field of SPDIF input interface，When can solve audio chip reception SPDIF audio stream input by this technology，SPDIF audio stream and the audio chip deviation to the clock that reply SPDIF audio stream processes is caused owing to SPDIF audio stream is asynchronous input，So that external SPDIF audio stream can intactly receive and process，This technical method relatively simple and resource and technology well solve this problem，Make audio processing chip can have SPDIF input concurrently simultaneously、Input interface，And also can be applied in combination with other output audio interface such as I2S etc.，Compared with cannot accomplishing to have SPDIF input interface with most audio processing chips on the market，The function and application scope of the audio chip being applied to this technology greatly strengthens，More products application scheme can be provided，Significantly enhance the market competitiveness of audio chip.

Description

A kind of SPDIF Asynchronous Reception frequency coupling solution

Technical field

The present invention relates to audio area asynchronous clock frequency processing field, processing owing to SPDIF audio frequency BMC code stream and audio chip system agree SPDIF process this difficult point of associated clock frequency departure for SPDIF audio frequency this Asynchronous Reception of BMC code stream, the perfect stomach SPDIF audio frequency BMC code stream that solves causes frequency departure problem as input.Hardware resource involved in the present invention is simple, can be achieved with by relatively simple designing technique.

Background technology

SoC full name is (System on Chip), means SOC(system on a chip), also referred to as systems-on-a-chip, be by integrated for system core parts on one chip.

SPDIF(Sony/Philips Digital Interconnect Format) digital music interface, be Sony and Philips two giants in the eighties it is a kind of digital signal coffret out customized in general household equipment, realizes digital signal asynchronous transmission with cost than relatively low hardware.

Audio Processing SoC chip refers to be integrated with the System on Chip/SoC of conventional audio frequency Peripheral Interface such as I2S, SPDIF etc., it is common that audio data is carried out certain audio effect processing, is then exported by distinct interface.For SPDIF audio frequency BMC code stream, use Asynchronous Reception processing mode, thus result in this inevitable offset issue of the clock for asynchronous SPDIF audio frequency BMC code stream and audio processing chip clock, the most more complicated generally for asynchronous clock drift correction technology, and need great amount of hardware resources, it is difficult to perfection and realizes.Thus overwhelming majority audio processing chips generally the most on the market, have SPDIF input, output interface the most simultaneously concurrently, typically have SPDIF input interface, thus resulted in audio processing chip application and limited.

Summary of the invention

The present invention proposes a kind of SPDIF Asynchronous Reception frequency coupling solution, use less hardware resource, after the fairly simple Clock Extraction achieving SPDIF input audio frequency BMC code stream and frequency multiplication, it is applied on audio processing chip as system clock, solves SPDIF audio frequency BMC code stream as inevitable clock jitter problem during input.

The present invention is to solve SPDIF audio frequency BMC code stream input clock deviation by following technical proposals:

Hardware components of the present invention comprises:

101, SPDIF Asynchronous Reception clock recovery extraction unit；

102, SPDIF receives clock multiplier unit；

103, unit is selected with system clock after SPDIF receives clock multiplier；

2, the whole procedure of clock frequency coupling is as follows:

201, the SPDIF audio frequency BMC code stream of external input is carried out resolving sampling by SPDIF Asynchronous Reception clock recovery unit, recovers the clock of SPDIF code stream；

202, the SPDIF code stream clock recovered SPDIF Asynchronous Reception clock recovery unit by SPDIF reception clock multiplier unit carries out frequency multiplication；

203, unit is selected to gate with system clock after clock and system clock receive clock multiplier by SPDIF after frequency multiplication, when there being SPDIF audio stream to input, as system work clock after the clock multiplier that gating SPDIF audio code stream recovers, it is added in SPDIF, I2S etc. module, thus reaches frequency and unanimously mate.

3, method according to claim 1, wherein, is extracted as the essential elements of this patent method for the clock recovery of SPDIF code stream:

301, SPDIF audio frequency BMC code stream is resolved, extraction recovers fundamental clock, the clock recovered needs to carry out frequency multiplication according to suitable multiplier parameter, thus draw the clock consistent with system clock frequency, and with this clock and before system clock gate, the principle of gating is when there being SPDIF audio frequency BMC code stream input, using recovering the clock after also frequency multiplication as system clock, is applied in the modules such as SPDIF, I2S；

302, clock multiplier unit, needs are configurable, it is possible to the correct suitable multiplier parameter of configuration, and SPDIF audio frequency BMC code stream recovers the clock multiplier extracted, alternative as system clock.

Accompanying drawing explanation

Fig. 1 is the concrete scheme schematic diagram that a present invention is applied on a audio processing chip.

Detailed description of the invention

In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing 1 practical embodiments, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.

See Fig. 1, provide a kind of SPDIF in one embodiment and receive audio frequency BMC code stream frequency departure solution.The method includes:

Step 201, the SPDIF audio frequency BMC code stream of external input is carried out resolving sampling, recovers the clock of SPDIF code stream by SPDIF Asynchronous Reception clock recovery unit；

Concrete, by input SPDIF audio frequency BMC code stream is resolved, resolve the fundamental clock extracting input SPDIF code stream, such as bit clock BCLK by the system dominant frequency of chip itself, parse the multiplier parameter of correspondence simultaneously；

202, the SPDIF code stream clock recovered SPDIF Asynchronous Reception clock recovery unit by SPDIF reception clock multiplier unit carries out frequency multiplication；

By the configuration to multiplier unit, parsed clock by 201 and obtain the alternative clock of system clock through frequency multiplication；

203, unit is selected to gate with system clock after clock and the alternative clock of system receive clock multiplier by SPDIF after frequency multiplication, when there being SPDIF audio stream to input, as system work clock after the clock multiplier that gating SPDIF audio code stream recovers, it is added in SPDIF, I2S etc. module, thus reaches frequency and unanimously mate.

3, method according to claim 1, wherein, is extracted as the essential elements of this patent method for the clock recovery of SPDIF code stream:

301, SPDIF audio frequency BMC code stream is resolved, extraction recovers fundamental clock, the clock recovered needs to carry out frequency multiplication according to suitable multiplier parameter, thus draw the clock consistent with system clock frequency, and with this clock and before system clock gate, the principle of gating is when there being SPDIF audio frequency BMC code stream input, using recovering the clock after also frequency multiplication as system clock, is applied in the modules such as SPDIF, I2S；

302, clock multiplier unit, needs are configurable, it is possible to the correct suitable multiplier parameter of configuration, and SPDIF audio frequency BMC code stream recovers the clock multiplier extracted, alternative as system clock.

Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to make some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.

Claims (3)

1. a SPDIF Asynchronous Reception frequency coupling solution, comprises with lower part:

101, SPDIF Asynchronous Reception clock recovery extraction unit；

102, SPDIF receives clock multiplier unit；

103, unit is selected with system clock after SPDIF receives clock multiplier.

Method the most according to claim 1, the whole procedure of clock frequency coupling is as follows:

201, the SPDIF audio frequency BMC code stream of external input is carried out resolving sampling by SPDIF Asynchronous Reception clock recovery unit, recovers the clock of SPDIF code stream；

202, the SPDIF code stream clock recovered SPDIF Asynchronous Reception clock recovery unit by SPDIF reception clock multiplier unit carries out frequency multiplication；

203, unit is selected to gate with system clock after clock and system clock receive clock multiplier by SPDIF after frequency multiplication, when there being SPDIF audio stream to input, as system work clock after the clock multiplier that gating SPDIF audio code stream recovers, it is added in SPDIF, I2S etc. module, thus reaches frequency and unanimously mate.

Method the most according to claim 1, wherein, is extracted as the essential elements of this patent method for the clock recovery of SPDIF code stream:

301, SPDIF audio frequency BMC code stream is resolved, extraction recovers fundamental clock, the clock recovered needs to carry out frequency multiplication according to suitable multiplier parameter, thus draw the clock consistent with system clock frequency, and with this clock and before system clock gate, the principle of gating is when there being SPDIF audio frequency BMC code stream input, using recovering the clock after also frequency multiplication as system clock, is applied in the modules such as SPDIF, I2S；

302, clock multiplier unit, needs are configurable, it is possible to the correct suitable multiplier parameter of configuration, and SPDIF audio frequency BMC code stream recovers the clock multiplier extracted, alternative as system clock.