CN106252310B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN106252310B CN106252310B CN201610387453.3A CN201610387453A CN106252310B CN 106252310 B CN106252310 B CN 106252310B CN 201610387453 A CN201610387453 A CN 201610387453A CN 106252310 B CN106252310 B CN 106252310B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 230000000149 penetrating effect Effects 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
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- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 6
- 230000002411 adverse Effects 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 229910002601 GaN Inorganic materials 0.000 description 10
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 238000009826 distribution Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 239000010936 titanium Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
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- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- Ceramic Engineering (AREA)
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Abstract
The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: preparing a semiconductor layer on one of the surfaces of a substrate, the semiconductor layer including an active region and a passive region outside the active region; a plurality of sources, a plurality of gates and a plurality of drains located within the active region; a source pad connected to the source; a gate pad connected to the gate; a drain pad connected to the drain; a first via hole in the passive region, penetrating the substrate and the semiconductor layer, and electrically connecting the ground electrode to the source pad; and a second via hole located in the active region, penetrating the substrate and the semiconductor layer, and electrically connecting the ground electrode and the source electrode. The embodiment of the invention can reduce the overall parasitic inductance of the device, reduce the adverse effect of the concentrated opening of the existing semiconductor device on the heat dissipation of the device, and is beneficial to improving the gain and the output power of the device.
Description
Technical Field
The invention relates to the field of manufacturing methods of microelectronics and semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
The gallium nitride semiconductor material has the obvious advantages of large forbidden bandwidth, high electron saturation drift rate, high breakdown field strength, high temperature resistance and the like, is more suitable for manufacturing electronic devices with high temperature, high voltage, high frequency and high power compared with the first generation semiconductor silicon and the second generation semiconductor gallium arsenide, has wide application prospect, and becomes a hotspot of current semiconductor industry research.
Gallium nitride High Electron Mobility Transistor (HEMT) is a gallium nitride device formed by using two-dimensional electron gas at an AlGaN/GaN heterojunction, and can be applied to the fields of high frequency, high voltage and high power. Because the two-dimensional electron gas has higher mobility and saturation drift rate, the depletion type gallium nitride HEMT device is usually manufactured by utilizing the normally open characteristic of a two-dimensional electron gas channel, and is suitable for the high-frequency application fields of wireless communication and the like. In the process of packaging a gan device, a via structure is usually used to improve the gain of the device and reduce the ground inductance. This structure is generally formed by introducing a via hole (substrate back-side grounded) from the substrate back side, which penetrates the substrate and the nitride semiconductor epitaxial layer to the source, by etching, and then filling the via hole with a metal to connect the source and the grounded substrate back side to reduce the source-to-ground inductance.
At present, the through holes of the gallium nitride device are distributed mainly in two forms, wherein one form is that the through holes are arranged below the source electrodes of the active regions, so that the source electrodes in each active region are directly grounded through the through holes, the distance from the source electrodes in the active regions to the ground is reduced, and the grounding inductance is reduced. However, the through holes are all arranged in the active region in the position distribution manner of the through holes, which causes the heat dissipation performance of the device to be poor, because the active region is a region where heat of the device is concentrated, the through hole structure is usually a hollow structure, which may destroy the heat dissipation performance of the substrate, and the through holes are all arranged in the active region, which may greatly affect the heat dissipation of the device, and limit the power design of the device. Another form is to open a via under the source pad of the inactive region. The through holes are arranged in the passive area in a position distribution mode, so that the influence of the through holes on the heat dissipation of the device is reduced. However, the through holes are all located on the same side opposite to the drain bonding pad, so that the current in the active area flows in the same direction and is not dispersed, the mutual inductance generated by the metal finger insertion parts of the active area is strongest, the current density on a single finger insertion part is largest, and the heat generation amount of the active area is highest and concentrated when the device works; secondly, the distance from the source in the active region to the ground is increased, that is, the grounding inductance of the source is increased, thereby affecting the performance of the device, such as gain.
Disclosure of Invention
In view of the above, it is an object of the embodiments of the present invention to provide a semiconductor device and a method of manufacturing the same to improve the above-mentioned problems.
An embodiment of the present invention provides a semiconductor device, including: preparing a semiconductor layer on one of the surfaces of a substrate, the semiconductor layer including an active region and a passive region outside the active region; a plurality of sources, a plurality of gates and a plurality of drains located within the active region; a source pad connected to the source; a drain pad connected to the drain; preparing a ground electrode on the other surface of the substrate; a first via hole in the passive region, penetrating the substrate and the semiconductor layer, and electrically connecting the ground electrode to the source pad; and a second via hole located in the active region, penetrating the substrate and the semiconductor layer, and electrically connecting the ground electrode and the source electrode.
Preferably, a second through hole is formed below each source electrode in each active region, the positions of the second through holes on the two adjacent source electrodes on the respective source electrode, which are opposite to the source electrode, are different from each other, wherein one of the two second through holes on any two adjacent source electrodes is arranged below one end, close to the source electrode pad, of the source electrode where the second through hole is located, and the other second through hole is arranged below one end, close to the drain electrode pad, of the source electrode where the second through hole is located.
Preferably, an etching barrier layer material is arranged above the second through hole formed below the source electrode to form an electrical connection with the source electrode.
Preferably, each source electrode in the active region is connected with an independent source electrode bonding pad, and one second through hole is formed below one end, close to the drain electrode bonding pad, of each source electrode. Preferably, one first through hole is formed below each source bonding pad.
Preferably, a second through hole is formed below each source, and the positions of the second through holes on any two adjacent sources on the respective source where the second through holes are located are different from each other with respect to the source where the second through holes are located, wherein one of the two second through holes on any two adjacent sources is located below one end, close to the drain pad, of the source where the second through hole is located, and the other second through hole is located below the center of the source where the second through hole is located.
Preferably, at least two first through holes are formed below each source bonding pad.
Preferably, any two adjacent source electrodes are provided with a second through hole with different numbers, wherein one second through hole is provided below the middle position of one of any two adjacent source electrodes, and one second through hole is provided below one end of the other source electrode close to the source electrode bonding pad and one second through hole is provided below one end of the other source electrode close to the drain electrode bonding pad.
The manufacturing method of the semiconductor device provided by the embodiment of the invention comprises the following steps:
preparing a semiconductor layer on one surface of a substrate;
forming an active region and a passive region on the semiconductor layer;
forming a source electrode, a drain electrode and a grid electrode in the active region;
preparing interconnection metal on the semiconductor layer to form a source electrode bonding pad, a drain electrode bonding pad and a grid electrode bonding pad, so that the source electrode bonding pad is electrically connected with the source electrode, the grid electrode bonding pad is electrically connected with the grid electrode, and the drain electrode bonding pad is electrically connected with the drain electrode;
forming a first through hole penetrating through the substrate and the semiconductor layer to the source bonding pad and forming a second through hole penetrating through the substrate and the semiconductor layer to the source from the other surface of the substrate; and
and preparing a ground electrode metal from the other surface of the substrate, wherein the source pad and the source electrode are electrically connected to the ground electrode through the first via and the second via, respectively.
Preferably, in the process of forming a source electrode, a drain electrode and a gate electrode in the active region, a blank region is formed on the surface of the semiconductor layer above the second through hole in the active region through a patterning process; meanwhile, in the process of preparing interconnection metal on the semiconductor layer to form a source electrode bonding pad, a grid electrode bonding pad and a drain electrode bonding pad, etching barrier layer material on the blank area preparation to form electric connection with the source electrode, wherein the etching barrier layer material is located above the second through hole. The etching barrier layer material has higher etching selection ratio than the substrate and the semiconductor layer, and can ensure that the through hole only penetrates through the substrate and the semiconductor layer and stops at the etching barrier layer when being etched, and the front electrode metal is not damaged or penetrated. The etch barrier material may be formed of one or a combination of more than one of titanium (Ti), nickel (Ni), gold (Au), platinum (Pt), tungsten (W), copper (Cu), and the like, or an alloy.
Compared with the prior art, the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention have the advantages that the first through hole and the second through hole are respectively arranged below the source electrode pad and the source electrode in the active region, so that the through hole structures are not required to be completely arranged in the active region, the number of the holes in the active region is reduced, the distance between the holes is increased (more dispersed), the adverse effect on the heat dissipation of the device caused by concentrated holes in the active region is reduced, and the output power of the device is favorably improved. Secondly, because the hole is formed below the source electrode bonding pad of the passive region, the requirement of the number of the holes for grounding the source electrode is ensured under the condition that the heat dissipation effect on the active region is as small as possible.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1(a) is a schematic view of a semiconductor device according to a first embodiment of the present invention.
FIG. 1(b) is a sectional view taken along the line A-A' in FIG. 1 (a).
FIG. 1(c) is a sectional view taken along the line B-B' in FIG. 1 (a).
Fig. 2(a) is a schematic diagram of a semiconductor device according to a second embodiment of the present invention.
FIG. 2(b) is a sectional view taken along the line A-A' in FIG. 2 (a).
FIG. 2(c) is a sectional view taken along the line B-B' in FIG. 2 (a).
Fig. 3(a) is a schematic diagram of a semiconductor device according to a third embodiment of the present invention.
FIG. 3(b) is a sectional view taken along the line A-A' in FIG. 3 (a).
Fig. 4(a) is a schematic view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 4(b) is a sectional view taken along the line A-A' in FIG. 4 (a).
Fig. 5 is a schematic diagram of a semiconductor device according to a fifth embodiment of the present invention.
Fig. 6 is a schematic diagram of a semiconductor device according to a sixth embodiment of the present invention.
Fig. 7 is a schematic view of a semiconductor device according to a seventh embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Referring to fig. 1(a) -1 (c), a semiconductor device 100 according to a first embodiment of the present invention includes a semiconductor layer 81 formed on one surface of a substrate 61. The substrate may be one of silicon carbide (SiC), sapphire (Al2O3), silicon (Si), gallium arsenide (GaAS), gallium nitride (GaN), and the like. The semiconductor layer 81 may be formed of one or a combination of more than one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, and indium phosphide. The semiconductor layer 81 includes an active region 5 and an inactive region located outside the active region 5. The active region 5 may be of a closed form. The semiconductor device 100 further includes a plurality of sources 11, a plurality of drains 21, and a plurality of gates 31 in the active region 5. Preferably, the source electrode 11 and the drain electrode 21 are ohmic contact electrodes. The gate 31 is located in the active region 5 and between the source 11 and the drain 21, and is distributed in an interdigital shape.
The semiconductor device 100 further includes a source pad 13, a drain pad 22, and a gate pad 32. The source bonding pad 13 is used as interconnection metal of the source electrodes 11, and is used for realizing interconnection between the source electrodes 11. The drain pad 22 serves as an interconnection metal of the drains 21 for interconnecting the drains 21 with each other. The gate pad 32 serves as an interconnection metal of the gate electrodes 31 for realizing interconnection of the gate electrodes 31 with each other. Preferably, in this embodiment, the source pad 13, the drain pad 22, and the gate pad 32 are disposed in an inactive area outside the active area 5. The sources 11 in the active region 5 are connected to respective source pads 13 by metal bridging elements 12 (also called "air bridges"). Preferably, the metal bridging element 12 is a source bridging metal. The drains 21 in the active area 5 are directly connected to respective drain pads 22. The gate electrode 31 may also be directly connected to the gate pad 32
In addition, the semiconductor device 100 further includes a first via 41 located in the inactive region and penetrating through the substrate 61 and the semiconductor layer 81 up to the source pad 13 to be electrically connected to the source pad 13; and a second via 42 located in the active region 5 and penetrating through the substrate 61 and the semiconductor layer 81 to the source electrode 11 and electrically connected to the source electrode 11. In this way, the source pad 13 and the source electrode 11 in the active region 5 can be electrically connected to the ground electrode 71 prepared on the other surface of the substrate 61 through the first via hole 41 and the second via hole 42, respectively. In this embodiment, the cross-sectional shapes of the first through-hole 41 and the second through-hole 42 may be any regular shape or irregular shape, and preferably, the cross-sectional shapes of the first through-hole 41 and the second through-hole 42 are regular shapes such as a circle, an ellipse, or a parallel polygon (e.g., a diamond, a square, or a regular hexagon). Note that, in the present embodiment, for convenience of understanding, the shapes of the first via hole 41 and the second via hole 42 are shown in the regions corresponding to the source pad 13 and the source electrode 11, respectively. In an actual product, the first through hole 41 and the second through hole 42 do not penetrate through the source pad 13 and the source electrode 11.
In this embodiment, a second through hole 42 is formed below each source 11, and the positions of the second through holes 42 on two adjacent sources 11 below the respective source 11 are different from each other with respect to the position of the respective source. Preferably, the distribution of the positions between two adjacent second through holes 42 is as follows: the mutual distance is as large as possible. For example, in a preferred embodiment, one of the two second through holes 42 on any two adjacent source electrodes 11 is disposed below the end of the source electrode 11 on which the second through hole is located close to the source pad 13, and the other second through hole 42 is disposed below the end of the source electrode 11 on which the second through hole is located close to the drain pad 22, so that the distance between the two adjacent through holes 42 is as large as possible.
Accordingly, the method for manufacturing the semiconductor device 100 provided by the embodiment of the invention comprises the following steps:
preparing a semiconductor layer 81 on one surface of a substrate 61;
forming an active region 5 and a passive region on the semiconductor layer;
forming a source electrode 11, a drain electrode 21 and a gate electrode 31 in the active region 5, wherein the source electrode 11 and the drain electrode 21 are preferably ohmic contact electrodes;
preparing interconnection metal on the semiconductor layer to form a source bonding pad 13, a gate bonding pad 32 and a drain bonding pad 22, wherein the source bonding pad 13 can be electrically connected with the source electrode 11 through a metal bridging element 12;
forming a first via hole 41 penetrating the substrate 61 and the semiconductor layer 81 from the other surface of the substrate 61 and terminating at the source pad 13; and forming a second via 42 through the substrate 61 and the semiconductor layer 81, terminating at the source 11;
a ground electrode 71 is formed on the other surface of the substrate 61, and the source pad 13 and the source electrode 11 are electrically connected to the ground electrode 71 through the first via hole 41 and the second via hole 42, respectively. For example, the source pad 13 and the source electrode 11 may be electrically connected to the ground electrode 71 by filling a conductive material (e.g., a metal) in the first via 41 and the second via 42, or coating or preparing a conductive material on the inner walls of the first via 41 and the second via 42.
In summary, in the semiconductor device 100 provided in this embodiment, the first through hole 41 and the second through hole 42 are simultaneously and respectively disposed below the source pad 13 and the source 11 in the active region 5, so that the through hole structures do not need to be all disposed in the active region 5, the number of openings in the active region 5 is reduced, and the distance between the openings is increased (more dispersed), thereby reducing the adverse effect on the heat dissipation of the device caused by the concentrated openings in the active region 5, and facilitating to improve the output power of the device.
Secondly, due to the opening under the source pad 13 of the inactive area, the requirement of the number of openings for grounding the source 11 is ensured under the condition that the heat dissipation effect on the active area is as small as possible.
And thirdly, the positions of the holes below the source electrode 11 in the active region 5 are distributed regularly, the holes correspond to the holes below the source electrode bonding pad 13 of the passive region, the flow direction of the working current in the active region 5 is guided, and the flow direction of the current in the active region 5 is dispersed and reversed. On one hand, the local current density distribution of the active region 5 can be reduced, the concentrated heating of the device caused by large current density is reduced, and the heat distribution of the active region 5 is more uniform. On the other hand, the current flow direction of the active region 5 (source and drain) is opposite, so that the mutual inductance between the metal insertion fingers of the active region can be reduced, and the effect is better particularly under the high-frequency condition, thereby reducing the overall parasitic inductance of the device and improving the gain of the device.
Referring to fig. 2(a) -2 (c), a semiconductor device 100 according to a second embodiment of the present invention is similar to the first embodiment, except that: in the second embodiment, the semiconductor device 100 has the etching barrier material 420 above the second via 42 opened in the active region 5 to form an electrical connection with the source electrode 11. Accordingly, the second embodiment provides a method for manufacturing a semiconductor device 100, including the steps of:
preparing a semiconductor layer 81 on one surface of a substrate 61;
forming an active region 5 and an inactive region on the semiconductor layer 81;
forming a source electrode 11 and a drain electrode 21 in the active region, wherein the source electrode 11 and the drain electrode 21 are preferably ohmic contact electrodes; in this step, a blank region (a region where the etching barrier material 420 needs to be formed) is formed on the source electrode 11 in the active region 5 by a patterning process, so as to prevent the blank region from forming an ohmic contact metal.
Forming a gate electrode 31 on the semiconductor layer 81;
preparing interconnection metal on the semiconductor layer 81 to form a source pad 13, a source bridge member 12 (air bridge), a gate pad 32 and a drain pad 22, wherein the source pad 13 is electrically connected to the source electrode 11 through the source bridge member 12; at the same time, the user can select the desired position,
in the process, an etching barrier layer material 420 is formed on the blank area preparation upper interconnection metal and is electrically connected with the source electrode 11;
forming a first via hole 41 penetrating the substrate 61 and the semiconductor layer 81 from the other surface of the substrate 61 and terminating at the source pad 13; forming a second through hole 42 which penetrates through the substrate 61 and the semiconductor layer 81 and is terminated at the etching barrier layer in the source electrode 11, wherein the second through hole 42 is positioned right below the etching barrier metal material 420 area;
a ground electrode 71 is formed on the other surface of the substrate 61, and in this process, an upper ground electrode 71 is formed in the first via hole 41 and the second via hole 42, so that the source pad 13 and the source electrode 11 can be electrically connected to the ground electrode 71 through a conductive material (e.g., metal) in the first via hole 41 and the second via hole 42, respectively.
Referring to fig. 3(a) -3 (b), a semiconductor device 100 according to a third embodiment of the present invention is similar to the first embodiment, except that: in this third embodiment, each source 11 in the active region 5 is directly connected to a separate source pad 13, respectively, without an air bridge structure. In addition, in the third embodiment, the second via hole 42 opened under the source electrode 11 in the active region 5 is located under an end of the source electrode 11 close to the drain pad 22. Meanwhile, a first via hole 41 is opened under each source pad 13. Other structures and manufacturing methods are the same as those of the first embodiment, and are not described herein again.
Referring to fig. 4(a) -4 (b), a semiconductor device 100 according to a fourth embodiment of the present invention is substantially the same as the third embodiment, except that: in the fourth embodiment, the semiconductor device 100 has the etch barrier material 420 above the second via 42 corresponding to the source 11 in the active region 5 to form an electrical connection with the source 11. Other structures and manufacturing methods are the same as those of the third embodiment, and are not described herein again.
Referring to fig. 5, a semiconductor device 100 according to a fifth embodiment of the present invention is substantially the same as the first embodiment except that: in the fifth embodiment, the distance and the position between the second through holes 42 under the source 11 in the active region 5 are not limited, and are determined according to the actual requirements of the device. Preferably, in the fifth embodiment, one of the two second through holes 42 on any two adjacent source electrodes is disposed below one end of the source electrode 11 where the second through hole is located, which is close to the drain pad 22, and the other second through hole 42 is disposed below the center position of the source electrode 11 where the second through hole is located. Other structures and manufacturing methods are the same as those of the first embodiment, and are not described herein again.
Referring to fig. 6, a semiconductor device 100 according to a sixth embodiment of the present invention is substantially the same as the first embodiment except that: in the sixth embodiment, the number and size of the first through holes 41 formed below the source pad 13 are arbitrary and determined according to the actual requirements of the device. Preferably, in the sixth embodiment, at least two first through holes 41 are opened below each source pad 13. Other structures and manufacturing methods are the same as those of the first embodiment, and are not described in detail herein.
Referring to fig. 7, a semiconductor device 100 according to a seventh embodiment of the present invention is substantially the same as the sixth embodiment except that: the size, number and position of the second through holes 42 formed below the source 11 in the active region 5 are all arbitrary and determined according to the actual requirements of the device. Preferably, in the seventh embodiment, a second through hole 42 is formed below a middle position of any two adjacent source electrodes 11, and a second through hole 42 is formed below one end of the other source electrode 11 close to the source pad and one end of the other source electrode 11 close to the drain pad. Other structures and manufacturing methods are the same as those of the sixth embodiment, and are not described herein again.
It should also be noted that, in the description of the present invention, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A semiconductor device, characterized in that the semiconductor device comprises:
preparing a semiconductor layer on one of the surfaces of a substrate, the semiconductor layer including an active region and a passive region outside the active region;
a plurality of sources, a plurality of gates and a plurality of drains located within the active region, the gates being located between the sources and the drains;
a source pad connected to the source;
a drain pad connected to the drain;
a gate pad connected to the gate;
preparing a ground electrode on the other surface of the substrate;
a first via hole in the passive region, penetrating the substrate and the semiconductor layer, and electrically connecting the ground electrode and the source pad; and
a second via hole in the active region, penetrating the substrate and the semiconductor layer, and electrically connecting the ground electrode and the source electrode;
wherein, the second through hole arrangement form comprises any one of the following forms:
the setting form I is as follows: a second through hole is formed below each source electrode in each active region, the positions of the second through holes on the two adjacent source electrodes on the source electrodes where the second through holes are located relative to the source electrodes where the second through holes are located are different, wherein one of the two second through holes on any two adjacent source electrodes is arranged below one end, close to the source electrode pad, of the source electrode where the second through hole is located, and the other second through hole is arranged below one end, close to the drain electrode pad, of the source electrode where the second through hole is located;
setting a second mode: each source electrode in the active region is respectively connected with an independent source electrode bonding pad, and a second through hole is formed below one end, close to the drain electrode bonding pad, of each source electrode;
setting the form three: a second through hole is formed below each source electrode, the positions of the second through holes on any two adjacent source electrodes on the source electrode where the second through holes are located are different from each other relative to the source electrode where the second through holes are located, wherein one of the two second through holes on any two adjacent source electrodes is arranged below one end, close to the drain electrode bonding pad, of the source electrode where the second through hole is located, and the other second through hole is arranged below the center position of the source electrode where the second through hole is located; or the like, or, alternatively,
setting the form four: and second through holes with different numbers are formed in any two adjacent source electrodes, wherein one second through hole is formed below the middle position of one of the two source electrodes, and one second through hole is formed below one end, close to the source electrode bonding pad, of the other source electrode and one second through hole is formed below one end, close to the drain electrode bonding pad, of the other source electrode.
2. The semiconductor device of claim 1, wherein when the second via arrangement is the first arrangement, an etch stop layer material is disposed over the second via opening under the source to form an electrical connection with the source.
3. The semiconductor device according to claim 1, wherein when the second via arrangement form is the second arrangement form, one first via is opened below each source pad.
4. The semiconductor device of claim 2, wherein at least two of the first vias are opened under each of the source pads.
5. A method of manufacturing a semiconductor device, the method comprising:
preparing a semiconductor layer on one surface of a substrate;
forming an active region and a passive region on the semiconductor layer;
forming a source electrode, a drain electrode and a grid electrode in the active region;
preparing interconnection metal on the semiconductor layer to form a source electrode bonding pad, a drain electrode bonding pad and a grid electrode bonding pad, so that the source electrode bonding pad is electrically connected with the source electrode, the grid electrode bonding pad is electrically connected with the grid electrode, and the drain electrode bonding pad is electrically connected with the drain electrode;
forming a first through hole penetrating through the substrate and the semiconductor layer to the source bonding pad and forming a second through hole penetrating through the substrate and the semiconductor layer to the source from the other surface of the substrate; and
preparing a ground electrode from the other surface of the substrate, wherein the source pad and the source electrode are electrically connected to the ground electrode through the first via hole and the second via hole, respectively;
the step of forming a second via through the substrate and semiconductor layer to the source electrode comprises:
a second through hole is formed below each source electrode, so that the positions of the second through holes on the two adjacent source electrodes on the source electrodes where the second through holes are respectively located relative to the source electrodes where the second through holes are located are different, wherein one of the two second through holes on any two adjacent source electrodes is arranged below one end, close to the source electrode bonding pad, of the source electrode where the second through hole is located or below the center position of the source electrode where the second through hole is located, and the other second through hole is arranged below one end, close to the drain electrode bonding pad, of the source electrode where the second through hole is located; or
A second through hole is formed below one end, close to the drain electrode bonding pad, of each source electrode, wherein each source electrode in the active region is connected with an independent source electrode bonding pad; or
And forming a second through hole with different numbers on any two adjacent source electrodes, so that one second through hole is formed below the middle position of one of the two adjacent source electrodes, and one second through hole is formed below one end, close to the source electrode bonding pad, of the other source electrode and one second through hole is formed below one end, close to the drain electrode bonding pad, of the other source electrode respectively.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming a source, a drain, and a gate in the active region comprises: forming a blank area on the surface of the semiconductor layer above the second through hole in the active area through a patterning process; and
the step of forming a source pad, a gate pad and a drain pad by preparing interconnection metal on the semiconductor layer further comprises: and preparing an etching barrier layer material on the blank area to form electric connection with the source electrode, wherein the etching barrier layer material is positioned above the second through hole.
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| CN109671773B (en) * | 2017-10-16 | 2020-05-05 | 苏州能讯高能半导体有限公司 | Semiconductor device and method for manufacturing the same |
| CN109671774B (en) * | 2017-10-16 | 2020-08-21 | 苏州能讯高能半导体有限公司 | Semiconductor device and method for manufacturing the same |
| JP2020027974A (en) * | 2018-08-09 | 2020-02-20 | 株式会社村田製作所 | High frequency module and communication device |
| CN111354640B (en) * | 2018-12-21 | 2022-08-12 | 苏州能讯高能半导体有限公司 | Semiconductor device and preparation method thereof |
| CN110676317B (en) * | 2019-09-30 | 2022-10-11 | 福建省福联集成电路有限公司 | Transistor tube core structure and manufacturing method |
| CN113437040B (en) * | 2021-06-29 | 2022-05-31 | 深圳市时代速信科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN115863420A (en) * | 2021-09-24 | 2023-03-28 | 苏州能讯高能半导体有限公司 | Semiconductor device and preparation method thereof |
| CN113809174B (en) * | 2021-11-16 | 2022-03-11 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| CN114188407B (en) * | 2022-02-17 | 2022-05-06 | 深圳市时代速信科技有限公司 | Semiconductor device electrode structure, manufacturing method and semiconductor device |
| WO2023159589A1 (en) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | Chip and manufacturing method therefor, radio frequency power amplifier and terminal |
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| CN104617092A (en) * | 2014-11-06 | 2015-05-13 | 苏州捷芯威半导体有限公司 | Semiconductor device and manufacturing method thereof |
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