CN106229320B - The manufacturing method of LTPS array substrate - Google Patents
The manufacturing method of LTPS array substrate Download PDFInfo
- Publication number
- CN106229320B CN106229320B CN201610803326.7A CN201610803326A CN106229320B CN 106229320 B CN106229320 B CN 106229320B CN 201610803326 A CN201610803326 A CN 201610803326A CN 106229320 B CN106229320 B CN 106229320B
- Authority
- CN
- China
- Prior art keywords
- mask plate
- width
- manufacturing
- layer
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 title claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The present invention provides a kind of manufacturing method of LTPS array substrate, and the manufacturing method includes: that a base is formed in a lower layer；Form a upper layer in the base, the upper layer includes being superimposed portion and non-superimposed portion with the base, and the non-superimposed portion is contacted with the lower layer；A photoresist layer is formed on the upper layer；A mask plate is placed on the photoresist layer, get rid of the photoresist layer not covered by mask plate and the upper layer using photoetching process, wherein the width of the corresponding part in the mask plate and the superposition portion in a first direction greater than mask plate part corresponding with the non-superimposed portion the first direction width.
Description
Technical field
The present invention relates to field of display screen more particularly to a kind of manufacturing methods of LTPS array substrate.
Background technique
Because the production layer of LTPS (low temperature polycrystalline silicon) liquid crystal display is not more, and to the other line width uniformity requirements of layer compared with
Height, the superposition when occurring that causing due to photoresistance film thickness is different in photoetching occurs in light resistance mobility at different layers not superposition in production
Locate and had differences at non-superimposed, causes the other formation line width of layer different, to cannot achieve production and the prison of high-quality product
Control.
Summary of the invention
In order to overcome the deficiencies of the prior art, the present invention provides a kind of LTPS array base of homogeneity for promoting the other line width of layer
The manufacturing method of plate.
The present invention provides a kind of manufacturing method of LTPS array substrate, and the manufacturing method includes:
A base is formed in a lower layer；A upper layer is formed in the base, the upper layer includes and the base
Superposition portion and non-superimposed portion, the non-superimposed portion are contacted with the lower layer；A photoresist layer is formed on the upper layer；In the light
A mask plate is placed in resistance layer, gets rid of the photoresist layer not covered by mask plate and the upper layer using photoetching process, wherein institute
The width of mask plate part corresponding with the superposition portion in a first direction is stated greater than the mask plate and the non-superimposed portion
Width of the corresponding part in the first direction.
Further, the lower layer is glass plate.
Further, the base is polysilicon layer, and upper layer position gate electrode film is got rid of using photoetching process and do not covered
Diaphragm plate cover gate electrode film and form grid line.
Further, mask plate described in the width of mask plate part corresponding with the superposition portion in a first direction
Difference of the part corresponding with the non-superimposed portion between the width of the first direction is 0.2um.
Further, the width of mask plate part corresponding with the superposition portion in a second direction and the exposure mask
The difference of plate and the width of the polysilicon layer in this second direction is 1.2um, the first direction vertical described second
Direction.
Further, the polysilicon layer is in U-shape.
Further, the grid line is elongated.
In the present invention, a mask plate is placed on the photoresist layer, is got rid of using photoetching process and is not hidden by mask plate
The photoresist layer of lid and the upper layer, wherein the width of mask plate part corresponding with the superposition portion in a first direction is big
In mask plate part corresponding with the non-superimposed portion in the width of the first direction, the mask plate corresponds to superposition portion
Width be greater than the width in corresponding non-superimposed portion, can reduce in this way the upper layer in photoetching process correspond to superposition portion width and
Divide the difference between the width in superposition portion, to make the line width on upper layer more evenly.
Detailed description of the invention
Fig. 1 is the LTPS array base being related in the better embodiment for the manufacturing method of LTPS array substrate of the present invention
The schematic diagram of plate.
Fig. 2 is the LTPS array base being related in the better embodiment for the manufacturing method of LTPS array substrate of the present invention
Another schematic diagram of plate.
Fig. 3 is the flow chart of the manufacturing method better embodiment of LTPS array substrate of the present invention.
Specific embodiment
Now, it is described more fully present inventive concept hereinafter with reference to attached drawing, the invention is shown in the accompanying drawings
The exemplary embodiment of design.According to the exemplary embodiment below described in more detail with reference to the accompanying drawings, present inventive concept
The advantages of and feature and make they realize method will be apparent.It is to be noted, however, that present inventive concept is not limited to
Following illustrative embodiment, and can be implemented in a variety of manners.Therefore it provides exemplary embodiment is only for open
Present inventive concept and allow skilled in the art realises that present inventive concept scope.In the accompanying drawings, the embodiment of present inventive concept
It is not limited to specific example provided herein.
Unless otherwise defined, otherwise all terms used in the embodiment disclosed by the invention (including technical term and
Scientific term) there is meaning identical with the those of ordinary skill of technical field belonging to the present invention normally understood meaning of institute,
And it is not necessarily limited to known specific definitions when describing the present invention.Therefore, these terms may include the moment it
The equivalent terms created afterwards.It will be further understood that such as these terms defined in usually used dictionary should be explained
For with meaning identical with their meaning in this specification and under the background of the prior art, and unless here it is clear this
Otherwise sample definition will not be explained with Utopian or too formal meaning.
Fig. 1, Fig. 2 and Fig. 3 are please referred to, in the manufacturing method embodiment of the LTPS array substrate of LCD TV, the system
The method of making includes:
S301 forms a base 20 in a lower layer 10；In the present embodiment, the lower layer is glass substrate, the base
Layer is a polysilicon layer, and the polysilicon layer is in U-shape；
S303, forms a upper layer 30 in the base 20, and the upper layer includes being superimposed portion and non-folded with the base
Add portion, the non-superimposed portion is contacted with the lower layer；In the present embodiment, the upper layer is gate electrode film；
S305 forms a photoresist layer 40 on the upper layer 30；
S307 is placed a mask plate 50 on the photoresist layer 40, is got rid of using photoetching process and do not covered by mask plate
Photoresist layer 40 and the upper layer 30, wherein using photoetching process get rid of by mask plate cover gate electrode film and do not form grid
Polar curve, the grid line is elongated, and the width of mask plate part corresponding with the superposition portion in a first direction is big
In mask plate part corresponding with the non-superimposed portion the first direction width.
In the present embodiment, it is covered described in the width of mask plate part corresponding with the superposition portion in a first direction
Difference of the diaphragm plate part corresponding with the non-superimposed portion between the width of the first direction is 0.2um.The mask plate
The width of part corresponding with the superposition portion in a second direction and the mask plate and the polysilicon layer are described second
The difference of width on direction is 1.2um, the vertical second direction of the first direction.
The grid line is elongated, and the line width in the first direction of the grid line is 3.0um.
In conventional methods where, since the gate electrode film docile is on the polysilicon layer, the gate electrode film is located at described more
Superposition portion on crystal silicon layer is different from the thickness in non-superimposed portion, after photoetching process, the superposition portion of the grid line of formation
Width is less than the width in non-superimposed portion, causes line width different.
And in an embodiment of the present invention, a mask plate is placed on the photoresist layer, is got rid of not using photoetching process
The photoresist layer covered by mask plate and the upper layer, wherein mask plate part corresponding with the superposition portion is in a first direction
On width be greater than width of the mask plate part corresponding with the non-superimposed portion in the first direction, the mask plate
The width in corresponding superposition portion is greater than the width in corresponding non-superimposed portion, can reduce the upper layer in photoetching process in this way and correspond to superposition portion
Width and the difference between the width for dividing the portion of superposition, to make the line width of grid line more evenly.
Although the present invention has shown and described referring to specific embodiment, it should be appreciated by those skilled in the art that:
In the case where not departing from the spirit and scope of the present invention being defined by the claims and their equivalents, can carry out herein form and
Various change in details.
Claims (7)
1. a kind of manufacturing method of LTPS array substrate, it is characterised in that: the manufacturing method includes:
A base is formed in a lower layer；
Form a upper layer in the base, the upper layer includes being superimposed portion and non-superimposed portion with the base, described non-folded
Portion is added to contact with the lower layer；
A photoresist layer is formed on the upper layer；
A mask plate is placed on the photoresist layer, and the photoresist layer and described not covered by mask plate is got rid of using photoetching process
Upper layer, wherein the width of mask plate part corresponding with the superposition portion in a first direction is greater than the mask plate and institute
The corresponding part in non-superimposed portion is stated in the width of the first direction.
2. the manufacturing method according to claim 1, which is characterized in that the lower layer is glass plate.
3. manufacturing method according to claim 2, which is characterized in that the base is polysilicon layer, and the upper layer is grid
Pole film is got rid of using photoetching process and is not formed grid line by the gate electrode film of mask plate covering.
4. manufacturing method according to claim 3, which is characterized in that mask plate part corresponding with the superposition portion
The part corresponding with the non-superimposed portion of width and the mask plate in a first direction the first direction width it
Between difference be 0.2um.
5. manufacturing method according to claim 3, which is characterized in that mask plate part corresponding with the superposition portion
The difference of width of the width in a second direction with the mask plate with the polysilicon layer in this second direction is
1.2um, the vertical second direction of the first direction.
6. manufacturing method according to claim 3, which is characterized in that the polysilicon layer is in U-shape.
7. manufacturing method according to claim 3, which is characterized in that the grid line is elongated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610803326.7A CN106229320B (en) | 2016-09-06 | 2016-09-06 | The manufacturing method of LTPS array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610803326.7A CN106229320B (en) | 2016-09-06 | 2016-09-06 | The manufacturing method of LTPS array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106229320A CN106229320A (en) | 2016-12-14 |
| CN106229320B true CN106229320B (en) | 2019-04-05 |
Family
ID=58075421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610803326.7A Active CN106229320B (en) | 2016-09-06 | 2016-09-06 | The manufacturing method of LTPS array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106229320B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473449A (en) * | 2018-11-07 | 2019-03-15 | 惠科股份有限公司 | Overline structure, manufacturing method thereof and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622297A (en) * | 2004-12-13 | 2005-06-01 | 友达光电股份有限公司 | Method for manufacturing thin-film transistor element |
| CN101086968A (en) * | 2006-06-09 | 2007-12-12 | 三星电子株式会社 | Bottom gate thin film transistor and method of manufacturing the same |
| CN101162736A (en) * | 2006-10-11 | 2008-04-16 | 旺宏电子股份有限公司 | Vertical channel transistor structure and manufacturing method thereof |
| CN101984506A (en) * | 2010-10-12 | 2011-03-09 | 北京大学 | Method for preparing thin film transistor by two-time photo-etching |
| CN102820337A (en) * | 2011-06-07 | 2012-12-12 | 索尼公司 | Radioactive-ray imaging apparatus, radioactive-ray imaging display system and transistor |
| CN102969362A (en) * | 2011-09-01 | 2013-03-13 | 中国科学院微电子研究所 | high stability amorphous metal oxide TFT device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW456048B (en) * | 2000-06-30 | 2001-09-21 | Hannstar Display Corp | Manufacturing method for polysilicon thin film transistor liquid crystal display panel |
-
2016
- 2016-09-06 CN CN201610803326.7A patent/CN106229320B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622297A (en) * | 2004-12-13 | 2005-06-01 | 友达光电股份有限公司 | Method for manufacturing thin-film transistor element |
| CN101086968A (en) * | 2006-06-09 | 2007-12-12 | 三星电子株式会社 | Bottom gate thin film transistor and method of manufacturing the same |
| CN101162736A (en) * | 2006-10-11 | 2008-04-16 | 旺宏电子股份有限公司 | Vertical channel transistor structure and manufacturing method thereof |
| CN101984506A (en) * | 2010-10-12 | 2011-03-09 | 北京大学 | Method for preparing thin film transistor by two-time photo-etching |
| CN102820337A (en) * | 2011-06-07 | 2012-12-12 | 索尼公司 | Radioactive-ray imaging apparatus, radioactive-ray imaging display system and transistor |
| CN102969362A (en) * | 2011-09-01 | 2013-03-13 | 中国科学院微电子研究所 | high stability amorphous metal oxide TFT device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106229320A (en) | 2016-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2018184403A1 (en) | Thin-film transistor, manufacturing method thereof, array substrate and display device | |
| US20150227013A1 (en) | Display substrate and method of manufacturing the same, and display device | |
| JP6570640B2 (en) | Array substrate, display panel, and method for preparing array substrate | |
| US20160064415A1 (en) | Array substrate and fabricating method thereof, display panel and display apparatus | |
| CN103809324B (en) | A kind of display floater and display device | |
| WO2017118073A1 (en) | Array substrate and preparation method therefor, and display apparatus | |
| CN104460147A (en) | Thin film transistor array substrate, manufacturing method and display device | |
| CN104932152B (en) | The manufacturing method of liquid crystal display panel and liquid crystal display panel | |
| US9685466B2 (en) | Thin film transistor, array substrate and display device | |
| US9791755B2 (en) | Color filter-on-array substrate, display device, and method for manufacturing the color filter-on-array substrate | |
| WO2015096392A1 (en) | Array substrate, manufacturing method therefor, and display device | |
| CN105700261B (en) | Array substrate and its manufacturing method, liquid crystal display | |
| WO2016065798A1 (en) | Array substrate and manufacturing method therefor, and display device | |
| CN105957812B (en) | Field effect transistor and its manufacturing method, array substrate and its manufacturing method and display panel | |
| US10324325B2 (en) | Black matrix mask, method for manufacturing black matrix, and application thereof | |
| CN103681514B (en) | Array base palte and preparation method thereof, display unit | |
| WO2018205524A1 (en) | Array substrate and manufacturing method therefor, and display device | |
| US9490266B2 (en) | Array substrate and method for producing the same and display apparatus | |
| CN106229320B (en) | The manufacturing method of LTPS array substrate | |
| US20160363828A1 (en) | Array substrate and display device | |
| US20150280014A1 (en) | Tft and manufacturing method thereof, array substrate | |
| US20160322388A1 (en) | Array substrate, its manufacturing method and display device | |
| KR102227519B1 (en) | Display Substrate and Method for Preparing the Same | |
| CN102790056A (en) | Array substrate, manufacturing method of array substrate, manufacturing method of GOA unit and display device | |
| CN108333845A (en) | The production method of array substrate, display panel and array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |