CN106229288A - active area preparation method - Google Patents
active area preparation method Download PDFInfo
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- CN106229288A CN106229288A CN201610596085.3A CN201610596085A CN106229288A CN 106229288 A CN106229288 A CN 106229288A CN 201610596085 A CN201610596085 A CN 201610596085A CN 106229288 A CN106229288 A CN 106229288A
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- Prior art keywords
- active area
- shallow trench
- layer
- photoresist
- hard mask
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- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 132
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 85
- 230000008569 process Effects 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000004380 ashing Methods 0.000 claims abstract description 30
- 229920000642 polymer Polymers 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 45
- 239000004065 semiconductor Substances 0.000 claims description 39
- 239000007789 gas Substances 0.000 claims description 31
- 238000002161 passivation Methods 0.000 claims description 26
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 13
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 238000010790 dilution Methods 0.000 claims description 3
- 239000012895 dilution Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 239000001117 sulphuric acid Substances 0.000 claims description 3
- 235000011149 sulphuric acid Nutrition 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000012545 processing Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 115
- 239000000463 material Substances 0.000 description 15
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000011049 filling Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000006722 reduction reaction Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910001868 water Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- PRPAGESBURMWTI-UHFFFAOYSA-N [C].[F] Chemical compound [C].[F] PRPAGESBURMWTI-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
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- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
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- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 238000001548 drop coating Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000013618 particulate matter Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of active area preparation method, the technique that then wet method is removed photoresist is processed by first ashing is performed a plurality of times, described patterned photoresist layer and the polymer residue problem of shallow trench etching generation can be removed completely, thus ensure the critical size of active area, and improve fillet manufacturing process and the effect of fill process processing procedure of follow-up fleet plough groove isolation structure, finally improve the yield of device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of active area preparation method.
Background technology
In the manufacturing process of semiconductor device, the preparation technology of active device generally includes: the preparation of grid, active area
Preparation (AA loop), interlayer dielectric layer deposition, the preparation (CT loop) etc. of contact hole.Wherein, active area preparation technology is i.e.
It is the etching technics for fleet plough groove isolation structure, refer to Figure 1A, specifically include following steps: first, in Semiconductor substrate
Forming pad oxide (PadOxide) 101 and hard mask layer 102 on 100, described hard mask layer generally can use silicon nitride；Connect
, form patterned photoresist layer 103 on hard mask layer 102, this step is referred to as photoetching (AA photo, AA PH)；It
After, with this patterned photoresist layer 103 as mask, etch described hard mask layer 102, pad oxide 101 and Semiconductor substrate
100 form shallow trench (STI) 104, and define active area (AA, Active Area), and this step is referred to as shallow trench isolation junction
Structure etching (AA etch)；Afterwards, process (Ashing) and wet method by one ashing to remove photoresist the removal of (PR wet strip) technique
Described patterned photoresist layer；Then, thermal oxidation technology is used to form lining oxide layer in the bottom of shallow trench 104 and sidewall
(LinerOxide), to improve the interfacial characteristics of silicon substrate and the oxide of follow-up filling, and high annealing (High is carried out
Temperature Anneal) to discharge stress, optimize the quality of lining oxide layer；Then, in shallow trench, oxidation is then inserted
Thing material is (such as SiO2Material) etc. as isolated material, and carry out high annealing (High Temperature Anneal) to release
Put the isolated material in stress, and densification shallow trench；Then, carry out cmp (CMP) and planarize each body structure surface, with
Described hard mask layer, as grinding stop layer, leaves smooth surface, the most described hard mask layer and pad oxide is removed.
In above-mentioned active area preparation technology, the etching gas containing C, F is generally used to etch described hard mask layer 102, pad
Oxide layer 101 and Semiconductor substrate 100 are to form shallow trench 104, in this etching process, in order to solve reverse narrow raceway groove problem,
We use a kind of fillet (TOP Corner rounding) technique that can obtain fleet plough groove isolation structure, and this technique can make
Must etch and produce the most serious polymer, therefore be easy to form polymeric by-products at shallow trench 104 upper surface and sidewall
(Polymer residue), as shown in Figure 1B, this polymeric by-products by one ashing of above-mentioned technique process (Ashing) and
Wet method is removed photoresist, and (PR wet strip) step is very difficult to be removed completely, can cause the critical dimension reduction (shrink) of active area, and
Influence whether some follow-up processing procedures.Wherein, about the fillet technique of fleet plough groove isolation structure, specifically, at described hard mask
The overetch stage of layer and pad oxide etching incipient stage, general employing is passivated the strongest gas and realizes, etching reaction
The nonvolatile by-products produced etc. can produce the thickest passivation protection layer near the top of Semiconductor substrate, follow-up half
Conductor substrate etch is formed after groove, this passivation protection layer can be removed by the cleaning removing photoresist that (it is right to be similar to
Being etched back to of hard mask layer counter pushes away technique), the most in the trench can quick because of top wedge angle during thermal oxide growth lining oxide layer
Aoxidize and sphering, if the polymer residue that now shallow trench 104 top exists, on the one hand, shallow trench 104 top can be caused
Wedge angle cannot favourable conversions be fillet；On the other hand, in subsequent lining oxide layer growth course, owing to some part is gathered by these
Compound residual is sheltered from, and makes the lining oxide layer of shallow trench top relatively thin, even wholly without lining oxide layer, therefore
The isolated material easily cause shallow trench filling cavity (Void), filling peels off and fleet plough groove isolation structure isolates work accordingly
By Problem of Failure, ultimately result in corresponding chip failure.
To this end, need a kind of new active area preparation method badly, it is possible to the polymer being substantially improved shallow trench etching generation is residual
Stay problem, thus improve yield of devices.
Summary of the invention
It is an object of the invention to provide a kind of active area preparation method, it is possible to be substantially improved the poly-of shallow trench etching generation
Compound residue problem, thus improve yield of devices.
For solving the problems referred to above, the present invention proposes a kind of active area preparation method, including:
Semiconductor substrate is provided, sequentially forms pad oxide, hard mask layer and graphical on the semiconductor substrate
Photoresist layer；
With this patterned photoresist layer described as mask, etch described hard mask layer, pad oxide and Semiconductor substrate,
To form shallow trench in described Semiconductor substrate, and define active area；
First ashing is performed a plurality of times and processes the technique that then wet method is removed photoresist, to remove described patterned photoresist layer and institute
State the polymer residue on shallow trench surface.
Further, first ashing processes the execution number of times of the technique that then wet method is removed photoresist is 2 times.
Further, the formula that the first ashing every time performed processes the technique that then wet method is removed photoresist is identical.
Further, the photoresist after the wet method once performed before monitoring is removed photoresist and polymer residue situation data, and root
Technical recipe that the ashing currently performed according to described data point reuse processes and the technical recipe that wet method is removed photoresist.
Further, the technological temperature that described ashing processes is 80 DEG C～300 DEG C, and the process gas used includes oxygen
With auxiliary gas, described auxiliary gas includes at least one in hydrogen, nitrogen and fluoro-gas,.
Further, the process that described wet method is removed photoresist includes: the Fluohydric acid. initially with dilution is carried out, and then uses
Sulphuric acid and hydrogen peroxide mixed liquor clean, and finally use ammonia and hydrogen peroxide mixed liquor to clean.
Further, after removing described patterned photoresist layer, also the top of described shallow trench is carried out fillet
Change processes.
Further, with this patterned photoresist layer described as mask, first etch described hard mask layer and pad oxide,
To form opening, wherein begin with at the over etching of hard mask layer and pad oxide etching the passivation of etching gas than
Remaining etch stages of described hard mask layer and pad oxide is all strong, to form passivation guarantor at hard mask layer and pad oxide sidewall
Retaining wall；Then, with described hard mask layer and pad oxide and passivation protection wall as mask, the quasiconductor of described open bottom is etched
Substrate, to form shallow trench in described Semiconductor substrate, and defines active area.
Further, after forming shallow trench, remove described passivation protection wall, and described Semiconductor substrate is carried out fillet
Etching or etching of pulling back the pad oxide at described shallow trench top, carried out at corners the top of described shallow trench
Reason.
Further, after forming shallow trench, first ashing is first performed a plurality of times and processes the technique that then wet method is removed photoresist, to remove
Described patterned photoresist layer and described passivation protection wall；Fillet is formed with to described shallow ridges afterwards by thermal oxidation technology
The top of groove carries out corners process.
Compared with prior art, the active area preparation method of the present invention, process then wet method by first ashing is performed a plurality of times
The technique removed photoresist, can remove described patterned photoresist layer completely, and be substantially improved the polymer that shallow trench etching produces
Residue problem, thus ensure the critical size of active area, and improve the fillet manufacturing process of follow-up fleet plough groove isolation structure
And the effect of fill process processing procedure, finally improve the yield of device.
Accompanying drawing explanation
Figure 1A is the device architecture generalized section in existing a kind of active area preparation technology；
Figure 1B is the SEM figure of the active area of preparation in prior art；
Fig. 2 is the active area preparation method flow chart of the specific embodiment of the invention；
Fig. 3 A to 3C is the device architecture generalized section in this active area preparation method sending out bright embodiment concrete.
Detailed description of the invention
For making the purpose of the present invention, feature become apparent, below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is made
Further instruction, but, the present invention can realize by different forms, should simply not be confined to described embodiment.
Refer to Fig. 2, the present embodiment proposes a kind of active area preparation method, including:
S21, it is provided that Semiconductor substrate, sequentially forms pad oxide, hard mask layer and figure on the semiconductor substrate
The photoresist layer of shape；
S22, with this patterned photoresist layer described as mask, etches described hard mask layer, pad oxide and quasiconductor
Substrate, to form shallow trench in described Semiconductor substrate, and defines active area；
S23, is performed a plurality of times first ashing and processes the technique that then wet method is removed photoresist, with remove described patterned photoresist layer with
And the polymer residue on described shallow trench surface；
S24, uses thermal oxidation technology to form lining oxide layer in the bottom of described shallow trench and sidewall；
S25, inserts isolated material in described shallow trench, and using described hard mask layer as grinding stop layer, to described
The surface of isolated material carries out chemical-mechanical planarization.
Refer to Fig. 3 A, the Semiconductor substrate 300 provided in the step s 21 can be monocrystalline, polycrystalline or non crystalline structure
Silicon, germanium, GaAs or SiGe (SiGe) compound, it is also possible to be the Semiconductor substrate made of silicon-on-insulator (SOI), this area
Technical staff can according in Semiconductor substrate 300 formed transistor types select Semiconductor substrate type, the most partly lead
The type of body substrate 30 should not limit the scope of the invention.In described Semiconductor substrate 300, sequentially form from the bottom to top
Pad oxide 301, hard mask layer 302.Wherein, described pad oxide 301 may utilize the mode of thermal oxidation technology growth and formed, its
Compact structure, provides cushion for follow-up hard mask layer 302, it is to avoid directly in Semiconductor substrate 300, grown silicon nitride etc. is hard
The shortcoming that can produce dislocation during mask layer 302, with protection Semiconductor substrate 300 below.In the present embodiment, described hard mask
Layer 302 is preferably silicon nitride layer, and it can use chemical vapour deposition technique (CVD) to be formed, in other embodiments of the invention, firmly
Mask layer 302 can be single layer structure, it is also possible to be multilayer lamination structure, and its material can be silicon nitride, silicon oxynitride, amorphous
One or more in carbon, boron nitride, titanium nitride etc.；Also pad oxidation is can be without between Semiconductor substrate 300 and hard mask layer 302
Layer 301.On described hard mask layer 302, coat photoresist, and the series of steps such as through exposure and development afterwards, formed graphical
Photoresist layer 303, patterned photoresist layer 303 defines the position of shallow trench.In other embodiments of the invention, in institute
Before stating coating photoresist, first can form amorphous carbon layer (Amorphous selectively on described hard mask layer 3022
Carbon, AC, not shown), darc layer (Dielectric Anti-Reflect Coating, dielectric anti reflective layer, not shown)
With one or more layers in BARC layer (Bottom Anti-reflective coating, bottom antireflective coating, not shown),
Then re-use spin coating (spin-on coating), spraying (spray coating), drop coating (dip coating), brush
The method such as (brush coating) or evaporation forms a layer photoetching glue-line, and aligned, expose, the series of process such as development
After obtain patterned photoresist layer 303；Described amorphous carbon layer can provide high-resolution and fine patterning, it is ensured that after
The stability of continuous shallow trench width consistency；Darc layer is used as to be subsequently formed light-absorption layer during patterned photoresist layer, permissible
Reduce the reflection to exposure light that amorphous carbon layer causes, reduce the shadow that photoresist is exposed by the reflection light of exposure light
Ring, improve photoresist layer exposure accuracy.BARC layer, in described photoresist layer exposure process, can effectively reduce standing wave effect and carry
The contrast of the high figure formed on described photoresist layer.
Refer to Fig. 3 A and 3B, in step S22, the photoresist layer 305 graphically changed is mask, successively etches hard mask
Layer 302, pad oxide 301 and Semiconductor substrate 300, to form shallow trench 304, shallow ridges in described Semiconductor substrate 300
The Semiconductor substrate 300 of groove 304 both sides is active area.Specifically, the photoresist layer 305 first graphically changed is mask, uses blunt
More weak but the etch rate etching gas faster of the property changed, generally rich in the gas (fluorine carbon ratio is more than 2) of fluorine, such as SF6、CHF3、
CF4、C2F6And C3F8In at least one, etching gas also can mix a certain amount of O2Or N2, hard mask layer 302 is led
Etching, the technique of this main etching can be with reactive ion etching process (reactiveionetching, RIE) or high-density plasma
The dry etching methods such as body (highdensityplasma, HDP) etching technics, etch period is relatively long, and etching stopping is firmly
The certain depth of mask layer 302, the pattern formed on opening 304a, and patterned photoresist layer 305 is transferred to firmly simultaneously
On mask layer 302；Then, the etching gas that passivation property is the strongest, typically rich in the gas (fluorine carbon ratio is not more than 2) of carbon, example are used instead
Such as C4F6、CH2F2、C4F8、C5F8、C2F4, and CH3At least one in F, carries out over etching to fully open to hard mask layer 302
Hard mask layer 302, and pad oxide 301 is carried out less amount of etching (i.e. the etching incipient stage of pad oxide 301), at this
In etching process, etching gas can react with photoresist etc., produces substantial amounts of nonvolatile, highly cross-linked and insulation
By-product polymer, these polymer can be quickly bottom hard mask layer 302 and pad oxide sidewall and etching opening 304a
Deposition, thus form passivation protection wall 305 (i.e. it is mainly composed of polymer), such that it is able to suppress follow-up to Semiconductor substrate
Isotropic etching impact；Then with hard mask layer 302 and passivation protection wall 305 as mask, passivation is again used instead
Remaining pad oxide 301 and Semiconductor substrate 300 are performed etching by more weak etching gas, to fully open pad oxide
301, and in Semiconductor substrate 300, form shallow trench 304, the degree of depth of the shallow trench 304 in Semiconductor substrate 300 can be by carving
The erosion time controls.
Refer to Fig. 3 B and 3C, in step S23, degumming process is performed a plurality of times, to remove patterned photoresist layer 303
And the passivation protection wall 305 of polymer property.Degumming process is the process that after first ashing processes, wet method is removed photoresist every time, every time
The formula of degumming process can be identical, can be different, it is preferred that is gone by the wet method in the degumming process that once performs before monitoring
Photoresist after glue and polymer residue situation data, and currently perform according to described data point reuse at the ashing in degumming process
The technical recipe that the technical recipe of reason and wet method are removed photoresist.First the process that ashing processes every time can be such that, to patterned
Photoresist layer 303 and passivation protection wall 305 surface carry out preheating process, concrete, and the reacting gas used can be O2、
H2And N2Mixed gas, wherein O2For main reacting gas, proportioning can be 60%～80%, and reaction power can be
500W～800W, for example, 650W, technological temperature can be 80 DEG C～150 DEG C, for example, 150 DEG C, and ashing time can be 5s
～10s, for example, 8s；Then, the duricrust of patterned photoresist layer 303 and passivation protection wall 305 surface is softened, tool
Body, the reacting gas used can be O2、H2And N2Mixed gas；Wherein, N2And H2For main reacting gas, N2With
H2Shared ratio can be 60%～80%, utilizes N2And H2Carry out reduction reaction, by patterned photoresist layer 303 and blunt
The crosslinking duricrust changing the formation of protective bulkhead 305 surface reacts into the little molecule of short chain, it is easy to follow-up removal, reaction power can be 800W
～1500W, technological temperature can be 200 DEG C～300 DEG C, and the response time can be 10s～50s；Then, patterned light is removed
Photoresist layer 303 and the duricrust on passivation protection wall 305 surface, have residual photoresist, at hard mask layer on hard mask layer 302 surface
302 sidewalls still remain passivation protection wall 305, concrete, and the reacting gas used can be O2、H2And N2Mixed gas,
O2And H2For main reacting gas；O2And H2Shared ratio can be 50%～90%, reaction power be 1500W～
2000W, technological temperature can be 250 DEG C～300 DEG C, and the response time is 10s～50s, in the present embodiment, in each degumming process
The total time that ashing processes is less than 60s, for example, 40s.After performing the ashing process of degumming process for the first time, patterned photoetching
The duricrust on glue-line 303 and passivation protection wall 305 surface is entirely removed, but, patterned photoresist layer 303 and passivation
Protective bulkhead 305 is not removed completely, i.e. there is residual photoresist and etch polymers, it is therefore desirable to removed photoresist into one by wet method
Step removes residual photoresist and passivation protection wall 305 polymer.First the process that wet method is removed photoresist every time can be such that, first adopts
It is carried out with the Fluohydric acid. of dilution, to remove the Organic substance such as residual photoresist and polymer；Then, use sulphuric acid with double
Oxygen water mixed liquid cleans, to remove natural oxidizing layer and the metal ion of shallow trench 304 sidewall surfaces；Then, use ammonia,
The mixed solution of hydrogen peroxide and deionized water is carried out, to remove particulate matter etc..After when first time, wet method degumming process terminates,
The photoresist after wet method is removed photoresist and passivation protection wall polymer residue situation data can be monitored, and connect according to described data point reuse
The technical recipe that the technical recipe of the ashing process in the degumming process got off and wet method are removed photoresist, wet method is removed photoresist such as the first time
After the photoresist that monitors and polymer residue less, therefore shorten the total time that second time ashing processes, and reduce second
Wet method is removed photoresist the solubility of used cleanout fluid, thus enough avoids shallow trench is caused defective workmanship, it can also be ensured that effectively
Polymer residue on the photoresist on removal hard mask layer 302 surface and shallow trench 304 surface, further increases product good
Rate.Therefore, it can the photoresist after being removed photoresist and polymer residue situation data by the wet method of a front degumming process of monitoring,
Deciding whether to perform degumming process next time, in the present embodiment, perform that twice first ashing process that then wet method removes photoresist goes
Adhesive process so that the polymer residue of shallow trench sidewall is reduced to device manufacture requirements.
Refer to continued reference to Fig. 3 C, the top side wall of the shallow trench 304 owing to being formed is generally sharp-pointed chamfering, and passes through
After step S23, shallow trench sidewall no longer has polymer residue, the most in step s 24, forms low defect on the surface of shallow trench
During with the lining oxide layer 306 of high-compactness, oxygen therein occurs with the silicon in the Semiconductor substrate 300 of STI shallow trench corner
Reaction, makes shallow trench 304 sidewall oxidation, makes the oxide layer of STI top corner to thicken, thus the top of round and smooth shallow trench is turned
Angle, and remove the damage introduced on shallow trench 304 surface in Semiconductor substrate 300 etching process, and can improve because STI turns oxygen
It is the highest that change layer crosses the raw yield rate of small property, the problem of reliability reduction.Wherein, lining oxide layer 306 can be silicon oxide (SiO2), its
Formation process is atom layer deposition process, boiler tube thermal oxidation technology (Furnace Oxide) or original position steam oxidation technique
(ISSG Oxide, in-situ steam generation Oxide), it is also preferred that the left after forming lining oxide layer 306, carry out height
Temperature annealing (High Temperature Anneal), to discharge the stress in lining oxide layer 306, optimizes the matter of lining oxide layer 306
Amount, and make the oxygen in lining oxide layer 306 forming process fully occur with the silicon in the Semiconductor substrate 300 of STI shallow trench corner
Reaction, the top corner of round and smooth shallow trench.Lining oxide layer 306 can not only improve the boundary of silicon substrate and the oxide of follow-up filling
Face characteristic, and can in the annealing process of the isolated material of follow-up filling, stop the oxy radical in isolated material and
H2O is to the diffusion of active area, it is to avoid oxidation and the damage to active area border, thus greatly reduces active area critical dimension (AA
CD) reduce.In other embodiments of the invention, lining oxide layer 306 can also be silicon oxynitride (SiOxNy), its formation process
For ald and the combination of oxidation technology, specifically, first, use SiH2Cl2And NH3Reacting gas is in shallow trench
Surface repeatedly cycle atomic layer deposition nitration case；Then, in situ steam oxidation technique (ISSG) oxidation nitridation layer and shallow is used
Flute surfaces, thus the nitrogen oxide layer of the inner surface formation line style at shallow trench, (used is anti-for steam oxidation technique in situ
Answering gas can be H2And O2Mixed gas, the material of nitrogen oxide layer can be silicon oxynitride, wherein in the mistake of oxidation nitridation layer
Cheng Zhong, the most unavoidably oxidizes away the surface of trenched side-wall, and the nitrogen oxide layer ultimately formed is possible not only to improve simple groove
Round and smooth degree and the ambient stress improved in shallow trench, and active area critical dimension can be efficiently reduced and reduce.
Please continue to refer to Fig. 3 C, in step s 25, high-aspect-ratio technique (HARP) inner surface can be used to be coated with lining
The shallow trench of oxide layer 306 carries out the filling (filling) of isolated material 307, and with hard mask layer 302 as stop-layer, carries out
Cmp, so that the planarization of isolated material 307 top surface.It is also preferred that the left before cmp, to fill
Isolated material 307 carries out water vapour annealing, to discharge stress, and makes isolated material fine and close (densify) change, repairs in HARP
Space, finally forms void-free shallow trench isolation (shallow trench isolation is called for short STI) knot in shallow trench
Structure.
From the above mentioned, the active area preparation method of the present embodiment, process then wet method remove photoresist by first ashing is performed a plurality of times
Technique, can remove described patterned photoresist layer completely, and be substantially improved the polymer residue that shallow trench etching produces
Problem, thus ensure the critical size of active area, and improve follow-up fleet plough groove isolation structure fillet manufacturing process and
The effect of fill process processing procedure, finally improves the yield of device.
From the above mentioned, the active area preparation method of the present embodiment, on the one hand, process the wettest by first ashing is performed a plurality of times
The technique that method is removed photoresist, can remove described patterned photoresist layer completely, and be substantially improved the polymerization that shallow trench etching produces
Thing residue problem, thus ensure the critical size of active area, and improve the fillet technique system of follow-up fleet plough groove isolation structure
Journey and the effect of fill process processing procedure, finally improve the yield of device；On the other hand, by passivation protection wall at quasiconductor
The part extended on substrate surface, further ensures the critical size of follow-up shallow trench revised to quasiconductor substrate etching
And follow-up shallow trench fillet processes the effect of technique.
Obviously, those skilled in the art can carry out various change and the modification spirit without deviating from the present invention to invention
And scope.So, if the present invention these amendment and modification belong to the claims in the present invention and equivalent technologies thereof scope it
In, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. an active area preparation method, it is characterised in that including:
Semiconductor substrate is provided, sequentially forms pad oxide, hard mask layer and patterned light on the semiconductor substrate
Photoresist layer；
With this patterned photoresist layer described as mask, etch described hard mask layer, pad oxide and Semiconductor substrate, with
Described Semiconductor substrate is formed shallow trench, and defines active area；
First ashing is performed a plurality of times and processes the technique that then wet method is removed photoresist, to remove described patterned photoresist layer and described shallow
The polymer residue of flute surfaces.
2. active area preparation method as claimed in claim 1, it is characterised in that first ashing processes the technique that then wet method is removed photoresist
Execution number of times be 2 times.
3. active area preparation method as claimed in claim 1, it is characterised in that the first ashing every time performed processes then wet method
The formula of the technique removed photoresist is identical.
4. active area preparation method as claimed in claim 1, it is characterised in that after the wet method once performed before monitoring is removed photoresist
Photoresist and polymer residue situation data, and the technical recipe that processes of the ashing currently performed according to described data point reuse and
The technical recipe that wet method is removed photoresist.
5. active area preparation method as claimed in claim 1, it is characterised in that the technological temperature that described ashing processes is 80 DEG C
～300 DEG C, the process gas used includes oxygen and auxiliary gas, and described auxiliary gas includes hydrogen, nitrogen and contains fluorine gas
At least one in body.
6. active area preparation method as claimed in claim 1, it is characterised in that the process that described wet method is removed photoresist includes: first
The Fluohydric acid. using dilution is carried out, and then uses sulphuric acid and hydrogen peroxide mixed liquor to clean, finally uses ammonia and hydrogen peroxide
Mixed liquor cleans.
7. active area preparation method as claimed in claim 1, it is characterised in that remove described patterned photoresist layer it
After, also the top of described shallow trench is carried out corners process.
8. active area preparation method as claimed in claim 1, it is characterised in that with this patterned photoresist layer described for covering
Film, first etches described hard mask layer and pad oxide, and to form opening, wherein over etching and pad oxide at hard mask layer are carved
Erosion begins with the passivation of etching gas than remaining etch stages at described hard mask layer and pad oxide all by force, with
Hard mask layer and pad oxide sidewall form passivation protection wall；Then, with described hard mask layer and pad oxide and passivation protection
Wall is mask, etches the Semiconductor substrate of described open bottom, to form shallow trench in described Semiconductor substrate, and defines
Active area.
9. active area preparation method as claimed in claim 8, it is characterised in that after forming shallow trench, remove described passivation
Protective bulkhead, carries out corners process to the top of described shallow trench.
10. active area preparation method as claimed in claim 9, it is characterised in that after forming shallow trench, elder generation is first performed a plurality of times
Ashing processes the technique that then wet method is removed photoresist, to remove described patterned photoresist layer and described passivation protection wall；Rear logical
Cross thermal oxidation technology and carry out corners process to form fillet with the top to described shallow trench.
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| CN109755171A (en) * | 2017-11-06 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of groove and the forming method of fleet plough groove isolation structure |
| CN110211919A (en) * | 2019-07-15 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of fleet plough groove isolation structure and the forming method of semiconductor devices |
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| CN110854068A (en) * | 2019-10-28 | 2020-02-28 | 深圳市华星光电技术有限公司 | Preparation method of TFT array substrate and TFT array substrate |
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