CN106227603A - The power calculation algorithms of multiple core chip and system - Google Patents
The power calculation algorithms of multiple core chip and system Download PDFInfo
- Publication number
- CN106227603A CN106227603A CN201610596010.5A CN201610596010A CN106227603A CN 106227603 A CN106227603 A CN 106227603A CN 201610596010 A CN201610596010 A CN 201610596010A CN 106227603 A CN106227603 A CN 106227603A
- Authority
- CN
- China
- Prior art keywords
- threads
- core
- allocation strategy
- core chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5018—Thread allocation
Abstract
The invention provides power calculation algorithms and the system of a kind of multiple core chip, described method comprises the steps: to obtain total thread of multi core chip；The number of threads of each kernel is known according to allocation strategy；The power of each core is calculated according to this number of threads.The advantage that the technical scheme that the present invention provides has power calculation and management.
Description
Technical field
The present invention relates to electronic chip field, particularly relate to power calculation algorithms and the system of a kind of multiple core chip.
Background technology
Chip also has the place of its uniqueness, broadly, as long as use the semiconductor chip that microfabrication means manufacture
Son, can be called chip, and might not there be circuit the inside.Such as semiconductor light source chips；Such as machinery chip, such as MEMS top
Spiral shell instrument；Or biochip such as DNA chip.In communication with information technology, when scope is confined to silicon integrated circuit, chip
It is exactly on " circuit on silicon wafer " with the common factor of integrated circuit.Chipset, then be a series of chip portfolios that are mutually related,
They interdepend, and combine and can play the processor inside bigger effect, such as computer and south north bridge chipset,
Radio frequency, base band and power management chip group inside mobile phone.
Existing chip cannot realize calculating and the management of power.
Summary of the invention
The power calculation algorithms of a kind of multiple core chip is provided, which solves prior art and cannot realize the calculating of power
And logistical drawbacks.
On the one hand, it is provided that the power calculation algorithms of a kind of multiple core chip, described method comprises the steps:
Obtain total thread of multi core chip；
The number of threads of each kernel is known according to allocation strategy；
The power of each core is calculated according to this number of threads.
Optionally, described foundation allocation strategy knows that the number of threads of each kernel is concrete, including:
Allocation strategy according to load balancing distributes the number of threads of each core.
Optionally, described foundation allocation strategy knows that the number of threads of each kernel is concrete, including:
The allocation strategy divided equally according to quantity distributes the number of threads of each core.
Second aspect, it is provided that the power calculation system of a kind of multiple core chip, described system includes:
Acquiring unit, for obtaining total thread of multi core chip；
Allocation unit, for knowing the number of threads of each kernel according to allocation strategy；
Computing unit, for calculating the power of each core according to this number of threads.
Optionally, described allocation unit, specifically for distributing the Thread Count of each core according to the allocation strategy of load balancing
Amount.
Optionally, described allocation unit, the allocation strategy specifically for dividing equally according to quantity distributes the Thread Count of each core
Amount.
The technical scheme that the specific embodiment of the invention provides obtains total thread of multi core chip, knows according to allocation strategy
The number of threads of each kernel, calculates the power of each core, so it has realizes multiple core chip according to this number of threads
Power calculation and the advantage of management.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
The flow chart of the power calculation algorithms of a kind of multiple core chip that Fig. 1 provides for the present invention；
The structure chart of the power calculation system of a kind of multiple core chip that Fig. 2 provides for the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
Power calculation side refering to a kind of multiple core chip that Fig. 1, Fig. 1 provide for the present invention the first better embodiment
The flow chart of method, the method is completed by electronic chip, and the method is as it is shown in figure 1, comprise the steps:
Step S101, total thread of acquisition multi core chip；
Step S102, foundation allocation strategy know the number of threads of each kernel；
Step S103, according to this number of threads calculate each core power.
The technical scheme that the specific embodiment of the invention provides obtains total thread of multi core chip, knows according to allocation strategy
The number of threads of each kernel, calculates the power of each core, so it has realizes multiple core chip according to this number of threads
Power calculation and the advantage of management.
Optionally, the implementation method of above-mentioned steps S102 is specifically as follows:
Allocation strategy according to load balancing distributes the number of threads of each core.
Optionally, the implementation method of above-mentioned steps S103 is specifically as follows:
The allocation strategy divided equally according to quantity distributes the number of threads of each core.
Power calculation system refering to a kind of multiple core chip that Fig. 2, Fig. 2 provide for the present invention the second better embodiment
System, this system includes:
Acquiring unit 201, for obtaining total thread of multi core chip；
Allocation unit 202, for knowing the number of threads of each kernel according to allocation strategy；
Computing unit 203, for calculating the power of each core according to this number of threads.
The technical scheme that the specific embodiment of the invention provides obtains total thread of multi core chip, knows according to allocation strategy
The number of threads of each kernel, calculates the power of each core, so it has realizes multiple core chip according to this number of threads
Power calculation and the advantage of management.
Optionally, above-mentioned allocation unit 202, specifically for distributing the thread of each core according to the allocation strategy of load balancing
Quantity.
Optionally, above-mentioned allocation unit 202, the allocation strategy specifically for dividing equally according to quantity distributes the thread of each core
Quantity.
It should be noted that for aforesaid each method embodiment or embodiment, in order to be briefly described, therefore by its all table
Stating as a series of combination of actions, but those skilled in the art should know, the present invention is not by described sequence of movement
Restriction, because of according to the present invention, some step can use other orders or carry out simultaneously.Secondly, people in the art
Member also should know, embodiment described in the specification or embodiment belong to preferred embodiment, involved action and list
Necessary to the unit not necessarily present invention.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and does not has the portion described in detail in certain embodiment
Point, may refer to the associated description of other embodiments.
Step in embodiment of the present invention method can carry out order according to actual needs and adjust, merges and delete.
Unit in embodiment of the present invention device can merge according to actual needs, divides and delete.This area
The feature of the different embodiments described in this specification and different embodiment can be combined or combine by technical staff.
Through the above description of the embodiments, those skilled in the art it can be understood that to the present invention permissible
Realize with hardware, or firmware realizes, or combinations thereof mode realizes.When implemented in software, can be by above-mentioned functions
It is stored in computer-readable medium or is transmitted as the one or more instructions on computer-readable medium or code.Meter
Calculation machine computer-readable recording medium includes computer-readable storage medium and communication media, and wherein communication media includes being easy to from a place to another
The individual local any medium transmitting computer program.Storage medium can be any usable medium that computer can access.With
As a example by this but be not limited to: computer-readable medium can include random access memory (Random Access Memory,
RAM), read only memory (Read-Only Memory, ROM), EEPROM (Electrically
Erasable Programmable Read-Only Memory, EEPROM), read-only optical disc (Compact Disc Read-
Only Memory, CD-ROM) or other optical disc storage, magnetic disk storage medium or other magnetic storage apparatus or can be used in
Carry or store and there is instruction or the desired program code of data structure form can be by any other of computer access
Medium.In addition.Any connection can be suitable become computer-readable medium.Such as, if software is to use coaxial cable, light
Fine optical cable, twisted-pair feeder, Digital Subscriber Line (Digital Subscriber Line, DSL) or such as infrared ray, radio and
The wireless technology of microwave etc from website, server or other remote source, then coaxial cable, optical fiber cable, double
The wireless technology of twisted wire, DSL or such as infrared ray, wireless and microwave etc be included in affiliated medium fixing in.Such as this
Bright used, dish (Disk) and dish (disc) include compress laser disc (CD), laser dish, laser disc, Digital Versatile Disc (DVD),
Floppy disk and Blu-ray Disc, the duplication data of the usual magnetic of its mid-game, dish then carrys out the duplication data of optics with laser.Group above
Close within should also be as being included in the protection domain of computer-readable medium.
In a word, the foregoing is only the preferred embodiment of technical solution of the present invention, be not intended to limit the present invention's
Protection domain.All within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. made, should be included in
Within protection scope of the present invention.
Claims (6)
1. the power calculation algorithms of multiple core chip, it is characterised in that described method comprises the steps:
Obtain total thread of multi core chip；
The number of threads of each kernel is known according to allocation strategy；
The power of each core is calculated according to this number of threads.
Method the most according to claim 1, it is characterised in that the described Thread Count knowing each kernel according to allocation strategy
Measurer body, including:
Allocation strategy according to load balancing distributes the number of threads of each core.
Method the most according to claim 1, it is characterised in that the described Thread Count knowing each kernel according to allocation strategy
Measurer body, including:
The allocation strategy divided equally according to quantity distributes the number of threads of each core.
4. the power calculation system of multiple core chip, it is characterised in that described system includes:
Acquiring unit, for obtaining total thread of multi core chip；
Allocation unit, for knowing the number of threads of each kernel according to allocation strategy；
Computing unit, for calculating the power of each core according to this number of threads.
System the most according to claim 4, it is characterised in that described allocation unit, specifically for according to load balancing
Allocation strategy distributes the number of threads of each core.
System the most according to claim 4, it is characterised in that described allocation unit, specifically for divide equally according to quantity
Allocation strategy distributes the number of threads of each core.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596010.5A CN106227603A (en) | 2016-07-25 | 2016-07-25 | The power calculation algorithms of multiple core chip and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596010.5A CN106227603A (en) | 2016-07-25 | 2016-07-25 | The power calculation algorithms of multiple core chip and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106227603A true CN106227603A (en) | 2016-12-14 |
Family
ID=57533060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610596010.5A Withdrawn CN106227603A (en) | 2016-07-25 | 2016-07-25 | The power calculation algorithms of multiple core chip and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106227603A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018018373A1 (en) * | 2016-07-25 | 2018-02-01 | 张升泽 | Power calculation method and system for multiple core chips |
| WO2018018451A1 (en) * | 2016-07-27 | 2018-02-01 | 李媛媛 | Power distribution method and system in electronic chip |
-
2016
- 2016-07-25 CN CN201610596010.5A patent/CN106227603A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018018373A1 (en) * | 2016-07-25 | 2018-02-01 | 张升泽 | Power calculation method and system for multiple core chips |
| WO2018018451A1 (en) * | 2016-07-27 | 2018-02-01 | 李媛媛 | Power distribution method and system in electronic chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106227603A (en) | The power calculation algorithms of multiple core chip and system | |
| CN106294063A (en) | Temperature-controlled process based on chip and system | |
| CN106201726A (en) | Many core chip thread distribution method and system | |
| CN106250235A (en) | Multi-task scheduling methods based on many core chip and system | |
| CN106227606A (en) | The method and system of many interval distribution electronic chip voltages | |
| CN106056837A (en) | Noise alarm method and system of electronic chip | |
| CN106155862A (en) | Current calculation method in electronic chip and system | |
| CN106227639A (en) | Multi core chip voltage calculates method and system | |
| CN106250238A (en) | Load balancing application process in multi core chip and system | |
| CN106201725A (en) | The power realization method and system of multi core chip | |
| CN106250538A (en) | Wechat is shared the method and system of big data | |
| CN106202773A (en) | The noise modulated method and system of electronic chip | |
| CN106292976A (en) | Electronic chip builtin voltage distribution method and system | |
| CN106200740A (en) | The voltage modulated method and system of electronic chip | |
| CN106227602A (en) | The distribution method being supported between multi core chip and system | |
| CN106199149A (en) | The electric current alarm method of electronic chip and system | |
| CN106093522A (en) | The electric current method for drafting of electronic chip and system | |
| CN106130420A (en) | Vertical coil winding machine method for controlling number of revolution based on motor and system | |
| CN106095343A (en) | The power storage method and system of electronic chip | |
| CN105955383A (en) | Current modulation method and system of electronic chip | |
| CN106018933A (en) | Electronic chip voltage alarming method and system | |
| CN106126119A (en) | The signal storage method and system of electronic chip | |
| CN106126120A (en) | The noise storage method and system of electronic chip | |
| CN106155169A (en) | The power modulation method of electronic chip and system | |
| CN106295818A (en) | Customization method and system when of English course |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20161214 |