CN106210591A

CN106210591A - A kind of desktop Video based on FPGA transmission system

Info

Publication number: CN106210591A
Application number: CN201610578215.0A
Authority: CN
Inventors: 李敏
Original assignee: Shenzhen Huawei Intelligent Technology Co Ltd
Current assignee: Shenzhen Huawei Intelligent Technology Co Ltd
Priority date: 2016-07-20
Filing date: 2016-07-20
Publication date: 2016-12-07

Abstract

The invention discloses a kind of desktop Video based on FPGA transmission system, by power pack, user interface subcard, master control processes subcard and base plate subcard four part forms, power pack connects user interface subcard respectively, master control processes subcard and base plate subcard, and user interface subcard, master control process subcard and base plate subcard is interconnected by FPC winding displacement；Using FPGA to carry out conversion of resolution and the clock jitter removing of video, the logical system of the conversion of resolution that employing FPGA carries out video is mainly made up of audio/video matrix module, DDR2 Read-write Catrol module, IIC receiver module, PLL reconfigurable ACS module, output display module, video scaling module.Present system uses FPGA to carry out conversion of resolution and the clock jitter removing design of video, reduces time delay and ensures that audio stream stably transmits, and simple and convenient, transmission delay is low, and lossless compress image transmitting quality is high.

Description

A kind of desktop Video based on FPGA transmission system

Technical field

The present invention relates to video data transmission technical field, a kind of desktop Video based on FPGA transmission system.

Background technology

Along with the development of video conferencing system, the electronic equipment above current conference table increasingly modernizes and intelligent. Desktop voice-transmission system, speech system, translation system, video frequency following system, tone tracking system, No paper office system etc. Deng.

For desktop video transmission system, major part product is star schema based on video matrix the most on the market Or wireless throwing screen technology.There is natural defect in video matrix star schema, if all video source to go up projection or TV must Matrix must be first passed through.So layout and video cabling of video matrix is very limited, and its transmission range is the most comparatively short.Wireless throwing is shielded The transmission of video time delay of technology, image Lossy Compression Algorithm, transmission range and the requirement etc. to conferencing environment interference, it should The client the highest to video quality demands with a part can only be met, but it is difficult to meet user and wants in formal large-scale meeting-place Ask.

Summary of the invention

It is an object of the invention to provide that a kind of wiring is simple and convenient, transmission delay is low, lossless compress image transmitting quality High desktop Video based on FPGA transmission system, with the problem solving to propose in above-mentioned background technology.

For achieving the above object, the present invention provides following technical scheme:

A kind of desktop Video based on FPGA transmission system, by power pack, user interface subcard, master control process subcard and Base plate subcard four part forms, and power pack connects user interface subcard respectively, master control processes subcard and base plate subcard, Yong Hujie Openning card, master control process subcard and base plate subcard is interconnected by FPC winding displacement；The resolution using FPGA to carry out video turns Change and clock jitter removing, use FPGA carry out video conversion of resolution logical system mainly by audio/video matrix module, DDR2 Read-write Catrol module, IIC receiver module, PLL reconfigurable ACS module, output display module, video scaling module form.

As the further scheme of the present invention: power pack provides 5V unidirectional current for system, and power pack includes AC220V Turn DC 5V module and interface circuit thereof.

As the further scheme of the present invention: user interface subcard includes that analogue audio frequency input interface, VGA video input connect Mouthful, local HDMI input interface, from end DVI input interface, audio frequency and video processing unit FPGA circuitry and network input/output and Corresponding interface circuit.

As the further scheme of the present invention: master control processes subcard and includes master control processing unit MCU circuit.

As the further scheme of the present invention: base plate subcard includes HDMI change-over circuit and HDBT input/output circuitry.

As the further scheme of the present invention: IIC receiver module completes the CPU configuration work to FPGA；Output display mould Block completes display function；Audio/video matrix module completes the selection output of audio frequency and video.

As the further scheme of the present invention: DDR2 Read-write Catrol module completes the arbitration of the read-write to DDR2 and controls.

As the further scheme of the present invention: PLL reconfigurable ACS module is controlled logic module by user, phaselocked loop reconfigures Module, phase-locked loop clock output module three part form；Complete the configuration feature of FPGA output video clock.

As the further scheme of the present invention: the algorithm that video scaling module uses is bilinear interpolation, completes video and divides The scaling of resolution.

As the further scheme of the present invention: the process using FPGA to carry out clock jitter removing is to use FPGA to video counts According to carrying out frame buffer, FPGA produces clock to DA output by PLL reconfigurable ACS module simultaneously.

Compared with prior art, the invention has the beneficial effects as follows:

Present system uses FPGA to carry out conversion of resolution and the clock jitter removing design of video, reduces time delay and guarantee Audio stream stably transmits, and is carried out hand in hand the cascaded transmission of audio frequency and video by netting twine, and its engineering place and route is simple and convenient, passes Defeated time delay is low, and lossless compress image transmitting quality is high, and the long transmission distance between adjacent 2 can support 100M, permissible Meet the actual demand in all medium-and-large-sized meeting-place.

Accompanying drawing explanation

Fig. 1 is present system applied environment figure.

Fig. 2 is present system component connection figure.

Fig. 3 is present system structure diagram.

Fig. 4 is present system logical design block diagram.

Fig. 5 is present system clock diagram.

Fig. 6 is that bilinear interpolation calculates procedure chart.

Fig. 7 is video scaling module flowchart.

Fig. 8 is pll_reconfig_top module simulation point diagram structure chart.

Fig. 9 is PLL scan chain circuit figure.

Figure 10 is PLL scanning sequence figure.

Figure 11 is the module connection figure that Quartus II instrument generates.

Figure 12 is that user's phaselocked loop reconfigures Logic control module (user_reconfig_logic) state diagram.

Detailed description of the invention

Below in conjunction with the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, Obviously, described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based in the present invention Embodiment, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, all Belong to the scope of protection of the invention.

Embodiment 1

Referring to Fig. 1-Figure 12, in the embodiment of the present invention, a kind of desktop Video based on FPGA transmission system, by power supply unit Point, user interface subcard, master control process subcard and base plate subcard four part composition, power pack connect respectively user interface Card, master control process subcard and base plate subcard, and user interface subcard, master control process subcard and base plate subcard is carried out by FPC winding displacement Interconnection.

As it is shown on figure 3, wherein: 1) power pack, provide 5V unidirectional current for system, turn DC 5V module including AC220V, and Its interface circuit.

2) user interface subcard, including: analogue audio frequency input interface, VGA video input interface, local HDMI input connect Mouthful, from end DVI input interface, audio frequency and video processing unit FPGA circuitry and network input/output and corresponding interface circuit thereof.

3) master control processes subcard, including master control processing unit MCU circuit.

4) base plate subcard, including HDMI change-over circuit and HDBT input/output circuitry.

Concrete circuit connecting relation is as shown in Figure 2.MCU STM32Fxxx chip connect respectively VS100TX transmitter, FPGA EP4CE30F23C8 chip, ADV7511 chip, PHY chip, VS100RX chip, the other end of PHY chip connects IP175D exchanger chip, VS100TX transmitter is also respectively connected with IP175D exchanger chip, ADV7511 chip, VS100RX Chip is also respectively connected with IP175D exchanger chip, ADV7611 chip, and FPGA EP4CE30F23C8 chip is also respectively connected with ADV7511 chip, ADV7611 chip, ADV7604 chip, PCM1808 chip.

The key technology of present system is when different user accesses different video resolutions, output to TV or throwing The necessary display all over the screen of the resolution of shadow, and the transmission audio/video flow that system delay is stable within 100Ms.

In order to reduce time delay and ensure that audio stream stably transmits, this system uses FPGA to carry out the conversion of resolution of video Designing with clock jitter removing, owing to FPGA is processing mode based on hardware circuit, the transmission delay that each of which processes box is permissible Controlling within 1 frame, calculate according to video frame rate 60Hz, the time delay of every frame is 16.66Ms, in order to ensure that system delay controls Within 100Ms, system at most can cascade 6-7 level in theory.But the cascade of 6-7 level is agree in the application of actual large conference room Surely being inadequate, in order to increase cascade progression, MCU can be as desired to configuration video flowing be the need of the most right by FPGA Transmit after data buffer storage.Experiment shows, video flowing transmits stable output after can cascading 4 grades not over FPGA after caching, And system is almost zero propagation.So cascade number of whole system just can reach 24-28 level, almost can meet all in The actual demand in large-scale meeting-place.

Logical system design block diagram of the present invention, as shown in Figure 4.Logical system is mainly by audio/video matrix module, video contracting Amplification module, DDR2 Read-write Catrol module, IIC receiver module, PLL reconfigurable ACS module, output display module form.Modules Function the most following.

1) IIC receiver module, i.e. iic_slv, from mode module, mainly complete the CPU configuration work to FPGA.

2) DDR2 Read-write Catrol module, i.e. mem_ctrl.v mainly complete the arbitration control of the read-write to DDR2.

3) PLL reconfigurable ACS module, i.e. pll_reconfig_top.v mainly complete the configuration of FPGA output video clock Function.

4) output display module, i.e. vout_display_pro.v mainly complete display function.

5) selection that audio/video matrix module, i.e. Video_4x1, Video_5x2, Audio_4x2 complete audio frequency and video is defeated Go out.

6) video scaling module completes the scaling of video resolution.

When audio frequency and video need not caching, CPU configuration FPGA is through to DA chip, and data transmission delay now is almost Zero；When audio frequency and video need debounce or carry out resolution conversion, clock and data have to pass through DDR2 caching and convert accordingly, But also bring along time delay simultaneously.So system needs to consider clock jitter and system delay, according to reality when configuring logic Border application scenarios one suitable system of configuration.

Present system clock block diagram is as shown in Figure 5.

Each road audio frequency and video are converted into parallel clock and data are linked into FPGA, due to audio frequency and video with road clock through A/D chip Data clock all recovers from data, so the anti-ability of trembling of clock and quality can be poor.What cascade through After, the clock performance recovered can progressively be deteriorated, and in order to ensure the stable transmission of clock and data, centre must carry out debounce Dynamic process.De-jitter in present system uses FPGA that video data carries out frame buffer, and FPGA is by joining simultaneously Putting phaselocked loop, namely PLL reconfigurable ACS module produces clock to DA output.

Logical system implementation: the key modules in this logic implementations is DDR2 Read-write Catrol module, video contracting Amplification module and PLL reconfigurable ACS module.When the resolution that user accesses and output resolution ratio are inconsistent, need to carry out resolution Scaling design.Meanwhile, if user needs to change output resolution ratio, in addition it is also necessary to reconfigure the output clock of PLL.

Video scaling module designs: mainly carrying out the conversion of video resolution, the algorithm of employing is bilinear interpolation.Double Linear interpolation, is also called bilinear interpolation.Mathematically, bilinear interpolation is that the line of the interpolating function having two variablees is linearly inserted Value extension, its core concept is to carry out once linear interpolation respectively in both direction.

Assuming that source images size is m x n, target image is a x b.The side ratio of so two width images is respectively as follows: m/a And n/b.Noting, generally this ratio is not integer, floating type the to be used when of program storage.Target image (i, j) individual Pixel (i row j row) can return source images by side ratio correspondence.Its respective coordinates is (i*m/a, j*n/b).Obviously, this Respective coordinates is not the most integer, and non-integral coordinate cannot use in this discrete data of image.Two-wire Property interpolation by finding apart from nearest four pixels of this respective coordinates, calculate value (gray value or the RGB of this point Value).If image is gray level image, then (i, j) mathematics computing model of the gray value put is:

F (x, y)=b₁+b₂x+b₃y+b₄xy

Wherein b₁,b₂,b₃,b₄It it is relevant coefficient.Calculating process about it is as follows: as shown in Figure 6, it is known that Q₁₂, Q₂₂, Q₁₁, Q₂₁, but the point being intended to interpolation is P point, this will use bilinear interpolation, the most in the direction of the x axis, to R₁And R₂Two Individual clicking on row interpolation, this is very simple, then according to R₁And R₂P point is entered row interpolation, here it is so-called bilinear interpolation.

Bilinear interpolation, is also called bilinear interpolation.Mathematically, bilinear interpolation is to have the interpolating function of two variablees Linear interpolation extension, its core concept is to carry out once linear interpolation respectively in both direction.

If we expect that unknown function f is in a P=(x, value y), it is assumed that our known function f is at Q₁₁=(x₁, y₁),Q₁₂=(x₁, y₂),Q₂₁=(x₂, y₁) and Q₂₂=(x₂, y₂) value of four points.

First carry out linear interpolation in x direction, obtain

Then carry out linear interpolation in y direction, obtain

Thus obtain desired result f (x, y),

If select a coordinate system make f four known point coordinates be respectively (0,0), (0,1), (1,0) and (1, 1), then formula for interpolation can be with abbreviation just

F (x, y) ≈ f (0,0) (1-x) (1-y)+f (1,0) x (1-y)+f (0,1) (1-x) y+f (1,1) xy.

Or it is expressed as with matrix operations

The result of this interpolation method is frequently not linear, and the result of linear interpolation is unrelated with the order of interpolation.First Carrying out the interpolation in y direction, then carry out the interpolation in x direction, obtained result is the same.

1) video scaling module

Video scaling module interface signal definition is as shown in table 1.

Table 1 Scaler module interface signal definition

Signal name	Direction	Bit wide	Describe
				rst_n	INPUT	1	Chip reset signal is low effectively
clkin	INPUT	1	Scaling clock (typically takes DDR2 and exports clock)
				fifo_alempty	INPUT	1	Input FIFO almost spacing wave
rd_req	OUTPUT	1	MEMORY request signal is read before Scaler scaling
				yc_din	INPUT	16	Data from MEMORY request
frame_flag	INPUT	1	Frame sync identifications
				fifo_alfull	INPUT	1	Output FIFO almost expires signal
wr_req	INPUT	1	FIFO request signal is write after Scaler scaling
				yc_dout	OUTPUT	16	Data are write after scaling
s_width	INPUT	12	Video display width before scaling
				s_height	INPUT	12	Video display height before scaling
t_width	INPUT	12	Scaling rear video display width
				t_height	INPUT	12	Scaling rear video display height
K_h	INPUT	16	The video scaling width ratio factor
				K_v	INPUT	16	The video scaling height ratio factor

Video scaling module realizes: after system receives video input, will according to synchronizing signals such as frame synchronization, row synchronizations During valid data writing line is deposited.Row has two effects: isolate input and two different clock-domains of output and as table tennis Module improves the handling capacity of data.

According to the requirement of system scaling, video scaling module deposits middle reading related data from row.As shown in Figure 7: when During image up conversion, the Data duplication of some address during row is deposited is needed to read；During image down conversion, some data need not Participate in computing, be therefore rejected.The control signal repeating to read or give up is determined by interpolation phase generation module.Read data After, in pixel generation module, according to the weights of the corresponding each adjacent original pixels of newly-generated pixel, calculate newly-generated pixel The pixel value of point.All data processing module synchronised clocks are produced by synchronization control module, it is ensured that the synchronization of data stream and Video data can export with correct format.

The general resolution list of notebook is as follows:

Table 2

The method effect in the case of video scaling multiple is less than 2 is preferable；When scale value is more than 2, this algorithm is at literary composition The discreet portions that word shows is defective.From table 2 it can be seen that the scaling size of this system is substantially within the scope of 2 times, do not affect Picture quality.Experiment effect also demonstrates that so.

2) PLL reconfigurable ACS module

Phaselocked loop (PLL, Phase Lock Loop) Main Function is that the phase and frequency of inner/outer clock is synchronized In input reference clock.PLL is typically realized by analog circuit, and its structure is as shown in Figure 8.

PLL operation principle: PLL uses a phase-frequency detector (PFD) the rising edge of reference input clock with anti- Feedback clock alignment.When PFD detects input clock and feedback clock edge to it, phaselocked loop just locking.Voltage controlled oscillator (VCO) exporting a clock by self-vibration, feed back to the frequency-phase detector (PFD) of input simultaneously, PFD is according to the most defeated Enter the phase place of clock and feedback clock to judge the speed that VCO exports, export rising (Pump-up) simultaneously or decline (Pump- Down) signal, determines that VCO is the need of with higher or lower frequency work.The output of PFD is applied to electric charge pump (CP) and ring Path filter (LF), produces control voltage and arranges the frequency of VCO.If PFD produces rising signals, then VCO will increase.Instead It, dropping signal can reduce the frequency of VCO.

PFD exports these raising and lowering signals to electric charge pump (CP).If electric charge pump receives rising signals, electric current injects Loop filter (ICP increase).Whereas if receive dropping signal, electric current will flow out loop filter (ICP reduction).

Loop filter is converted to voltage these raising and lowering signals, as the bias voltage of VCO.Loop filter Also eliminate the interference of electric charge pump, prevent voltage overshoot, thus can minimize the shake of VCO.The voltage of ring wave filter determines The speed of VCO operation

PLL reconfigurable ACS module, the FPGA of the series such as the CycloneIV of altera corp provides the reconfigurable mould of PLL Block, such that it is able to reconfigure PLL in real time so that it is adapts to new job requirement.Such as Fig. 9-10.

Please perform the following step to reconfigure PLL enumerator

1) before moving into first (D0) of scandata, to one scanclk of major general's scanclkena home position signal Cycle.

2) serial data (scandata) is gone up along being moved in scan chain on second of scanclk.

3) all of 144 be all scanned in scan chain after, scanclkena signal is set low, to prevent in scan chain The accidental movement of position.

4) one scanclk cycle of configupdate home position signal, to use the data in scan chain to update PLL counting Device.

5) scandone signal uprises, and shows to reconfigure PLL.Trailing edge shows that PLL enumerator has made It is updated with new setting.

6) if having modified M, N, rear scaling output C enumerator or Icp, R, C are arranged, and need to use areset signal pair PLL resets.

7) step 1 can be repeated and arrive step 5, PLL be carried out arbitrary number of times and reconfigures.

PLL reconfigurable ACS module, i.e. pll_reconfig_top module, when this module mainly realizes phase-locked loop pll output The dynamic configuration of clock, this module is mainly made up of three parts, and user controls logic module, phaselocked loop reconfiguration module, phaselocked loop Clock output module.

Table 3 pll_reconfig_top module interface signal definition

Signal name	Direction	Bit wide	Describe
				rst_n	INPUT	1	Chip reset signal is low effectively
clkin	INPUT	1	Phaselocked loop input reference clock 27MHz
				clk0	OUTPUT	1	Phaselocked loop output video clock
locked	OUTPUT	1	Output clock lock indication signal
				reconfig_clk	INPUT	1	Configuration PLL reference clock 50MHz
reconfig_en	INPUT	1	Reconfigure phaselocked loop pulse triggering signal
				mifsel	INPUT	8	Reconfigure phaselocked loop MIF file and select signal
reconfig_done	INPUT	1	Configuration phaselocked loop completes signal

A reconfigurable PLL can be generated, such as ref_pll on the right of Figure 11 by the Quartus II software of Altera Shown in module；It addition, generate a reconfiguration module, such as the pll_reconfig module in the middle of Figure 11, that comes this PLL is concrete Parameter configures in real time.The module that the two Quartus II instrument generates is attached according to the mode shown in Figure 11, Then, the input port of Figure 11 listed on left margin just can be supplied to software programmers, software in real time it to be carried out weight Configuration.

By the state machine of Figure 12, logic is successfully realized real-time update clock MIF file, and obtained wanting time Clock.

Being debugged by FPGA on emulation and plate, system can stablize cascaded transmission single channel high-definition video signal, and they are adjacent two years old Transmission range between point can reach 100M, and the transmission delay of system is within 100Ms.This system is in meeting system at present Unite and particularly roundtable conference system has obtained successful Application！Well support the market demand to new product.

As it is shown in figure 1, this desktop Video system is mainly used in medium-and-large-sized meeting occasion, support multiple user video/sound Frequently equipment accesses, and supports to carry out seamless switching between video/audio source, and this system is set by multiple subscriber access terminations and transmission Standby cascade forms.

Between all user terminals, all channel C AT5E cables are together in series, and finally arrive display device, such as hand in hand one As.Accessing numerous in medium-and-large-sized group meeting occasion, conference speech person and audio/video devices, this system can ensure that each sets Standby access is convenient, is easy to again conference management.

In this system, the interface towards user is desktop multimedia socket, and HDMI/VGA video input supported by this socket, Independent audio input (3.5mm earphone jack, it can not use with HDMI audio frequency simultaneously), the external charging socket of USB and AC 220V Alternating Current Power Supply socket.

It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie In the case of the spirit or essential attributes of the present invention, it is possible to realize the present invention in other specific forms.Therefore, no matter From the point of view of which point, all should regard embodiment as exemplary, and be nonrestrictive, the scope of the present invention is by appended power Profit requires rather than described above limits, it is intended that all by fall in the implication of equivalency and scope of claim Change is included in the present invention.

Although moreover, it will be appreciated that this specification is been described by according to embodiment, but the most each embodiment only wraps Containing an independent technical scheme, this narrating mode of description is only that for clarity sake those skilled in the art should Description can also be formed those skilled in the art through appropriately combined as an entirety, the technical scheme in each embodiment May be appreciated other embodiments.

Claims

1. desktop Video based on a FPGA transmission system, it is characterised in that by power pack, user interface subcard, master control Processing subcard and base plate subcard four part composition, power pack connects user interface subcard respectively, master control processes subcard and base plate Subcard, user interface subcard, master control process subcard and base plate subcard is interconnected by FPC winding displacement；FPGA is used to regard The conversion of resolution of frequency and clock jitter removing, use FPGA to carry out the logical system of conversion of resolution of video mainly by sound/regard Frequently matrix module, DDR2 Read-write Catrol module, IIC receiver module, PLL reconfigurable ACS module, output display module, video scaling Module forms.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that power pack is system Thering is provided 5V unidirectional current, power pack includes that AC220V turns DC 5V module and interface circuit thereof.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that user interface subcard bag Include analogue audio frequency input interface, VGA video input interface, local HDMI input interface, at end DVI input interface, audio frequency and video Manage unit F PGA circuit and network input/output and corresponding interface circuit thereof.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that master control processes subcard bag Include master control processing unit MCU circuit.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that base plate subcard includes HDMI change-over circuit and HDBT input/output circuitry.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that IIC receiver module is complete Become the CPU configuration work to FPGA；Output display module completes display function；Audio/video matrix module completes the choosing of audio frequency and video Select output.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that DDR2 Read-write Catrol mould Block completes the arbitration of the read-write to DDR2 and controls.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that the reconfigurable mould of PLL Block is controlled logic module by user, phaselocked loop reconfiguration module, phase-locked loop clock output module three part form；Complete FPGA defeated Go out the configuration feature of video clock.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that video scaling module is adopted Algorithm be bilinear interpolation, complete the scaling of video resolution.

Desktop Video based on FPGA the most according to claim 1 transmission system, it is characterised in that use FPGA to enter The process of row clock debounce is to use FPGA that video data is carried out frame buffer, and FPGA is produced by PLL reconfigurable ACS module simultaneously Raw clock exports to DA.