CN106206619A - Array base palte and driving method thereof and display device - Google Patents
Array base palte and driving method thereof and display device Download PDFInfo
- Publication number
- CN106206619A CN106206619A CN201610786139.2A CN201610786139A CN106206619A CN 106206619 A CN106206619 A CN 106206619A CN 201610786139 A CN201610786139 A CN 201610786139A CN 106206619 A CN106206619 A CN 106206619A
- Authority
- CN
- China
- Prior art keywords
- thin film
- film transistor
- pixel thin
- tft
- virtual pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
Disclosure one array base palte and driving method thereof and display device, this array base palte includes: multirow pixel thin film transistor, at least a line virtual pixel thin film transistor (TFT), a plurality of grid line and a plurality of data lines, and a plurality of grid line is connected with the pixel thin film transistor of corresponding line and the grid of virtual pixel thin film transistor (TFT) respectively；A plurality of data lines is connected with the pixel thin film transistor of respective column and the source electrode of virtual pixel thin film transistor (TFT) respectively；Wherein the drain electrode of virtual pixel thin film transistor (TFT) is connected with public electrode, to provide predeterminated voltage.By the drain electrode of virtual pixel thin film transistor (TFT) being connected by via with public electrode, move data signal to predeterminated voltage when 3D shows, show black picture, it is achieved the black plug function of right and left eyes image.When 2D shows, data line voltage is charged in advance predeterminated voltage after a frame picture terminates, it is to avoid the voltage of data wire is directly jumped to positive magnitude of voltage by the magnitude of voltage born, reduces the scintillation that picture shows.
Description
Technical field
The disclosure relates in general to Display Technique field, in particular to a kind of array base palte and driving method thereof and aobvious
Showing device.
Background technology
In recent years, along with the fast development of virtual reality technology (Virtual Reality is called for short VR), to display device
It is also proposed that higher requirement, such as, 3D liquid crystal indicator can be utilized to realize VR.
Show to make 3D liquid crystal indicator realize 3D shutter, it usually needs after a frame picture shows during shutter switching
Inserting black picture, to reduce right and left eyes frame crosstalk, promotes 3D display effect.The viewing area of array base palte is provided with multirow
Pixel thin film transistor and be arranged on pixel thin film transistor coboundary and/or a line of lower boundary or two row virtual pixels are thin
Film transistor.Generally, a corresponding pixel cell of pixel thin film transistor, a virtual pixel thin film transistor (TFT) correspondence one
Individual virtual pixel cell, when (virtual) pixel thin film transistor turns on, corresponding data signal is written to corresponding (virtual)
In pixel cell.
Also need to arrange public electrode on-off circuit in the outside of the viewing area of array base palte, in order to black inserting simultaneously
During picture, all of thin film transistor (TFT) is opened, but owing to public electrode on-off circuit need to take outside viewing area certain
Width so that non-display area is broadening.Accordingly, it would be desirable to a kind of new array base palte and driving method thereof and display device.
Be only used for strengthening the understanding of background of this disclosure in information above-mentioned disclosed in described background section, therefore it
Can include not constituting the information to prior art known to persons of ordinary skill in the art.
Summary of the invention
The disclosure provides a kind of array base palte and driving method thereof and display device, to solve public electrode in prior art
On-off circuit takies the technical problem of width certain outside viewing area.
Other characteristics of the disclosure and advantage will be apparent from by detailed description below, or partially by the disclosure
Practice and acquistion.
According to an aspect of this disclosure, it is provided that a kind of array base palte, including:
Multirow pixel thin film transistor and at least a line virtual pixel thin film transistor (TFT)；
A plurality of grid line, connects with the pixel thin film transistor of corresponding line and the grid of virtual pixel thin film transistor (TFT) respectively
Connect；
A plurality of data lines, connects with the pixel thin film transistor of respective column and the source electrode of virtual pixel thin film transistor (TFT) respectively
Connect；
Wherein the drain electrode of virtual pixel thin film transistor (TFT) is connected with public electrode, to provide predeterminated voltage.
In a kind of exemplary embodiment of the disclosure, public electrode is with the first public electrode of layer with grid line, and
One public electrode is connected by the via on interlayer dielectric layer with the drain electrode of virtual pixel thin film transistor (TFT).
In a kind of exemplary embodiment of the disclosure, public electrode is to be positioned at the second common electrical above planarization layer
Pole, and the second public electrode is connected by the via on planarization layer with the drain electrode of virtual pixel thin film transistor (TFT).
In a kind of exemplary embodiment of the disclosure, the second public electrode is transparent conductive film.
In a kind of exemplary embodiment of the disclosure, at least a line virtual pixel thin film transistor (TFT) is two row virtual pixels
Thin film transistor (TFT), before being separately positioned on the first row pixel thin film transistor and after last column pixel thin film transistor.
According to an aspect of this disclosure, it is provided that the driving method of a kind of array base palte, array base palte is provided with a plurality of
Grid line, a plurality of data lines, multirow pixel thin film transistor and at least a line virtual pixel thin film transistor (TFT), driving method bag
Include:
Scanning signal is provided to pixel thin film transistor and the virtual pixel thin film transistor (TFT) of corresponding line by grid line；
Pixel thin film transistor and virtual pixel thin film transistor (TFT) by data alignment respective column provide data signal；
Thered is provided to virtual pixel thin film transistor (TFT) by the public electrode being connected with the drain electrode of virtual pixel thin film transistor (TFT)
Predeterminated voltage.
In a kind of exemplary embodiment of the disclosure, at the black plug frame that 3D shows, grid line is to virtual pixel film crystal
The scanning signal that the grid of pipe provides triggers the conducting of virtual pixel thin film transistor (TFT), and public electrode is by thin for corresponding string pixel
The data signal of film transistor and virtual pixel thin film transistor (TFT) is charged to predeterminated voltage in advance.
In a kind of exemplary embodiment of the disclosure, predeterminated voltage or is positioned at the first public electrode of layer by with grid line
The second public electrode above planarization layer provides, and wherein the first public electrode is by the via on interlayer dielectric layer and virtual representation
The drain electrode of element thin film transistor (TFT) connects, and the second public electrode is by the via on planarization layer and virtual pixel thin film transistor (TFT)
Drain electrode connects.
In a kind of exemplary embodiment of the disclosure, in the pre-charging stage that 2D shows, after a frame picture shows and terminates,
The current potential of data wire is charged to predeterminated voltage in advance.
According to an aspect of this disclosure, it is provided that a kind of display device, including above-mentioned array base palte.
Technical scheme according to the disclosure, it is possible to obtain techniques below effect:
By the drain electrode of virtual pixel thin film transistor (TFT) is connected by via with public electrode, it is achieved will when 3D shows
The data signal of viewing area moves predeterminated voltage to, shows black picture, it is achieved the black plug function of right and left eyes image, brings good
VR visual experience.Meanwhile, when 2D shows, data line voltage is charged in advance predeterminated voltage after a frame picture terminates, it is to avoid number
Directly jumped to positive magnitude of voltage according to the voltage of line by the magnitude of voltage born, the scintillation that picture shows can be reduced.
It should be appreciated that it is only exemplary that above general description and details hereinafter describe, can not be limited this
Open.
Accompanying drawing explanation
Describing its example embodiment in detail by referring to accompanying drawing, above and other target of the disclosure, feature and advantage will
Become more fully apparent.
Fig. 1 illustrates the structural representation of a kind of array base palte provided in the disclosure one related embodiment.
Fig. 2 illustrates the structural representation of a kind of array base palte that the disclosure provides.
Fig. 3 illustrates the sectional view of one of them virtual pixel thin film transistor (TFT) in Fig. 2.
Fig. 4 illustrates the profile of virtual pixel thin film transistor (TFT) in Fig. 3.
Fig. 5 illustrates that the row that liquid crystal display is generally used overturn the schematic diagram of generating positive and negative voltage switching mode.
Fig. 6 illustrates change in voltage oscillogram when usual 2D shows.
Change in voltage oscillogram when Fig. 7 illustrates 2D display in the disclosure.
Fig. 8 illustrates the structural representation of the also another kind of array base palte that the disclosure provides.
Fig. 9 illustrates the sectional view of one of them virtual pixel thin film transistor (TFT) in Fig. 8.
Figure 10 illustrates the profile of virtual pixel thin film transistor (TFT) in Fig. 9.
Figure 11 illustrates the flow chart of the driving method of a kind of array base palte that the disclosure provides.
Detailed description of the invention
It is described more fully with example embodiment referring now to accompanying drawing.But, example embodiment can be with multiple shape
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, it is provided that these embodiments make the disclosure will more
Fully and completely, and by the design of example embodiment those skilled in the art is conveyed to all sidedly.Accompanying drawing is only the disclosure
Schematic illustrations, be not necessarily drawn to scale.Reference identical in figure represents same or similar part, thus
Repetition thereof will be omitted.
Additionally, described feature, structure or characteristic can be combined in one or more enforcement in any suitable manner
In mode.In the following description, it is provided that many details thus provide fully understanding of embodiment of this disclosure.So
And, it will be appreciated by persons skilled in the art that and can put into practice the technical scheme of the disclosure and omit in described specific detail one
Or more, or other method, constituent element, device, step etc. can be used.In other cases, it is not shown in detail or describes
Known features, method, device, realization, material or operation make each side of the disclosure become mould to avoid that a presumptuous guest usurps the role of the host
Stick with paste.
Some block diagrams shown in accompanying drawing are functional entitys, it is not necessary to must be with the most independent entity phase
Corresponding.Software form can be used to realize these functional entitys or real in one or more hardware modules or integrated circuit
These functional entitys existing, or it is real to realize these functions in heterogeneous networks and/or processor device and/or microcontroller device
Body.
Fig. 1 illustrates the structural representation of a kind of array base palte provided in the disclosure one related embodiment, including: multirow picture
Element thin film transistor (TFT) T1 and be arranged on two row virtual pixel thin film transistor (TFT)s of pixel thin film transistor coboundary and lower boundary
T2.As it is shown in figure 1, the grid of each of which row pixel thin film transistor T1 is all connected on gate line M1gate, source electrode connects
On data wire, drain electrode is connected to pixel cell；The grid of every a line virtual pixel thin film transistor (TFT) T2 is all connected to virtual grid
On line VGL, this virtual grid line VGL provides a preset low level, and source electrode is connected on data wire, and drain electrode is connected to public electrode wire
On ITO1_COM, this public electrode wire provides a common electric voltage.The on top virtual pixel thin film transistor (TFT) T2 peripheral circuit on boundary
In be additionally provided with public electrode on-off circuit, including multiple thin film transistor (TFT) T3, the grid of each thin film transistor (TFT) T3 is connected to
Controlling on metal wire SW_COM_M2, source electrode is connected on data wire, and drain electrode is connected on another public electrode wire V_COM, and this is another
One public electrode wire provides a preset voltage.
Owing to the grid of virtual pixel thin film transistor (TFT) T2 is all connected in preset low level, it is in normally off, not
Work.When in order to realize 3D shutter show and need inserting black picture time, all thin film transistor (TFT)s are turned on, at public electrode
When thin film transistor (TFT) T3 in on-off circuit turns on, its drain voltage (namely preset voltage) is written to often by data wire
In one pixel cell, thus show black picture.
A kind of array base palte that the disclosure provides, including: multirow pixel thin film transistor, at least a line virtual pixel thin film
Transistor, a plurality of grid line and a plurality of data lines, a plurality of grid line respectively with pixel thin film transistor and the virtual representation of corresponding line
The grid of element thin film transistor (TFT) connects；A plurality of data lines respectively with pixel thin film transistor and the virtual pixel thin film of respective column
The source electrode of transistor connects；Wherein the drain electrode of virtual pixel thin film transistor (TFT) is connected with public electrode, to provide predeterminated voltage.
The most here " public electrode " may refer to grid with the metal electrode of layer, it is also possible to refers to different from grid
Layer, be positioned at the metal-oxide film above planarization layer.
Fig. 2 illustrates the structural representation of a kind of array base palte that the disclosure provides, including: multirow pixel thin film transistor
T1, at least a line virtual pixel thin film transistor (TFT) T2, a plurality of grid line and a plurality of data lines, a plurality of grid line respectively with corresponding line
The grid of pixel thin film transistor T1 and virtual pixel thin film transistor (TFT) T2 connects；A plurality of data lines respectively with the picture of respective column
The source electrode of element thin film transistor (TFT) T1 and virtual pixel thin film transistor (TFT) T2 connects；The wherein leakage of virtual pixel thin film transistor (TFT) T2
Pole is connected with public electrode, to provide predeterminated voltage.Public electrode therein is with the first public electrode of layer with grid line, and
One public electrode is connected by the via on interlayer dielectric layer with the drain electrode of virtual pixel thin film transistor (TFT) T2.
As in figure 2 it is shown, at least a line virtual pixel thin film transistor (TFT) T2 in the disclosure is two row virtual pixel thin film crystalline substances
Body pipe T2, before being separately positioned on the first row pixel thin film transistor T1 and after last column pixel thin film transistor T1.
It is provided with dummy shift register drive circuit, leakage by the virtual pixel thin film transistor (TFT) T2 in the first row and last column
Pole is connected on the first public electrode, when 3D shows, and the virtual pixel thin film transistor (TFT) T2 conducting of the first row and last column
Time, its drain voltage (namely predeterminated voltage) is written in each pixel cell by data wire, thus shows black picture
Face, it is achieved the black plug between left eye picture and right eye picture.
Fig. 3 illustrates the top view of one of them virtual pixel thin film transistor (TFT) in Fig. 2, and accordingly, Fig. 4 illustrates in Fig. 3 empty
Intend the profile of pixel thin film transistor.Fig. 3-Fig. 4 represents the first public electrode with M1_COM, i.e. with grid with the metal of layer
Electrode, namely the first public electrode M1_COM in Fig. 3 and gate line M1gate is same layer metal (i.e. the first metal layer) shape
Become.The one second metal level M2 with grid different layers in Fig. 3, for forming the source S in Fig. 4 and drain D.In conjunction with reference to figure
Shown in 3 and Fig. 4, by the first via K1 connection source S and semiconductor active layer SAL, by the second via K2 connection drain D with
Semiconductor active layer SAL, simultaneously also by the 3rd via K3 connection drain D and the first public electrode M1_COM, finally, by the
Four via K4 connection drain D and the second public electrode ITO1.
Referring also to shown in Fig. 4, wherein the 3rd via K3 between drain D and the first public electrode M1_COM is by right
The via that interlayer dielectric layer ILD above first public electrode M1_COM obtains through processing technique, and drain D is public with second
The 4th via K4 between common electrode ITO1 be by the planarization layer PLN above the second metal level M2 through processing technique
The via obtained.When 3D shows, virtual pixel thin film transistor (TFT) turn on, due to virtual pixel thin film transistor (TFT) drain D with
Being turned on by the 3rd via K3 between first public electrode M1_COM, drain voltage (namely write by data wire by predeterminated voltage
Enter in each pixel cell, thus show black picture, it is achieved the black plug function between left eye picture and right eye picture.
It addition, Fig. 4 also show glass substrate GS, light shield layer LS, cushion BL, planarization layer PLN, passivation layer PL with
And pixel electrode ITO2.Also, it should be noted the thin film transistor (TFT) shown in Fig. 4 is double grating structures, but not as
Limit.
Fig. 5 illustrates that the row that liquid crystal display is generally used overturn the schematic diagram of generating positive and negative voltage switching mode, works as respective pixel
When the thin film transistor (TFT) of unit turns on line by line, the generating positive and negative voltage turning on this line is overturn, becoming of i.e. original positive voltage
Negative voltage, originally negative voltage become positive voltage, simultaneously other row generating positive and negative voltage keep constant, by row upset generating positive and negative voltage
Switching can reduce the ghost problem that liquid crystal polarization causes.
Fig. 6 illustrates change in voltage oscillogram when usual 2D shows, owing to now need not " black plug " function, when positive and negative frame is cut
When changing, the negative magnitude of voltage of the 1st row gate directly jump to the positive magnitude of voltage of the 2nd row gate, i.e. negative number from Fig. 6
Directly jumping to positive data voltage according to voltage (i.e. data), so cause data voltage to change greatly, feedthrough affects
Increasing, the phenomenon of picture display flicker is the most serious.
Change in voltage oscillogram when Fig. 7 illustrates 2D display in the disclosure, although also without " black plug " function, but just
During negative frame switching, as it is shown in fig. 7, owing to data line voltage will be charged in advance predeterminated voltage, the most just after a frame picture terminates
It is first from negative data voltage to predeterminated voltage, then from predeterminated voltage to positive data voltage, is the most no longer by the voltage born
Value directly jumps to positive magnitude of voltage, it is possible to reduce the feedthrough that row reversion causes, and improves first trip display thin film transistor (TFT)
The charge rate of device, thus reduce the scintillation that picture shows.
Based on above-mentioned, the array base palte that the disclosure provides is by public with first by the drain electrode of virtual pixel thin film transistor (TFT)
Electrode is connected by the via of interlayer dielectric layer ILD, it is achieved move to the data signal of viewing area when 3D shows preset electricity
Pressure, shows black picture, it is achieved the black plug function of right and left eyes image, brings good VR visual experience.Meanwhile, when 2D shows,
Data line voltage is charged in advance predeterminated voltage, it is to avoid the voltage of data wire is directly jumped by the magnitude of voltage born after a frame picture terminates
Change to positive magnitude of voltage, the scintillation that picture shows can be reduced.
Fig. 8 illustrates the structural representation of the also another kind of array base palte that the disclosure provides, including: multirow pixel thin film crystal
Pipe T1, at least a line virtual pixel thin film transistor (TFT) T2, a plurality of grid line and a plurality of data lines, a plurality of grid line respectively with corresponding line
Pixel thin film transistor T1 and virtual pixel thin film transistor (TFT) T2 grid connect；A plurality of data lines respectively with respective column
The source electrode of pixel thin film transistor T1 and virtual pixel thin film transistor (TFT) T2 connects；Wherein virtual pixel thin film transistor (TFT) T2
Drain electrode is connected with public electrode, to provide predeterminated voltage.
Owing in the structure shown here and be not provided with grid with the first public electrode of layer, public electrode now is flat for being positioned at
The second public electrode above smoothization layer, and the drain electrode of the second public electrode and virtual pixel thin film transistor (TFT) T2 is by planarization
Via on layer connects.
Drive by being provided with dummy shift register at the virtual pixel thin film transistor (TFT) T2 of the first row and last column
Galvanic electricity road, drain electrode is connected on the second public electrode, when 3D shows, the virtual pixel film crystal of the first row and last column
During pipe T2 conducting, its drain voltage (namely predeterminated voltage) is written in each pixel cell by data wire, thus
Show black picture, it is achieved the black plug between left eye picture and right eye picture.
Fig. 9 illustrates the top view of one of them virtual pixel thin film transistor (TFT) in Fig. 8, and accordingly, Figure 10 illustrates virtual representation
The profile of element thin film transistor (TFT).In Fig. 8, ITO1_COM represents and the public electrode wire of grid G different layers, uses in Fig. 9-Figure 10
ITO1 represents the second public electrode, and this second public electrode is transparent conductive film.The Main Ingredients and Appearance of transparent conductive film is oxygen
Change indium stannum, there is good electric conductivity and the transparency.In conjunction with reference to shown in Fig. 9 and Figure 10, connect source S by the first via K1
With semiconductor active layer SAL, connect drain D and semiconductor active layer SAL by the second via K2, simultaneously also by the 4th via
K4 connection drain D and the second public electrode ITO1.Wherein the first via K1, the second via K2 and the 4th via K4 formation with
Describing accordingly in Fig. 4, here is omitted.
Owing to the array base palte shown in Fig. 8 being not provided with grid G with the first public electrode M1_COM of layer, therefore exist
During 3D display, virtual pixel thin film transistor (TFT) turns on, due to drain D and second public electrode of virtual pixel thin film transistor (TFT)
Being turned on by the 4th via K4 between ITO1, drain voltage (namely predeterminated voltage) is written to each pixel by data wire
In unit, thus show black picture, it is achieved the black plug function between left eye picture and right eye picture.
In like manner, during 2D display, when positive and negative frame switches, it is also possible to will be by data line voltage preliminary filling after a frame picture terminates
To predeterminated voltage, namely first from negative data voltage to predeterminated voltage, then from predeterminated voltage to positive data voltage, the most not
It is directly to be jumped to positive magnitude of voltage by the magnitude of voltage born again, it is possible to reduce the feedthrough that row reversion causes, improves first trip
The charge rate of display film transistor device, thus reduce the scintillation that picture shows.
Based on above-mentioned, although the array base-plate structure shown in disclosure Fig. 8 is different from Fig. 2, but equally realize 3D
The black plug function of right and left eyes image during display, reduces the effect of the scintillation that picture shows when 2D shows.
According to the result of the above two array base palte that the disclosure provides, also provide for the driving method of a kind of array base palte,
Wherein it is provided with a plurality of grid line, a plurality of data lines, multirow pixel thin film transistor and at least a line virtual representation on array base palte
Element thin film transistor (TFT), Figure 11 illustrates the flow chart of the driving method of a kind of array base palte that the disclosure provides.
As shown in figure 11, in step slo, by grid line to the pixel thin film transistor of corresponding line and virtual pixel thin film
Transistor provides scanning signal.
As shown in figure 11, in step S20, pixel thin film transistor and virtual pixel by data alignment respective column are thin
Film transistor provides data signal.
As shown in figure 11, in step s 30, by the public electrode that is connected with the drain electrode of virtual pixel thin film transistor (TFT) to
Virtual pixel thin film transistor (TFT) provides predeterminated voltage.
Predeterminated voltage VCOM therein can be provided with the first public electrode of layer by with grid line, or by being positioned at planarization
The second public electrode above Ceng provides.
With reference to shown in Fig. 3 and Fig. 4, the first public electrode M1_COM is with the metal electrode of layer with grid, is situated between by interlayer
The 3rd via K3 on matter layer is connected with the drain D of virtual pixel thin film transistor (TFT).Referring additionally to shown in Fig. 9 and Figure 10, second
Public electrode ITO1 is positioned at above planarization layer by the 4th via K4 on planarization layer PLN and virtual pixel thin film transistor (TFT)
Drain D connect.
Structure based on above two array base palte, at the black plug frame that 3D shows, grid line is to virtual pixel thin film transistor (TFT)
Grid provide scanning signal trigger virtual pixel thin film transistor (TFT) conducting, public electrode is by corresponding string pixel thin film
The data signal of transistor and virtual pixel thin film transistor (TFT) is charged to predeterminated voltage in advance, and such drain voltage (is namely preset
Voltage) be written in each pixel cell by data wire, thus show black picture, it is achieved left eye picture and right eye picture it
Between black plug function.
It addition, the pre-charging stage shown at 2D, after a frame picture shows and terminates, the current potential of data wire is charged to preset in advance
Voltage, so when positive and negative frame switches, owing to will be charged to predeterminated voltage in advance, also after a frame picture terminates by data line voltage
It is exactly first from negative data voltage to predeterminated voltage, then from predeterminated voltage to positive data voltage, is the most no longer by the electricity born
Pressure value directly jumps to positive magnitude of voltage, it is possible to reduce the feedthrough that row reversion causes, and improves first trip display film crystal
The charge rate of tube device, thus reduce the scintillation that picture shows.
In sum, the disclosure finally also provides for a kind of display device, including the array shown in above-mentioned Fig. 2 or Fig. 8
Substrate.
How to form and use particular example it will be clearly understood that present disclosure describes, but the principle of the disclosure is not limited to
Any details of these examples.On the contrary, teaching based on disclosure disclosure, these principles can be applied to many other
Embodiment.
More than it is particularly shown and described the illustrative embodiments of the disclosure.It should be appreciated that the disclosure does not limits
In detailed construction described herein, set-up mode or implementation method；On the contrary, the disclosure is intended to contain be included in claims
Spirit and scope in various amendments and equivalence arrange.
Claims (10)
1. an array base palte, it is characterised in that including:
Multirow pixel thin film transistor and at least a line virtual pixel thin film transistor (TFT)；
A plurality of grid line, respectively with the described pixel thin film transistor of corresponding line and the grid of described virtual pixel thin film transistor (TFT)
Connect；
A plurality of data lines, respectively with the described pixel thin film transistor of respective column and the source of described virtual pixel thin film transistor (TFT)
Pole connects；
The drain electrode of wherein said virtual pixel thin film transistor (TFT) is connected with public electrode, to provide predeterminated voltage.
Array base palte the most according to claim 1, it is characterised in that described public electrode is with the of layer with described grid line
One public electrode, and the drain electrode of described first public electrode and described virtual pixel thin film transistor (TFT) is by interlayer dielectric layer
Via connects.
Array base palte the most according to claim 1, it is characterised in that described public electrode is to be positioned at above planarization layer
Second public electrode, and the drain electrode of described second public electrode and described virtual pixel thin film transistor (TFT) is by planarization layer
Via connects.
Array base palte the most according to claim 3, it is characterised in that described second public electrode is transparent conductive film.
Array base palte the most according to claim 1, it is characterised in that described at least a line virtual pixel thin film transistor (TFT) is
Two row virtual pixel thin film transistor (TFT)s, before being separately positioned on the first row pixel thin film transistor and last column pixel thin film
After transistor.
6. a driving method for array base palte, described array base palte is provided with a plurality of grid line, a plurality of data lines, multirow pixel
Thin film transistor (TFT) and at least a line virtual pixel thin film transistor (TFT), it is characterised in that described driving method includes:
Scanning is provided to described pixel thin film transistor and the described virtual pixel thin film transistor (TFT) of corresponding line by described grid line
Signal；
Described pixel thin film transistor and described virtual pixel thin film transistor (TFT) by described data alignment respective column provide number
The number of it is believed that；
By the public electrode that is connected with the drain electrode of described virtual pixel thin film transistor (TFT) to described virtual pixel thin film transistor (TFT)
Predeterminated voltage is provided.
Driving method the most according to claim 6, it is characterised in that at the black plug frame that 3D shows, described grid line is to described
The described scanning signal that the grid of virtual pixel thin film transistor (TFT) provides triggers the conducting of described virtual pixel thin film transistor (TFT), described
Public electrode is by corresponding string pixel thin film transistor and the data signal preliminary filling of described virtual pixel thin film transistor (TFT)
To described predeterminated voltage.
Driving method the most according to claim 7, it is characterised in that described predeterminated voltage by with described grid line with the of layer
One public electrode or be positioned at above planarization layer second public electrode provide, wherein said first public electrode is situated between by interlayer
Via on matter layer is connected with the drain electrode of described virtual pixel thin film transistor (TFT), and described second public electrode is by planarization layer
Via be connected with the drain electrode of described virtual pixel thin film transistor (TFT).
Driving method the most according to claim 6, it is characterised in that in the pre-charging stage that 2D shows, a frame picture shows
After showing end, the current potential of described data wire is charged to described predeterminated voltage in advance.
10. a display device, it is characterised in that include the array base palte according to any one of claim 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610786139.2A CN106206619B (en) | 2016-08-31 | 2016-08-31 | Array substrate and its driving method and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610786139.2A CN106206619B (en) | 2016-08-31 | 2016-08-31 | Array substrate and its driving method and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106206619A true CN106206619A (en) | 2016-12-07 |
| CN106206619B CN106206619B (en) | 2019-10-11 |
Family
ID=58087001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610786139.2A Active CN106206619B (en) | 2016-08-31 | 2016-08-31 | Array substrate and its driving method and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106206619B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106773420A (en) * | 2017-02-06 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of array base palte, display device and its driving method |
| CN107065366A (en) * | 2017-06-19 | 2017-08-18 | 深圳市华星光电技术有限公司 | Array base palte and its driving method |
| CN108776403A (en) * | 2018-03-30 | 2018-11-09 | 友达光电股份有限公司 | Pixel structure and touch panel |
| CN109461718A (en) * | 2018-10-22 | 2019-03-12 | 昆山国显光电有限公司 | Display panel and display device |
| WO2019227791A1 (en) * | 2018-05-28 | 2019-12-05 | 武汉华星光电技术有限公司 | Gate driver on array circuit |
| US10852608B1 (en) | 2019-05-15 | 2020-12-01 | Au Optronics Corporation | Display panel and manufacturing method thereof |
| CN113782543A (en) * | 2020-08-21 | 2021-12-10 | 友达光电股份有限公司 | Pixel array substrate |
| US11605351B2 (en) | 2020-12-31 | 2023-03-14 | Shanghai Tianma AM-OLED Co., Ltd. | Display panel having a compensation unit for leakage current, driving method thereof and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006016662A1 (en) * | 2004-08-11 | 2006-02-16 | Sanyo Electric Co., Ltd. | Semiconductor element matrix array and manufacturing method of the same, and display panel |
| CN101296330A (en) * | 2007-04-23 | 2008-10-29 | 索尼株式会社 | Solid-state image pickup device, a method of driving the same, a signal processing method for the same |
| CN101882430A (en) * | 2010-07-02 | 2010-11-10 | 深超光电（深圳）有限公司 | Method for driving liquid crystal display device |
| CN104103234A (en) * | 2013-04-01 | 2014-10-15 | 三星显示有限公司 | Organic light-emitting display device, method of repairing the same, and method of driving the same |
| CN104280968A (en) * | 2014-10-31 | 2015-01-14 | 深圳市华星光电技术有限公司 | Liquid crystal panel and pixel black insertion method during 3D display of liquid crystal panel |
| CN105845082A (en) * | 2015-01-28 | 2016-08-10 | 三星显示有限公司 | Organic light emitting display apparatus |
-
2016
- 2016-08-31 CN CN201610786139.2A patent/CN106206619B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006016662A1 (en) * | 2004-08-11 | 2006-02-16 | Sanyo Electric Co., Ltd. | Semiconductor element matrix array and manufacturing method of the same, and display panel |
| CN101296330A (en) * | 2007-04-23 | 2008-10-29 | 索尼株式会社 | Solid-state image pickup device, a method of driving the same, a signal processing method for the same |
| CN101882430A (en) * | 2010-07-02 | 2010-11-10 | 深超光电（深圳）有限公司 | Method for driving liquid crystal display device |
| CN104103234A (en) * | 2013-04-01 | 2014-10-15 | 三星显示有限公司 | Organic light-emitting display device, method of repairing the same, and method of driving the same |
| CN104280968A (en) * | 2014-10-31 | 2015-01-14 | 深圳市华星光电技术有限公司 | Liquid crystal panel and pixel black insertion method during 3D display of liquid crystal panel |
| CN105845082A (en) * | 2015-01-28 | 2016-08-10 | 三星显示有限公司 | Organic light emitting display apparatus |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106773420A (en) * | 2017-02-06 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of array base palte, display device and its driving method |
| CN107065366A (en) * | 2017-06-19 | 2017-08-18 | 深圳市华星光电技术有限公司 | Array base palte and its driving method |
| CN108776403A (en) * | 2018-03-30 | 2018-11-09 | 友达光电股份有限公司 | Pixel structure and touch panel |
| WO2019227791A1 (en) * | 2018-05-28 | 2019-12-05 | 武汉华星光电技术有限公司 | Gate driver on array circuit |
| US11004380B2 (en) | 2018-05-28 | 2021-05-11 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Gate driver on array circuit |
| CN109461718A (en) * | 2018-10-22 | 2019-03-12 | 昆山国显光电有限公司 | Display panel and display device |
| US10852608B1 (en) | 2019-05-15 | 2020-12-01 | Au Optronics Corporation | Display panel and manufacturing method thereof |
| CN113782543A (en) * | 2020-08-21 | 2021-12-10 | 友达光电股份有限公司 | Pixel array substrate |
| CN113782543B (en) * | 2020-08-21 | 2023-05-16 | 友达光电股份有限公司 | Pixel array substrate |
| US11605351B2 (en) | 2020-12-31 | 2023-03-14 | Shanghai Tianma AM-OLED Co., Ltd. | Display panel having a compensation unit for leakage current, driving method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206619B (en) | 2019-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106206619B (en) | Array substrate and its driving method and display device | |
| CN102541343B (en) | 3-dimensional flat panel display with built-in touch screen panel | |
| TWI460517B (en) | Display panel and pixel therein and driving method in display panel | |
| CN102385201B (en) | Pixel array, pixel structure and driving method of pixel structure | |
| US9488877B2 (en) | Electrically-driven liquid crystal lens, display device and 3D liquid crystal display method | |
| US9052540B2 (en) | Array substrate and liquid crystal display panel | |
| CN103268043B (en) | A kind of array base palte and liquid crystal indicator | |
| US20130027439A1 (en) | Display apparatus | |
| CN103941442B (en) | Display floater and driving method thereof | |
| US20170344145A1 (en) | Method and apparatus for reducing pin count in in-cell touch display driver ic | |
| JP6208886B2 (en) | Alignment substrate and liquid crystal display panel | |
| CN104297969A (en) | Liquid crystal display panel, discharging method thereof and display device | |
| KR20150004225A (en) | Display device | |
| CN102651203B (en) | Display equipment and driving method thereof | |
| CN103389604A (en) | Array substrate and liquid crystal display panel | |
| US9581824B2 (en) | Three-dimensional (3D) display device | |
| CN205982852U (en) | Three -dimensional image display device and liquid crystal display panel | |
| CN103353698A (en) | Array substrate and liquid crystal display panel | |
| TW200949815A (en) | Electro-optical device, driving method thereof and electronic apparatus | |
| CN105487312A (en) | Array substrate, display device and driving method of display device | |
| CN102650781B (en) | Pixel structure and control method thereof used for stereo display | |
| US20120162208A1 (en) | 2d/3d image display device | |
| CN103472650B (en) | Liquid crystal lens and 3d display device | |
| WO2020001266A1 (en) | Display control method and apparatus, display apparatus, storage medium, and computer device | |
| KR101878482B1 (en) | Stereoscopic image display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |