CN106206517A - Semiconductor device and the manufacture method of semiconductor device - Google Patents
Semiconductor device and the manufacture method of semiconductor device Download PDFInfo
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- CN106206517A CN106206517A CN201510977812.6A CN201510977812A CN106206517A CN 106206517 A CN106206517 A CN 106206517A CN 201510977812 A CN201510977812 A CN 201510977812A CN 106206517 A CN106206517 A CN 106206517A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
The semiconductor device of the damage that semiconductor chip is caused by embodiments of the present invention a kind of lit-par-lit structure that can reduce semiconductor chip of offer when mounted and the manufacture method of semiconductor device.The semiconductor device of embodiment constitutes die-stacks (TA1) by laminated semiconductor chip (P1～P8), distance piece (8) is configured at least some of overlapping position with pad electrode (10), sealing resin (12) fills interval (SP1, SP2), and encapsulating chip duplexer (TA1) integratedly integratedly.
Description
[related application]
The application enjoys and applying for based on Japanese patent application 2015-111082 (applying date: on June 1st, 2015)
The priority of case.The application comprises the full content of basis application case by referring to this basis application case.
Technical field
Embodiments of the present invention relate to the manufacture method of a kind of semiconductor device and semiconductor device.
Background technology
Have semiconductor chip stacking to realize the saving spatialization, high performance and high capacity of semiconductor device
Situation.The electrical connection of the semiconductor chip of stacking in order to realize and have use to be referred to as TSV (Through Silicon Via)
The situation of through electrode.
Summary of the invention
One embodiment of the present invention provides a kind of lit-par-lit structure of semiconductor chip that can reduce when mounted to quasiconductor
The semiconductor device of the damage that chip causes and the manufacture method of semiconductor device.
According to an embodiment of the present invention, possess the N through stacking (N is the integer of more than 2) individual semiconductor chip,
Spacing body and pad electrode.At stacked direction, distance piece guarantees that the 1st is spaced between described semiconductor chip.Pad electrode sets
One side in the semiconductor chip of n-th layer.At least some of overlapping position with described pad electrode configures
State distance piece.
Accompanying drawing explanation
Fig. 1 (a) is the top view of the schematic configuration of the semiconductor device representing the 1st embodiment, and Fig. 1 (b) is to represent the 1st
The sectional view of the schematic configuration of the semiconductor device of embodiment.
Fig. 2 is the sectional view of the manufacture method of the semiconductor device representing the 1st embodiment.
Fig. 3 (a) and Fig. 3 (b) is the sectional view of the manufacture method of the semiconductor device representing the 1st embodiment.
Fig. 4 is the top view of the schematic configuration of the semiconductor device representing the 2nd embodiment.
Fig. 5 (a) is the top view of the schematic configuration of the semiconductor device representing the 3rd embodiment, and Fig. 5 (b) is to represent the 3rd
The sectional view of the schematic configuration of the semiconductor device of embodiment.
Fig. 6 (a) is the top view of the schematic configuration of the semiconductor device representing the 4th embodiment, and Fig. 6 (b) is to represent the 4th
The sectional view of the schematic configuration of the semiconductor device of embodiment.
Detailed description of the invention
Describe the semiconductor device of embodiment referring to the drawings in detail.It addition, the plurality of embodiment does not limit
Determine the present invention.
(the 1st embodiment)
Fig. 1 (a) is the top view of the schematic configuration of the semiconductor device representing the 1st embodiment, and Fig. 1 (b) is to represent the 1st
The sectional view of the schematic configuration of the semiconductor device of embodiment.It addition, in the following embodiments, exemplary semiconductor
The composition that chip laminate is 8 layers, but the composition of alternatively semiconductor chip stacking N (N is the integer of more than 2) layer.Additionally,
In the following embodiments, it is to illustrate NAND flash as semiconductor device, but semiconductor device both can be
DRAM(Dynamic Random Access Memory)、FRAM(Ferroelectric Random Access
Memory) (registered trade mark), MRAM (Magnetoresistive Random Access Memory), PCRAM (Phase
Change Random Access Memory) etc., it is possible to for logic circuit or processor etc..
In Fig. 1 (a) and Fig. 1 (b), constitute die-stacks TA1 by laminated semiconductor chip P1～P8.Now,
The thickness of each semiconductor chip P1～P8 can be set as below 40 μm.In order to prevent during process die-stacks TA1
Die-stacks TA1 is destroyed, it is possible to via tack coat 2, die-stacks TA1 is fixed on gripper shoe 1.Support
Plate 1 such as can use the metallic plates such as lead frame.The material of gripper shoe 1 can be Cu, it is possible to be 42 alloy (Fe-Ni
It is alloy).Tack coat 2 can use insulative resin, it is possible to use chip attachment film.
It is provided with unit area MA1, MA2 at each semiconductor chip P1～P8.At each unit region MA1, MA2 energy
NAND cell is enough set in array-like or the peripheral circuit such as sense amplifier or decoder is set.Now, at each list
Unit region MA1, MA2 are able to maintain that the mode of the systematicness of the configuration of unit pattern configures NAND cell.
It is provided with through electrode 5 at each semiconductor chip P2～P8.Now, can be not provided with through at semiconductor chip P1
Electrode 5.Each through electrode 5 is to be insulated with semiconductor chip P2～P8 by side wall insulating film 4.Through electrode 5
Material can use Cu, Ni or Al etc..It also is able to there is TiN etc. between through electrode 5 and side wall insulating film 4
Barrier metal film.At each semiconductor chip P2～P8, through electrode 5 can be configured at do not upset each unit region MA1,
The position of the systematicness of the configuration of the unit pattern of MA2.Therefore, through electrode 5 should not be located at each unit region MA1,
In MA2, it is preferably disposed to around each unit region MA1, MA2.In this, by maintain each unit region MA1,
The systematicness of the configuration of the unit pattern of MA2, it is possible to promote resolution during exposure such that it is able to improve NAND mono-
The integrated level of unit.Additionally, in order to prevent each semiconductor chip P1 of causing because of the warpage of each semiconductor chip P1～P8～
The bad connection of the through electrode 5 between P8, through electrode 5 also is able to be located between each unit region MA1, MA2.
One side at semiconductor chip P1 is provided with electrode 6A.One side at each semiconductor chip P2～P7 is provided with electrode 6B,
One side at semiconductor chip P8 is provided with electrode 6C, 6D.Additionally, the one side of semiconductor chip P8 be provided with distribution 9C,
9D.Distribution 9D can be configured at the signal by distribution 9D and not disturb the position of the signal by through electrode 5.?
The another side of each semiconductor chip P2～P8 is provided with electrode 7B.
In each semiconductor chip P2～P7, electrode 6B is electrically connected to the one side of through electrode 5.At semiconductor chip
P8, distribution 9C are electrically connected to the one side of through electrode 5, and electrode 6C is electrically connected to distribution 9C.Additionally, at quasiconductor
Chip P8, electrode 6D are electrically connected to distribution 9D.It is provided with pad electrode 10 in the end of distribution 9D.At each quasiconductor
Chip P2～P8, electrode 7B are electrically connected to the another side of through electrode 5.The electrode 6A electrical connection of semiconductor chip P1
Electrode 7B in semiconductor chip P2.Between semiconductor chip P2～P8, at the semiconductor chip that stacked direction is adjacent
The electrode 6B of P2～P8 is connected with electrode 7B.One side at semiconductor chip P8 is provided with interface (IF) chip 3.It addition,
Interface chip 3 can carry out data communication with each semiconductor chip P1～P8.The data that interface chip will input from outside
Send to each semiconductor chip P1～P8, and the data sent from each semiconductor chip P1～P8 are exported to outside.This
Time, interface chip 3 can send write data, order or ground via through electrode 5 to each semiconductor chip P1～P8
Location, or receive reading data from each semiconductor chip P1～P8.It also is able to replace interface chip 3, and arranges and carry out respectively
The controller chip of the Read-write Catrol of semiconductor chip P1～P8.It is provided with electrode 7C, 7D at interface chip 3.Quasiconductor
Electrode 6C, 6D of chip P8 is connected to electrode 7C, 7D of interface chip 3.It addition, in order to ensure quasiconductor
Interval SP1 between chip P1～P8, electrode 6A, 6B or electrode 7B can use the projection electrodes such as solder ball.Now,
Electrode 6A, 6B and electrode 7B two sides can be projection electrode, it is possible to for the combination of projection electrode Yu plane electrode.Electricity
The material of pole 6A, 6B and electrode 7B can be the monofilm of Au, Cu, Ni, Sn, Pg, Ag etc., it is possible to for stacking
Film.In the case of the materials'use solder material of electrode 6A, 6B and electrode 7B, such as can use Sn-Cu alloy,
Sn-Ag alloy etc..The material of distribution 9C, 9D can use such as Cu etc..The material of pad electrode 10 can make use-case
Such as Ni or the Ni/Pd structure etc. being formed on Cu.The surface that can also construct at Ni or Ni/Pd of pad electrode 10
Au tunicle is set.Also Sn plating is implemented on the surface that can construct Ni or Ni/Pd of pad electrode 10.
Between semiconductor chip P1～P8, it is provided with the stacked direction at described chip guarantees to be spaced the distance piece 8 of SP1.Between
Can be set in the range of about 10～20 μm every SP1.In order to not hinder to the sealing resin 12 being spaced SP1
Fillibility, the interval between distance piece 8 is preferably set to interval more than the SP1 of semiconductor chip P1～P8.Distance piece 8
Material can use and not reach at a temperature of the junction temperature of electrode 6A, 6B, 6C, 6D and electrode 7B, 7C, 7D
The insulative resin that can bond.Such as, in the feelings that electrode 6A, 6B, 6C, 6D are welded with electrode 7B, 7C, 7D
Under condition, it is possible to use less than the insulative resin that can bond at a temperature of the reflow temperature of solder.Such as, distance piece 8
Material can use epoxy resin, polyimide resin, acrylic resin, phenol resin or benzocyclobutane olefine resin etc..
In this, distance piece 8 can strengthen the through electrode 5 maintenance to interval SP1.Now, distance piece 8 can be configured at list
On unit region MA1, MA2.Thus, in the way of avoiding in each unit region MA1, MA2, through electrode is being configured
In the case of 5, it is also possible to stably maintain the interval SP1 between semiconductor chip P1～P8.Additionally, distance piece 8 can
It is configured at least some of overlapping position with pad electrode 10.Thus, pad electrode 10 is being applied with loading
In the case of, it is also possible to maintain the interval SP1 between semiconductor chip P1～P8 by distance piece 8.Therefore, it is possible to reduce
Damage when die-stacks TA1 flip is installed, semiconductor chip P1～P8 caused such that it is able to prevent quasiconductor
The destruction of chip P1～P8.
Die-stacks TA1 be highlighted electrode 11 support state and flip is installed on installation base plate 21.Now,
Interval SP2 it is provided with between die-stacks TA1 and installation base plate 21.This interval SP2 can be set as that 50 μm are left
Right.Interface chip 3 can be configured at interval SP2.Another side at installation base plate 21 is provided with ground electrode 22A and print
Brush distribution 22B, the another side at installation base plate 21 is provided with ground electrode 24A and printed wiring 24B.Ground electrode 22A
Surrounding and printed wiring 22B covered by solder resist 23.The surrounding of ground electrode 24A and printed wiring 24B are by welding resistance
Agent 25 covers.Projection electrode 11 is engaged in pad electrode 10 and ground electrode 22A.Projection electrode 26 is engaged in ground connection
Electrode 24A.The material of projection electrode 11,26 can be the monofilm of Au, Cu, Ni, Sn, Pg, Ag etc., it is possible to
For stacked film.In the case of the materials'use solder material of projection electrode 11,26, such as can use Sn-Cu alloy,
Sn-Ag alloy etc..The material of ground electrode 22A, 24A and printed wiring 22B, 24B can use Cu etc..Also may be used
Au tunicle is formed with the part exposed from solder resist 23,25 in ground electrode 22A, 24A.Installation base plate 21
Base material can use such as BT (Bismaleimide Triazine, Bismaleimide Triazine) resin etc..
Installation base plate 21 is provided with sealing resin 12.Interval SP1, SP2 can be filled and by core by sealing resin 12
Laminate TA1 seals.Now, sealing resin 12 can be completely covered semiconductor chip P1 on installation base plate 21
～P8 and interface chip 3.This sealing resin 12 can use mold resin.Now, sealing resin 12 can be used as
Underfill resin plays a role.This sealing resin 12 can use the epoxy resin being mixed into silica as filler.
Now, the mean diameter of filler can be set in the range of 0.5～3 μm.The content of filler can be set in 60～75
In the range of wt%.
In this, by sealing resin 12, semiconductor chip P1～P8 is sealed with interface chip 3, and to interval SP1,
SP2 fills sealing resin 12, thus need not arrange underfill resin outside the mold step of die-stacks TA1 separately
Filling step, it is possible to reduce semiconductor chip P1～P8 installation time number of steps.
Fig. 2, Fig. 3 (a) and Fig. 3 (b) are the sectional views of the manufacture method of the semiconductor device representing the 1st embodiment.Separately
Outward, in this manufacture method, illustrate situation about electrode 6A, 6B, 6C, 6D being welded with electrode 7B, 7C, 7D.
In fig. 2, by the another side of semiconductor chip P1 and gripper shoe 1 to in the way of, will half via tack coat 2
Conductor chip P1 is fixed on gripper shoe 1.On the other hand, it is formed with through electrode 5 at each semiconductor chip P2～P8.
Afterwards, the another side at each semiconductor chip P2～P8 forms distance piece 8.Then, at the bar not reaching solder refiow temperature
Under part, each semiconductor chip P2～Jie's P8 compartment spacing body 8 are in turn secured to semiconductor chip P1～P7 of its lower floor,
And interface chip 3 is configured on semiconductor chip P8.Now, it is possible to temperature is remained regularly about 110 DEG C.
Then, as shown in Fig. 3 (a), by semiconductor chip P1～P8 and interface chip 3 are heated to reflow temperature with
Upper (such as 240 DEG C), are engaged in the electrode 7B of semiconductor chip P2 respectively by the electrode 6A of semiconductor chip P1, will
The electrode 6B of semiconductor chip P2～P7 is engaged in the electrode 7B of semiconductor chip P3～P8, and by semiconductor chip
Electrode 6C, 6D of P8 is individually coupled to electrode 7C, 7D of interface chip 3.
Then, as shown in Fig. 3 (b), via projection electrode 11, flip is installed on installation base plate 21 to die-stacks TA1
On.Now, owing to die-stacks TA1 is supported by gripper shoe 1, it is possible to do not destroy die-stacks TA1 ground
Process die-stacks TA1.Additionally, due at least some of overlapping position configuration space with pad electrode 10
Part 8, even if so in the case of semiconductor chip P1～P8 being applied with loading via projection electrode 11, also can
Enough prevent being spaced SP1 crushed such that it is able to protection semiconductor chip P1～P8.
Then, die-stacks TA1 being installed on installation base plate 21 is configured to mould.Then, by core
Laminate TA1 carries out mold shaping, and utilizes sealing resin 12 by semiconductor chip P1～P8 and interface chip 3
Seal.Sealing resin 12 can be filled to being spaced SP1, SP2 when the mold of this die-stacks TA1 shapes.
In this, each semiconductor chip P2～P8 is fixed on semiconductor chip P1～P7 of its lower floor by Jie's compartment spacing body 8,
The most each semiconductor chip P2～P8 often stacking 1 layer need not just carry out 1 reflow.Therefore, each semiconductor chip P2～
P8 often stacking 1 layer need not just be repeated 1 times gradient of temperature such that it is able to improves yield, and can reduce through electrode 5
Thermal stress Deng applying.
(the 2nd embodiment)
Fig. 4 is the top view of the schematic configuration of the semiconductor device representing the 2nd embodiment.
In the composition of Fig. 4, replace the distance piece 8 of Fig. 1 (a) that distance piece 8A, 8B are set.Distance piece 8A, 8B
At least some of overlapping position with pad electrode 10 can be configured at.Now, 1 pad electrode 10 can be overlapping
Mode in multiple distance piece 8A, 8B configures.Thus, even if in the case of pad electrode 10 is applied with loading,
It also is able to maintain the interval SP1 between semiconductor chip P1～P8 by distance piece 8A, 8B.
(the 3rd embodiment)
Fig. 5 (a) is the top view of the schematic configuration of the semiconductor device representing the 3rd embodiment, and Fig. 5 (b) is to represent the 3rd
The sectional view of the schematic configuration of the semiconductor device of embodiment.
In the composition of Fig. 5 (a) and Fig. 5 (b), replace die-stacks TA1 that die-stacks TA2 is set.At chip
Duplexer TA2, replaces semiconductor chip P1 to arrange semiconductor chip P1'.The thickness of semiconductor chip P1' can be thick
Thickness in semiconductor chip P2～P8.Now, the thickness of semiconductor chip P1' can be set as stably supporting
Die-stacks TA2.For instance, it is possible to the thickness of semiconductor chip P1' is set as more than 100 μm.Semiconductor chip
P1' is upper can be not provided with through electrode 5.It is provided with unit area MA1', MA2' at semiconductor chip P1'.Unit area
MA1', MA2' can be constituted in the same manner as unit area MA1, MA2.
In this, utilize semiconductor chip P1' supporting-core laminate TA2, it is possible to gripper shoe 1 and tack coat 2 are removed,
Constitute it is thus possible to simplify.
(the 4th embodiment)
Fig. 6 (a) is the top view of the schematic configuration of the semiconductor device representing the 4th embodiment, and Fig. 6 (b) is to represent the 4th
The sectional view of the schematic configuration of the semiconductor device of embodiment.
In the composition of Fig. 6 (a) and Fig. 6 (b), replace die-stacks TA1 that die-stacks TA3 is set.At chip
Duplexer TA3, replaces distance piece 8 to arrange distance piece 8'.Distance piece 8' can be configured to membranaceous.Such as, cellular zone
Territory MA1, MA2 are able to be covered by 1 distance piece 8'.Now, a part of distance piece 8' can be configured at
The position of pad electrode 10 overlap.Thus, even if in the case of pad electrode 10 is applied with loading, it is also possible to logical
Super-interval part 8' maintains the interval SP1 between semiconductor chip P1～P8.
Although being illustrated some embodiments of the present invention, but the plurality of embodiment is to carry as example
Show, it is not intended to limit the scope of invention.The embodiment of the plurality of novelty can be implemented with other various forms, and
Without departing from carrying out various omission in the range of inventive concept, replace, change.The plurality of embodiment or its change
It is contained in scope and the purport of invention, and is contained in the invention described in claim and equivalency range thereof.
[explanation of symbol]
1 gripper shoe
2 tack coats
3 interfaces (IF) chip
P1～P8 semiconductor chip
MA1, MA2 unit area
4 side wall insulating films
5 through electrodes
6A～6D electrode
7A～7D electrode
8 distance pieces
9C, 9D distribution
10 pad electrode
11,26 projection electrode
12 sealing resins
21 installation base plates
22A, 24A ground electrode
22B, 24B printed wiring
23,25 solder resist
Claims (5)
1. a semiconductor device, it is characterised in that possess: through N number of semiconductor chip of stacking；Wherein, N is more than 2
Integer,
At stacked direction, distance piece, guarantees that the 1st is spaced between described semiconductor chip；And
Pad electrode, is located at the one side of the semiconductor chip of n-th layer；And
Described distance piece is configured at least some of overlapping position with described pad electrode.
Semiconductor device the most according to claim 1, it is characterised in that: each semiconductor chip of the 2nd layer to n-th layer
Possesses the through electrode of through described each semiconductor chip.
Semiconductor device the most according to claim 2, it is characterised in that possess: substrate, with described pad electrode pair
To mode be provided with the semiconductor chip of described N shell；
Projection electrode, guarantees that the 2nd is spaced between the semiconductor chip and described substrate of described n-th layer, and by institute
State pad electrode to electrically connect with described substrate；And
Sealing resin, fills described 1st interval and described 2nd interval, and seals the semiconductor chip of described N shell.
Semiconductor device the most according to claim 3, it is characterised in that: described semiconductor chip is semiconductor memory,
And there is IF chip, the data exported from described semiconductor memory are sent to outside by described IF chip,
And the data inputted from outside are sent to described semiconductor memory, and in described substrate and the half of described n-th layer
Described 2nd interval it is thinner than between conductor chip.
5. the manufacture method of a semiconductor device, it is characterised in that: it is interposed between semiconductor chip and guarantees at stacked direction
1 interval distance piece and by N number of for described semiconductor chip stacking, wherein, N is the integer of more than 2,
It is interposed between the semiconductor chip of n-th layer and installation base plate and guarantees the 2nd projection electrode being spaced and by described
The semiconductor chip of N shell is installed on described installation base plate,
Fill sealing resin to described 1st interval and described 2nd interval, and sealed by described sealing resin described
The semiconductor chip of N shell.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015111082A JP2016225484A (en) | 2015-06-01 | 2015-06-01 | Semiconductor device and method of manufacturing the same |
| JP2015-111082 | 2015-06-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106206517A true CN106206517A (en) | 2016-12-07 |
| CN106206517B CN106206517B (en) | 2019-11-08 |
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| CN201510977812.6A Active CN106206517B (en) | 2015-06-01 | 2015-12-23 | The manufacturing method of semiconductor device and semiconductor device |
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| JP (1) | JP2016225484A (en) |
| CN (1) | CN106206517B (en) |
| TW (1) | TWI642162B (en) |
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| CN109690771A (en) | 2016-09-23 | 2019-04-26 | 东芝存储器株式会社 | Storage device |
| JP2021044362A (en) * | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100171208A1 (en) * | 2009-01-06 | 2010-07-08 | Elpida Memory, Inc. | Semiconductor device |
| US20110147945A1 (en) * | 2009-12-17 | 2011-06-23 | Elpida Memory, Inc. | Semiconductor device capable of suppressing generation of cracks in semiconductor chip during manufacturing process |
| CN103022021A (en) * | 2011-09-22 | 2013-04-03 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090014856A1 (en) * | 2007-07-10 | 2009-01-15 | International Business Machine Corporation | Microbump seal |
| US8710654B2 (en) * | 2011-05-26 | 2014-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| JP2014192171A (en) * | 2013-03-26 | 2014-10-06 | Ps4 Luxco S A R L | Semiconductor device and manufacturing method of the same |
| KR102065648B1 (en) * | 2013-08-14 | 2020-01-13 | 삼성전자주식회사 | Semiconductor package |
| JP2015056563A (en) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | Semiconductor device and method of manufacturing the same |
| US9570421B2 (en) * | 2013-11-14 | 2017-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure |
-
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- 2015-12-18 TW TW104142826A patent/TWI642162B/en active
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100171208A1 (en) * | 2009-01-06 | 2010-07-08 | Elpida Memory, Inc. | Semiconductor device |
| US20110147945A1 (en) * | 2009-12-17 | 2011-06-23 | Elpida Memory, Inc. | Semiconductor device capable of suppressing generation of cracks in semiconductor chip during manufacturing process |
| CN103022021A (en) * | 2011-09-22 | 2013-04-03 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI642162B (en) | 2018-11-21 |
| CN106206517B (en) | 2019-11-08 |
| JP2016225484A (en) | 2016-12-28 |
| TW201644033A (en) | 2016-12-16 |
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