CN106206251A - Semiconductor device and the manufacture method of semiconductor device - Google Patents
Semiconductor device and the manufacture method of semiconductor device Download PDFInfo
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- CN106206251A CN106206251A CN201610304722.5A CN201610304722A CN106206251A CN 106206251 A CN106206251 A CN 106206251A CN 201610304722 A CN201610304722 A CN 201610304722A CN 106206251 A CN106206251 A CN 106206251A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 243
- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000005520 cutting process Methods 0.000 claims abstract description 31
- 238000000280 densification Methods 0.000 claims abstract description 20
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 239000011347 resin Substances 0.000 claims abstract description 19
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 101100008046 Caenorhabditis elegans cut-2 gene Proteins 0.000 abstract description 24
- 230000006835 compression Effects 0.000 abstract description 17
- 238000007906 compression Methods 0.000 abstract description 17
- 230000008602 contraction Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 16
- 239000012535 impurity Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 239000004020 conductor Substances 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000227 grinding Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
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- 229920001721 polyimide Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 2
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- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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- 239000002344 surface layer Substances 0.000 description 2
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- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- -1 aluminum-silicon-copper Chemical compound 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
The present invention provides that a kind of reliability is high, thermal diffusivity is good and low-resistance semiconductor device.And provide a kind of and productivity ratio can manufacture the manufacture method of semiconductor device of this semiconductor device well.The groove 3 starting at desired depth d from the front of semiconductor wafer 1 is formed at the line of cut 2 optionally removing the surface protection film 13 being made up of thermosetting resin in the front covering semiconductor wafer 1 and formed.By forming groove 3 at line of cut 2, it can be ensured that be applied to the passing away of the compression stress of the face side of semiconductor wafer 1 due to the thermal contraction of surface protection film 13 that produces when for forming the densification of surface protection film 13.Thus, the compression stress of the face side being applied to semiconductor wafer 1 is alleviated, and therefore easily carries out the thin plate of semiconductor wafer 1 afterwards.Then, after the back side of the semiconductor wafer 1 after thin plate forms backplate, cutting semiconductor chip 1 and make its singualtion.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device and semiconductor device.
Background technology
In order to tackle present energy-saving, carry out for making power-converting device, various industrial machinery
Deng in supply unit use electric power device energy-saving and expand universal low price further.Make
For such electric power device, representational have IGBT (Insulated Gate Bipolar Transistor:
Insulated gate bipolar transistor), MOSFET (Metal Oxide Semiconductor Field Effect
Transistor: insulated-gate type field effect transistor) etc. switch element.It addition, for high pressureization, low
Resistance and the purpose of high efficiency, be set to drift layer to improve impurity concentration by n-type area and p
The MOSFET's of superjunction (SJ:Super Junction) structure of the pn floor arranged side by side that type district is alternately arranged
Goodsization are the most accelerated.It addition, as device generations, just at application carborundum (SiC)
Switch element.
If these switch elements reach more than a certain temperature when switch motion along with heating, then can produce
Raw malfunction is so that being destroyed, it is advantageous to improve thermal diffusivity for making the lower thickness of semiconductor wafer
Switch element.It addition, have electricity along the thickness direction of semiconductor wafer by being set to by these switch elements
The longitudinal type of stream circulation, it is possible to realize low resistance, favorably by making the lower thickness of semiconductor wafer
In high efficiency.Therefore, can enumerate for improve thermal diffusivity, the purpose of low resistance and make semiconductor die
The problem of sheet thin plate.On the other hand, in order to improve the reliability of switch element, thermosetting is preferably used
Resin, such as polyimides are as the material of surface protection film (passivating film).But, in order to form heat
Thermosetting resin film must carry out densification operation, makes thermosetting resin film thermal contraction, meeting exist by densification
The front (interarea) of semiconductor wafer, produces compression stress in the direction parallel with front wafer surface.Therefore,
Afterwards in the case of making semiconductor wafer thin plate, owing to being applied to the compression in the front of semiconductor wafer
Stress and produce front in semiconductor die sector-meeting and become the warpage of concave surface.
In the case of semiconductor wafer creates warpage, when forming backplate half after existing
Conductor wafer cracks, or is partly leading when utilizing cutting etc. that semiconductor wafer is cut into each shaped like chips
Body chip produce cut, crackle and become the problem such as bad.Figure 10 is to represent conventional semiconductor device
The performance plot of the amount of warpage of the semiconductor wafer in manufacture method.Usual way will be utilized as wafer
After the surface protection film 102 that the formation of the final operation of face side is made up of thermosetting resin, make quasiconductor
Amount of warpage t102 of the semiconductor wafer 101 when the thickness t101 of wafer 101 is thinning is shown in Figure 10 (a).
Amount of warpage t102 of semiconductor wafer refers to the convex surface (back of the body of the semiconductor wafer 101 from the state in warpage
Face 101b) the thickest direction of thickness outside convex to wafer end of (lower section) prominent apex 101c
Distance (Figure 10 (b)) till the corner 101d of side, face.Symbol 101a is the quasiconductor of the state of warpage
The concave surface (front) of wafer 101.As shown in Figure 10 (a), the manufacturer of conventional semiconductor device
In method, in the case of making semiconductor wafer 101 be as thin as the thickness t101 of below 200 μm, can confirm that half
Amount of warpage t102 of conductor wafer 101 becomes big relative to the thickness t101 of semiconductor wafer 101, can produce
The problem caused by the warpage of above-mentioned semiconductor wafer 101.
Method as the warpage of suppression semiconductor wafer, it is proposed that following method: increasing with preset width
Thick and remain the peripheral part of semiconductor wafer, only make central part thin to the journey that can obtain predetermined element characteristic
Manufacturing process's (for example, referring to following patent documentation 1～3) is carried out under the state of degree.
It addition, as the method for cutting semiconductor chip, it is proposed that following method: at semiconductor wafer
Before upper formation transistor, utilize photoetching and be etched in the method for line of cut formation groove (under for example, referring to
State patent documentation 4 (the 0011st section)).In following patent documentation 4, by with the width than cutter
The position of the cutter when groove that wide width is formed corrects cutting offsets, and can suppress semiconductor wafer
Cut, crack.
It addition, as the other method of cutting semiconductor chip, it is proposed that following method: at quasiconductor
The front of wafer is formed at the etchant resist of the outs open corresponding with line of cut, the back side to semiconductor wafer
After being ground, etchant resist is carried out isotropic dry etch as mask, form ratio half at line of cut
Conductor element forms the groove (for example, referring to following patent documentation 5 (the 0032nd～0034 section)) of layer depth.
In following patent documentation 5, by making the width width of the width ratio cutter of groove, improve and brought by cutting
Cutting bits expulsion efficiency, thus suppress quality reduce and pollute.
It addition, as the another method of cutting semiconductor chip, it is proposed that following method: by half
Form semiconductor element on conductor wafer, the whole back side of semiconductor wafer is ground, afterwards half
The front of conductor wafer is formed at the etchant resist of the outs open corresponding with line of cut, using etchant resist as covering
Mould is etched, thus line of cut formed groove (for example, referring to following patent documentation 6 (the 0006th～
0007 section)).In following patent documentation 6, form groove by the width with the narrow width than line of cut,
Thus prevent from directly semiconductor wafer being applied with stress when cutting.
Prior art literature
Patent documentation
Patent documentation 1: Japanese Unexamined Patent Publication 2011-165771 publication
Patent documentation 2: Japanese Unexamined Patent Publication 2008-227521 publication
Patent documentation 3: Japanese Unexamined Patent Publication 2007-208074 publication
Patent documentation 4: Japanese Unexamined Patent Publication 10-083976 publication
Patent documentation 5: Japanese Unexamined Patent Publication 2008-103433 publication
Patent documentation 6: Japanese Unexamined Patent Publication 05-218195 publication
Summary of the invention
Technical problem
But, in above-mentioned patent documentation 1～3, due to by thin for the thickness of the central part of semiconductor wafer
Part is as effective chip region, and the part that the peripheral part of semiconductor wafer thickens and remains is not as quasiconductor
Wafer and cut, so effective chip region of semiconductor wafer area reduce.Accordingly, there exist can be from
The problem that the Effective number of chips of a piece of semiconductor wafer cutting tails off.It addition, at above-mentioned patent documentation 4～6
In, forming thermosetting resin film as surface protection film to improve the reliability of semiconductor element
In the case of, following problem can be produced.
Owing to forming oxide-film (SiO2, SiN), polysilicon film, so by formed thermosetting resin film
As surface protection film semiconductor wafer face side produce compression stress with at semiconductor wafer
The stress that front produces is compared greatly.Therefore, formed at semiconductor wafer as described in Patent Document 4
Before component structure in the case of line of cut forms groove, it is difficult to completely remove the thermosetting resin film of groove, by
The contraction of the thermosetting resin film in remaining in groove and be deformed at semiconductor wafer.Such as above-mentioned patent
Document 5,6 like that after making the lower thickness of semiconductor wafer in the case of line of cut forms groove, it is impossible to
Relax the compression stress produced because of thermosetting resin film in the front of semiconductor wafer, can be at semiconductor die
Sheet produces warpage.
The present invention is in order to eliminate above-mentioned the problems of the prior art, it is therefore intended that offer a kind of reliability height,
Thermal diffusivity height and low-resistance semiconductor device.It addition, the present invention is in order to eliminate above-mentioned prior art
In problem, it is therefore intended that provide one can productivity ratio manufacture that reliability is high, thermal diffusivity high well,
And the manufacture method of the semiconductor device of low-resistance semiconductor device.
Technical scheme
In order to solve above-mentioned problem, it is achieved the purpose of the present invention, the manufacturer of the semiconductor device of the present invention
Method has following characteristics.First, carry out being formed the element shape of component structure in the face side of semiconductor wafer
Become operation.It follows that carry out after said elements formation process, in the front of above-mentioned semiconductor wafer
Form the protecting film formation process of the surface protection film being made up of thermosetting resin.It follows that carry out selecting
The part removing above-mentioned surface protection film to selecting property and make the front of above-mentioned semiconductor wafer expose is set to cutting
The removal step of the line of cut as joint-cutting during above-mentioned semiconductor wafer.It follows that carry out removing above-mentioned
After going operation, make the densification operation of above-mentioned surface protection film densification.It follows that carry out above-mentioned
The position of the above-mentioned line of cut in the front of semiconductor wafer is formed starts at pre-from the front of above-mentioned semiconductor wafer
The groove formation process of the groove of depthkeeping degree.It follows that carry out after above-mentioned groove formation process, from rear side
Make the thin plate chemical industry sequence of the lower thickness of above-mentioned semiconductor wafer.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned groove formation process, with the thickness of the above-mentioned surface protection film after above-mentioned densification operation
The above-mentioned desired depth of more than 1/2 forms above-mentioned groove.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned groove formation process, form groove with the width of the narrow width than above-mentioned line of cut.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
After above-mentioned thin plate chemical industry sequence, also including backplate formation process, it is at above-mentioned semiconductor wafer
Back of the body surface forming electrode.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
After above-mentioned backplate formation process, also including cutting action, it makes above-mentioned semiconductor wafer monolithic
Change.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned groove formation process, with the thickness of the blade than the cutter for cutting above-mentioned semiconductor wafer
Wide width forms above-mentioned groove.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned groove formation process, form above-mentioned groove by the etching of anisotropy dry type.
It addition, in order to solve above-mentioned problem, it is achieved the purpose of the present invention, the semiconductor device of the present invention
Being characterised by, the end face along the semiconductor substrate of line of cut cutting semiconductor chip possesses: groove, its with
Starting at desired depth from the front of above-mentioned semiconductor wafer and be arranged at line of cut: surface protection film, it covers
The part of the inside, side of the above-mentioned groove of ratio of the face side of above-mentioned semiconductor substrate and by thermosetting resin structure
Become.
It addition, the semiconductor device of the present invention is characterised by, in above-mentioned invention, above-mentioned quasiconductor
Face beyond the above-mentioned groove of the end face of substrate is to utilize cutter and the facet that obtains.
It addition, the semiconductor device of the present invention is characterised by, in above-mentioned invention, it is also equipped with element
Structure, it is arranged at the face side of above-mentioned semiconductor substrate, above-mentioned surface protection film covering said elements knot
Structure.
According to above-mentioned invention, it is possible to changing manufacturing process hardly, and do not add new equipment
In the case of utilize the formation of surface protection film and relax compression that the face side at semiconductor wafer produces should
Power.Thus, in thin plate chemical industry sequence, there is warpage in semiconductor wafer hardly.Therefore, easily carry out
The thin plate of semiconductor wafer.It addition, thin plate laggard at semiconductor wafer can stably be carried out
The formation of the backplate of row, make the operation such as cutting of semiconductor wafer singualtion.Thereby, it is possible to reduce
Chip is bad.It addition, according to above-mentioned invention, due to not as in the past by outside semiconductor wafer
Perimembranous thickens with preset width and remains the intensity guaranteeing semiconductor wafer, it is possible to increase quasiconductor
The area of effective chip region of wafer.Thereby, it is possible to what increase can cut out from a piece of semiconductor wafer
Effective number of chips.
Invention effect
Semiconductor device according to the present invention and the manufacture method of semiconductor device, play and can provide reliable
Property high, exothermicity high and the effect of low-resistance semiconductor device.It addition, according to the half of the present invention
The manufacture method of conductor device, play can productivity ratio manufacture that reliability is high, thermal diffusivity high well and
And the effect of low-resistance semiconductor device.
Accompanying drawing explanation
Fig. 1 is the top view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 2 is the sectional view of the structure of the semiconductor device representing embodiment 1.
Fig. 3 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 4 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 5 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 6 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 7 is the sectional view of the end shape of the semiconductor device representing embodiment 1.
Fig. 8 is the degree of depth performance plot with the relation of the amount of warpage of semiconductor wafer of the groove representing line of cut.
Fig. 9 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 10 is the amount of warpage of the semiconductor wafer in the manufacture method representing conventional semiconductor device
Performance plot.
Symbol description
1: semiconductor wafer
2: line of cut
3,53: groove
10: chip region
11,12: electrode pad
13,41: surface protection film
The facet of the end of 14a, 14b: semiconductor wafer
21: initial wafer
22,26:n type epitaxial layer
23: the n-type area of pn layer side by side
24: the p-type area of pn layer side by side
25: pn layer side by side
27:n type district
28: gate insulating film
29: gate electrode
30:p type base
31:p+Type contact area
32:n+Type source region
33: interlayer dielectric
34: contact hole
35: source electrode
36: backplate
42: etchant resist
43: compression stress
The width of w1: line of cut
The width of w2: groove
The width of the open side of w3: groove
The width of the bottom of w4: groove
The width of w11～w13: semiconductor wafer
Detailed description of the invention
Hereinafter, referring to the drawings preferred to the manufacture method of the semiconductor device of the present invention and semiconductor device
Embodiment is described in detail.In the present description and drawings, for addition of the floor of n or p, district
Territory, refers to that electronics or hole are majority carrier respectively.It addition, be marked on n, p+and-represent respectively
Impurity concentration than unmarked+and-layer or the impurity concentration in region high and low.Should illustrate, following
In the explanation of embodiment and accompanying drawing, identical being constituted the symbol that labelling is identical, the repetitive description thereof will be omitted.
(embodiment 1)
The structural approach of the semiconductor device of embodiment 1 is illustrated.Fig. 1 is to represent embodiment
The top view of the state in the manufacture process of the semiconductor device of 1.Fig. 2 is represent embodiment 1 half
The sectional view of the structure of conductor device.Fig. 3～Fig. 6 is the system of the semiconductor device representing embodiment 1
The sectional view of the state during making.Fig. 1 (a) shows semiconductor wafer 1 is cut into each chip
State before shape.Fig. 1 (b) enlargedly show the part surrounded by the round frame A of Fig. 1 (a).Will
Cross section in the line of cut B-B' of Fig. 1 (a) is shown in Fig. 6.In Fig. 1 (a), Fig. 3～Fig. 6, omit
The diagram of each several part beyond surface protection film 13,41.Fig. 1 (b) illustrate only various electrode pad
11,12 and surface protection film 13.
First, as it is shown in figure 1, partly the leading of such as thickness about 700 μm being made up of silicon (Si)
The face side of body wafer 1 forms facade element structure.Facade element structure refers to be formed at active region
Mos gate (insulated gate being made up of the metal-oxide film-quasiconductor) knot of such as longitudinal type MOSFET
Unit cell structure (functional unit of element) such as structure (not shown) and/or be formed at terminal structure field
The pressure-resistance structure (not shown) such as protection ring.The region of current flowing is had when active region is conducting state.
Terminal structure region is arranged to surround around active region, and relax chip front side side electric field and
Keep pressure region.Facade element structure is respectively formed in chip region 10, described chip region 10 be
Semiconductor wafer 1 is configured with multiple.
Chip region 10 becomes semiconductor wafer (quasiconductor when being and semiconductor wafer 1 is cut into each shaped like chips
Substrate) region, surround about with line of cut 2.Specifically, line of cut 2 is at semiconductor wafer
The front of 1 is configured to cancellate plane figure, and chip region 10 is configured to line of cut 2 encirclement
Rectangular plane figure.Line of cut 2 be the front of semiconductor wafer 1 be formed without surface described later
The exposed portion of protecting film 13, joint-cutting when being that semiconductor wafer 1 is cut into single shaped like chips.Make
For being formed at an example of the component structure of chip region 10, the super node MOSFET of n-channel type is shown
In Fig. 2.In the case of the super node MOSFET shown in Fig. 2 is formed at chip region 10, such as, prepare
As n+The initial wafer 21 of type drop ply.
Initial wafer 21 can be such as with 1 × 1019/cm3The most miscellaneous example of arsenic (As) of input dosage
Silicon (Si) wafer such as the thickness about 725 μm.It follows that such as utilize each stacking N-shaped extension
Only selectively ion implanting n-type impurity or be selectively ion-implanted n-type impurity and N-shaped during layer
The multilayer epitaxial mode of impurity, is formed n-type area 23 and p-type area 24 edge in the front of initial wafer 21
The direction parallel with front wafer surface is alternately repeated the pn layer 25 arranged side by side of configuration.Now, the most permissible
The N-shaped epitaxial layer 22,26 of the orlop being layered in initial wafer 21 and the superiors is not carried out ion
Inject.Utilize operation hereto, be produced in initial wafer 21 and be sequentially laminated with undermost N-shaped
The semiconductor wafer 1 of the N-shaped epitaxial layer 26 of epitaxial layer 22, pn layer 25 arranged side by side and the superiors.
It follows that such as form the mos gate structure etc. of plane grid-type in the face side of semiconductor wafer 1
Unit cell structure, the pressure-resistance structure such as protection ring.Specifically, by semiconductor wafer 1 just
Face forms the screen oxide film (not shown) of the thickness of 50nm, across screen oxide film at semiconductor wafer
The front of 1 carries out the ion implanting of the p-type impurity such as such as phosphorus (P), thus at N-shaped epitaxial layer 26
Surface layer forms n-type area 27.The impurity concentration in N-shaped field 27 can be p-type base 30 described later
The 10 of impurity concentration-1Times, it is also possible to be n-type area 23 impurity concentration 102Times.
It follows that after eliminating screen oxide film, form the thickness of 100nm on the surface of n-type area 27
The gate insulating film 28 of degree.It follows that pile up (formation) with the thickness of 500nm on gate insulating film 28
It is made to pattern as the polysilicon layer of gate electrode 29.It follows that using gate electrode 29 as mask example
As after the ion implanting of the n-type impurity such as boron (B), such as, (moved back by the heat treatment of the temperature of 1150 DEG C
Fire) make impurity spread, with arrive the degree of depth in p-type field 24 n-type area 27 surface layer optionally
Form p-type base 30.At this point it is possible to together with p-type base 30, formed in terminal structure region and protect
The pressure-resistance structures such as retaining ring.It follows that by photoetching and ion implanting are repeated, utilize heat treatment to make miscellaneous
Matter spreads, thus respectively selectively forms p in the inside of p-type base 30+Type contact area 31 and n+Type
Source region 32.
It follows that clean semiconductor wafer 1.Then, such as utilize chemical vapor-phase growing (CVD:
Chemical Vapor Deposition) method, in the way of covering grid electrode 29 at semiconductor wafer 1 just
Face forms the interlayer dielectrics such as such as BPSG (Boro Phospho Silicate Glass: boron-phosphorosilicate glass)
33.It follows that by utilizing photoetching and etching to be formed at interlayer dielectric 33 in through the connecing of depth direction
Contact hole 34, makes p+Type contact area 31 and n+Type source region 32 is exposed.It follows that utilize sputtering, with embedment
The mode of contact hole 34 is formed such as by aluminum-silicon-copper (Al-Si-Cu) alloy structure on interlayer dielectric 33
The source electrode 35 become and electrode pad (not shown) etc..
It follows that carry out the temperature for make source electrode 35 and electrode pad low resistance such as 400 DEG C
Heat treatment.This source electrode 35 is equivalent to the such as electrode pad (source electrode pad) 11 of Fig. 1 (b),
Here the electrode pad formed is equivalent to the such as electrode pad 12 of Fig. 1 (b).Source electrode 35 and electrode
Pad can be formed respectively.It follows that form surface protection film (passivation in the whole front of semiconductor wafer
Film) 13, utilize surface protection film 13 to cover facade element structure.As the material of surface protection film 13,
Use the thermosetting resins such as polyimides (PI), polybenzoxazole (PBO).It follows that by selecting
Property ground remove surface protection film 13, thus while making various electrode pad 11,12 expose, with bag
The mode enclosing chip region 10 forms line of cut 2 (Fig. 1 (b)).
The reason forming line of cut 2 is when semiconductor wafer 1 is cut into each shaped like chips, surface protection
Film 13 can become cutting bits and produce granule.Surface protection film 13 can extend substantially to the weldering of various electrode
On the end of dish 11,12.Fig. 1 (b) shows and prolongs on the end of various electrode pads 11,12
Stretch the state having surface protection film 13.The material of surface protection film 13 can be photosensitive with right and wrong, it is possible to
Being photosensitive.In the case of the material making surface protection film 13 is non-photosensitive, utilize photoetching and
Etching selectivity ground removes surface protection film 13.On the other hand, at the material by surface protection film 13
Material be set to photosensitive in the case of, can optionally remove surface protection film as described later merely with photoetching
13。
As it is shown on figure 3, formed by photonasty and heat cured resin in the whole front of semiconductor wafer 1
The surface protection film 41 constituted.The thickness t1 of the surface protection film 41 before densification can be such as
About 16 μm.It follows that as shown in Figure 4, surface protection film 41 is formed etchant resist 42, utilizes
Exposed and developed etchant resist 42 is made to pattern.Now, together with etchant resist 42, with etchant resist 42 phase
Same pattern makes surface protection film 41 pattern.Thus, various electrode pad 11,12 is made to expose, and
And, make the front of semiconductor wafer 1 expose in surrounding the clathrate being configured to rectangular chip region 10.
Make the front of this semiconductor wafer 1 be the part exposed of clathrate be line of cut 2.Owing to can cutting
The shaking volume of cutter regards deviation value as, so the width w1 of line of cut 2 can thick than the blade of cutter
Degree width, such as, can be about 80 μm.By making the width w1 of line of cut 2 blade than cutter
Thickness width, it is possible to suppression cuts to chip region 10, the situation of surface protection film 13 by cutter,
Chip can be reduced bad.
It follows that as it is shown in figure 5, after eliminating etchant resist 42, such as pass through about 400 DEG C
At a temperature of heat treatment (roasting) make surface protection film 41 densification.This heat treatment such as can be by whole
Semiconductor wafer 1 keeps 75 minutes in such as remaining the constant temperature oven of temperature of about 380 DEG C.Pass through
This heat treatment makes surface protection film 41 thermal contraction, and the thickness t2 of the surface protection film 13 after densification is such as
Become about 10 μm.It addition, by making surface protection film 41 thermal contraction, thus at semiconductor wafer 1
Face side, near the end of the surface protection film 13 after densification (i.e. chip region 10 with cut
Near the border of secant 2) on the direction of side, chip region 10, produce compression stress 43.Now, half
Conductor wafer 1 by thin plate, is not thick state, and therefore semiconductor wafer 1 does not almost produce warpage,
But the compression stress 43 being applied to the face side of semiconductor wafer 1 concentrates on the end of surface protection film 13
Near.
Therefore, as shown in Figure 6, photoetching and etching are utilized, in the position of the line of cut 2 of semiconductor wafer 1
Put formation groove 3.By forming groove 3 at line of cut 2, it can be ensured that the face side at semiconductor wafer 1 is produced
The passing away of raw compression stress 43, thus relax the compression of the face side being applied to semiconductor wafer 1
Stress 43.The width w2 of groove 3 can be below the width w1 (w1 >=w2) of line of cut 2.Preferably,
The width w2 of groove 3 can narrower than the width w1 of line of cut 2 (w1 ＞ w2), can be such as 50 μm
Left and right.Owing to there is no exposed chip district 10 at the inwall of groove 3, it is possible to be avoided by cutter cutting
Situation to chip region 10.Although it addition, the width w2 of groove 3 can be than the thickness of the blade of cutter
Narrow, but cutter are due to cutting-up etc. in groove 3, it may occur however that and the life-span of cutter is short, or at quasiconductor
The generation crack, end of wafer, cut.It is therefore preferable that the width w2 of groove 3 is than the blade of cutter
Thickness width.
Degree of depth d of groove 3 can be the face side of semiconductor wafer 1 compression stress 43 concentrate the degree of depth with
On.Specifically, the thickness t2 of the surface protection film 13 after degree of depth d of groove 3 can be densification
About more than 1/2 (d >=1/2 × t2).More making degree of depth d of groove 3 is the surface protection film 13 after densification
Thickness t2 more than 1/2 the degree of depth, more can reduce when making the lower thickness of semiconductor wafer 1 produce
It is born in the warpage of semiconductor wafer 1.It addition, for example, it is preferable to comprise carbon tetrafluoride (CF by employing4)
With hydrogen (H2) the anisotropy dry type etching of atmosphere etc. groove 3 is formed as cross section is substantially rectangular shape
Shape.Its reason is dimensional accuracy can to form groove 3 well.It follows that remove for forming groove 3
The photoresistive mask etched and the polymer generated when etching.Therefore, it is possible to described later from the back side
Side grinding semiconductor chip 1 relaxes the compression stress produced because of the densification of surface protection film 13 before,
Manufacturing process after not carrying out when being applied with compression stress.Thus, carrying out from rear side
In the thin plate chemical industry journey of grinding semiconductor chip 1, semiconductor wafer 1 is nearly free from warpage.Therefore,
Easily carry out the thin plate of semiconductor wafer 1.It addition, can stably carry out at semiconductor wafer 1
The operations such as the formation of the backplate carried out after thin plate, the cutting making semiconductor wafer 1 singualtion,
Chip can be reduced bad.
It follows that from rear side grinding semiconductor chip 1, be ground to the goods as semiconductor device thick
The position of degree (about such as 180 μm).The pressure of the face side to semiconductor wafer 1 applied as described above
Stress under compression 43 is relaxed by the groove 3 that formed at line of cut 2.Therefore, semiconductor wafer 1 is almost
Do not produce warpage, it is possible to make the lower thickness of semiconductor wafer 1.It follows that at semiconductor wafer 1
The back side after grinding forms the backplate 36 as drain electrode.Afterwards, semiconductor wafer 1 is cut (single
Sheet) it is single shaped like chips.That is, by along line of cut 2 cutting semiconductor chip 1, by each chip
District 10 is separated into single semiconductor wafer, thus completes the longitudinal type MOSFET shown in Fig. 2 and (partly lead
Body wafer).Then, by this semiconductor wafer is arranged on the circuit pattern of insulated substrate, draw
Line bonding, connect up and the common assembling procedure such as sealing, thus complete semiconductor device.
It follows that the end shape of semiconductor wafer (i.e. the state of goods) is illustrated.Fig. 7 is
Represent the sectional view of the end shape of the semiconductor device of embodiment 1.In Fig. 7, eliminate element knot
The diagram of each several part beyond the surface protection film 13 of structure.It addition, though it is shown that from Fig. 1's in Fig. 7
One of cross section in the line of cut B-B' of the semiconductor wafer (semiconductor substrate) of semiconductor wafer 1 cutting
Individual end, but the surrounding of substantially rectangular semiconductor wafer (i.e. four limits) all almost identical shapes
State.Specifically, it is set as the blade than cutter as described above by by the width w1 of line of cut 2
Thickness width, thus be formed without table in the end of semiconductor wafer surrounding to remain in the way of chip region 10
The line of cut 2 of surface protective film 13.But, the side (end face) of semiconductor chip is according to being formed at cutting
The width w2 of the groove 3 of line 2 and different.
As shown in Fig. 7 (a), in the case of the width w2 of groove 3 is wider than the thickness of the blade of cutter,
Groove 3 is cut cutter and disconnects.Therefore, the side at semiconductor wafer remains with in chip front side side by such as
The groove 3 of L-shaped is formed on sidewall and bottom.The chip back side of the side of semiconductor wafer is from groove 3
Bottom utilizes, to chip back, the facet 14a that cutter obtain.That is, by the front at semiconductor wafer
Side remains groove 3, thus the width w11 of the face side of semiconductor chip is narrower than the width w12 of rear side.
On the other hand, as shown in Fig. 7 (b), narrower than the thickness of the blade of cutter at the width w2 of groove 3
In the case of, groove 3 is cut cutter cutting.Therefore, the side of semiconductor wafer is from chip front side to the back side
The facet 14b utilizing cutter and obtain.That is, the width w13 of semiconductor wafer is from face side to the back of the body
Side, face is the same.Width w11～w13 of semiconductor wafer is to have partly leading of substantially rectangular flat shape
The length on one side of body wafer.
It follows that degree of depth d of groove 3 is verified with the relation of the amount of warpage of semiconductor wafer 1.Figure
8 is the degree of depth performance plot with the relation of the amount of warpage of semiconductor wafer of the groove representing line of cut.Fig. 8 (a)
Degree of depth d that transverse axis is the groove 3 being formed at line of cut 2, the longitudinal axis is amount of warpage t12 of semiconductor wafer.
Amount of warpage t12 of semiconductor wafer refers to the convex surface (back side 1b) of the semiconductor wafer 1 of the state in warpage
The thickest direction of thickness outside (lower section) prominent from apex 1c to the angle of the convex side of wafer end
The distance (Fig. 8 (b)) of portion 1d.Symbol 1a be the concave surface of the semiconductor wafer 1 of the state of warpage (just
Face).In Fig. 8 (b), eliminate the diagram of the groove 3 formed at line of cut 2.
First, according to the manufacture method of the semiconductor device of above-mentioned embodiment 1, be ready for from
Face side forms the operation of facade element structure to the operation of the lower thickness making semiconductor wafer 1
Multiple samples (semiconductor wafer 1).Degree of depth d of the groove being formed at line of cut 2 of each sample is different,
Condition beyond degree of depth d of grooving 3 is foregoing illustrative each condition.That is, the surface before densification is protected
The thickness t1 of cuticula 41 is set to 16 μm.The thickness t2 of the surface protection film 13 after densification is set to
10μm.The thickness t1 after the thin plate of semiconductor wafer 1 is made to be thinned to 180 μm.Then, these are measured
The amount of warpage of each sample.The results are shown in Fig. 8 (a).
Can confirm that according to the result shown in Fig. 8 (a), degree of depth d of groove 3 is relative to the surface after densification
When the thickness t2 of protecting film 13 is about 1/2 (=5 μm), the amount of warpage of semiconductor wafer 1 with partly lead
The thickness t1 of body wafer 1 be the amount of warpage (≈ 200 μm) during 200 μm be same degree.Additionally can be true
Recognize, by increasing degree of depth d of groove 3 further, it is possible to reduce the amount of warpage of semiconductor wafer 1 further.
As it has been described above, according to embodiment 1, even if using thermosetting resin as surface protection film
In the case of material, by removing the surface protection film on line of cut before making surface protection film densification,
Manufacturing process can changed hardly, and pass through surface protection film in the case of not adding new equipment
Formation relax semiconductor wafer face side produce compression stress.Thus, partly lead making afterwards
During the lower thickness of body wafer, semiconductor wafer is nearly free from warpage.Therefore, quasiconductor is easily carried out
The thin plate of wafer, it is possible to easily carry out the exothermicity raising of semiconductor wafer, the low electricity of semiconductor element
Resistanceization.By improving the thermal diffusivity of semiconductor wafer, such as produce when can be released in switch motion efficiently
Raw heat, improves the stability of element movement.By realizing the low resistance of semiconductor element, it is possible to
Reduce energy loss.
It addition, according to embodiment 1, even if use thermosetting resin is as the material of surface protection film,
It also is able to improve the reliability of semiconductor element.It addition, according to embodiment 1, even if making semiconductor die
The lower thickness of sheet, semiconductor wafer is also nearly free from warpage, and it is possible to stably to carry out is laggard
The formation of the backplate of row, make the operation such as cutting of semiconductor wafer singualtion.Thereby, it is possible to reduce
Chip is bad.It addition, according to embodiment 1, due to not as in the past by outside semiconductor wafer
Perimembranous thickens residual for preset width to guarantee the intensity of semiconductor wafer, it is possible to increase semiconductor die
The area of effective chip region of sheet.Thereby, it is possible to increase from having that a piece of semiconductor wafer can cut out
Effect chip-count, it is possible to reduce manufacturing cost.
(embodiment 2)
It follows that the manufacture method of the semiconductor device of embodiment 2 is illustrated.Fig. 9 is to represent
The sectional view of the state in the manufacture process of the semiconductor device of embodiment 2.Partly leading of embodiment 2
The section shape of the groove 53 in line of cut 2 formation of body device is with the semiconductor device of embodiment 1 not
With.Specifically, as it is shown in figure 9, the section shape of groove 53 can be width from open side towards bottom
The taper (trapezoidal) (w3 ＞ w4) become narrow gradually.Preferably make opening of groove 53 in the same manner as embodiment 1
Below the width w1 that width w3 is line of cut 2 (w1 >=w3) of mouth side.It addition, the opening of groove 53
The width w3 (the preferably width w4 of the bottom of groove 53) of side although can be than the thickness of the blade of cutter
Narrow, but preferably than the thickness width of blade of cutter (not shown).Its reason is identical with embodiment 1.
Although the width w4 of the bottom of groove 53 can be narrower than the thickness of the blade of cutter, but preferably than cutter
The thickness width of blade.Its reason is identical with embodiment 1.
As it has been described above, according to embodiment 2, it is possible to obtain the effect identical with embodiment 1.
Above, the present invention is not limited to above-mentioned embodiment, in the scope of the purport without departing from the present invention
In can carry out various change.Such as, in above-mentioned each embodiment, although illustrate use
Thermosetting resin is as the situation of the material of surface protection film, but the present invention is shunk by solidification in use
Material also can apply as in the case of the material of surface protection film, and play identical effect.It addition,
In the above-described embodiment, by making the thickness of semiconductor wafer from rear side grinding semiconductor chip
Thinning, but be not limited to this, such as can also by the rear side of semiconductor wafer is etched, or
Supporting substrates is fitted other semiconductor wafer, or separate after stacking epitaxial layer on supporting substrates
Hold substrate and make the lower thickness of semiconductor wafer.
It addition, in the above-described embodiment, although illustrate super node MOSFET, but do not limit
In this, the surface protection film such as common MOSFET, IGBT can be applied to cover semiconductor wafer
Whole component structures in front.It addition, the present invention is not limited to silicon substrate, such as, can apply by carbonization
The semiconductor substrate that the various semi-conducting materials such as silicon (SiC) substrate are constituted.It addition, in above-mentioned each enforcement
In mode, the size in the most each portion, impurity concentration, the rule as requested such as treatment conditions of manufacturing process
Lattice etc. carry out various setting.It addition, in each embodiment, make conductivity type (N-shaped, p-type) exchange also same
Sample is set up.
Industrial applicability
Above, the electric power such as inverter are become by the semiconductor device of the present invention and the manufacture method of semiconductor device
The semiconductor device used in the supply unit of changing device, various industrial machines etc. etc. is useful.
Claims (10)
1. the manufacture method of a semiconductor device, it is characterised in that including:
Element formation process, the face side at semiconductor wafer forms component structure；
Protecting film formation process, after described element formation process, in the front of described semiconductor wafer
Form the surface protection film being made up of thermosetting resin；
Removal step, makes the front of described semiconductor wafer by optionally removing described surface protection film
The part exposed is set to line of cut, and this line of cut becomes joint-cutting when cutting described semiconductor wafer；
Densification operation, makes described surface protection film densification after described removal step；
Groove formation process, the position of the described line of cut in the front of described semiconductor wafer is formed from described
The groove of desired depth is started in the front of semiconductor wafer；And
Thin plate chemical industry sequence, after described groove formation process, from the rear side thickness to described semiconductor wafer
Degree carries out thin plate process.
The manufacture method of semiconductor device the most according to claim 1, it is characterised in that
In described groove formation process, the thickness of the described surface protection film after described densification operation
More than 1/2 described desired depth form described groove.
The manufacture method of semiconductor device the most according to claim 1 and 2, it is characterised in that
In described groove formation process, form described groove with the width than the narrow width of described line of cut.
The manufacture method of semiconductor device the most according to claim 1 and 2, it is characterised in that
After described thin plate chemical industry sequence, it is additionally included in the back of the body of the back of the body surface forming electrode of described semiconductor wafer
Face electrode forming process.
The manufacture method of semiconductor device the most according to claim 4, it is characterised in that
After described backplate formation process, also include the cutting making described semiconductor wafer singualtion
Operation.
The manufacture method of semiconductor device the most according to claim 1 and 2, it is characterised in that
In described groove formation process, with than cut described semiconductor wafer cutter thickness of knife edge more
Wide width forms described groove.
The manufacture method of semiconductor device the most according to claim 1 and 2, it is characterised in that
In described groove formation process, form described groove by the etching of anisotropy dry type.
8. a semiconductor device, it is characterised in that along partly leading of line of cut cutting semiconductor chip
The end face of structure base board possesses:
Groove, it is started at from the front of described semiconductor wafer and is arranged at line of cut with desired depth；And
Surface protection film, its cover described semiconductor substrate face side ratio described in groove side closer to
Inner side part and be made up of thermosetting resin.
Semiconductor device the most according to claim 8, it is characterised in that
Face beyond the described groove of the end face of described semiconductor substrate is to be cut the cutting obtained by cutter
Face.
Semiconductor device the most according to claim 8 or claim 9, it is characterised in that be also equipped with:
Component structure, it is arranged at the face side of described semiconductor substrate,
Described surface protection film covers described component structure.
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| JP2015111772A JP6492980B2 (en) | 2015-06-01 | 2015-06-01 | Semiconductor device manufacturing method |
| JP2015-111772 | 2015-06-01 |
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| CN106206251A true CN106206251A (en) | 2016-12-07 |
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| DE102017102127B4 (en) * | 2017-02-03 | 2023-03-09 | Infineon Technologies Ag | Method of manufacturing semiconductor devices using epitaxy and semiconductor devices with a lateral structure |
| JP7313968B2 (en) * | 2019-08-15 | 2023-07-25 | 株式会社ディスコ | Wafer processing method |
| CN115831736B (en) * | 2023-02-13 | 2023-05-05 | 成都万应微电子有限公司 | Cutting method of semiconductor material product |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332270A (en) * | 2002-05-15 | 2003-11-21 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
| JP2005353856A (en) * | 2004-06-11 | 2005-12-22 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332270A (en) * | 2002-05-15 | 2003-11-21 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
| JP2005353856A (en) * | 2004-06-11 | 2005-12-22 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor device |
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| JP2016225511A (en) | 2016-12-28 |
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