CN106205708A

CN106205708A - Cache device

Info

Publication number: CN106205708A
Application number: CN201510239685.XA
Authority: CN
Inventors: 菅野伸; 菅野伸一
Original assignee: Toshiba Corp
Current assignee: Kioxia Corp
Priority date: 2014-12-29
Filing date: 2015-05-12
Publication date: 2016-12-07
Anticipated expiration: 2035-05-12
Also published as: JP6595654B2; JP6320322B2; JP2018136970A; CN106205708B; JP2016126737A; TW201624288A

Abstract

According to an embodiment, a kind of cache device comprises non-volatile cache (4), writing unit (111), determines unit (112), selection unit (113) and erasing unit (115).Described non-volatile cache (4) comprises multiple erasure unit region.Each in described erasure unit region all comprises multiple write unit area.Said write unit (111) writes data into described non-volatile cache (4).Described determine that unit (112) determines whether the plurality of erasure unit region meets erased conditions.From the plurality of erasure unit regional choice region to be erased when described selection unit (113) meets described erased conditions in the plurality of erasure unit region.The erasing of described erasing unit (115) is written to the described data in described region to be erased.

Description

Cache device

The cross reference of related application

Subject application is based on following application case and the benefit of priority of advocating described application case: within 2014, December carries on the 29th Go out No. 62/097,530 U.S. Provisional Application case of application；The 2015-038997 that on February 27th, 2015 files an application Number Japanese patent application case；And the 14/656th, No. 559 U.S.'s non-provisional application case that on March 12nd, 2015 files an application, The full content of all these application cases is incorporated herein by reference.

Technical field

Embodiment described herein generally relates to a kind of cache device.

Background technology

Solid-state drive (SSD) comprises the nonvolatile semiconductor memories such as such as NAND quick-flash memory.Described NAND quick-flash memory comprises multiple pieces (physical blocks).The plurality of piece comprises the intersection being arranged in wordline with bit line Multiple memory cells.

Summary of the invention

In general, according to an embodiment, a kind of cache device comprises nonvolatile cache storage Device, writing unit, determine unit, select unit and erasing unit.Described non-volatile cache comprises many Individual erasure unit region.Each in described erasure unit region all comprises multiple write unit area.Said write list Unit writes data into described non-volatile cache.Described determine that unit determines the plurality of erasure unit district Whether territory meets erased conditions.From institute when described selection unit meets described erased conditions in the plurality of erasure unit region State multiple erasure unit regional choice region to be erased.Described erasing cell erasure is written to the described of described region to be erased Data.

Accompanying drawing explanation

Fig. 1 is the profile instance showing the information processor comprising cache device according to first embodiment Block diagram；

Fig. 2 is the flow chart of the example of the first cache control showing first embodiment；

Fig. 3 is the flow chart of the example of the second cache control showing first embodiment；

Fig. 4 is the flow chart of the example of the 3rd high speed buffer control showing first embodiment；

Fig. 5 is the flow chart of the example of the 4th cache control showing first embodiment；

Fig. 6 is the block diagram of the profile instance showing the information processing system according to the second embodiment；

Fig. 7 is the flow chart of the example of the process that displaying is performed by information processing system according to the second embodiment；

Fig. 8 is the block diagram of the example of the detailed configuration showing the information processing system according to the 3rd embodiment；And

Fig. 9 is the perspective view of the example showing the storage system according to the 3rd embodiment.

Detailed description of the invention

Hereinafter with reference to graphic, embodiment is described.In the following description, identical reference numerals represents have almost identical merit Energy and the assembly of layout, and when necessary, described assembly will be provided repeated description.

[first embodiment]

The cache device comprising non-volatile cache is described in the present embodiment.

In the present embodiment, in described non-volatile cache, data are wiped on ground, every erasure unit region jointly. Described erasure unit region comprises multiple write unit area and multiple reading unit area.

In the present embodiment, NAND quick-flash memory is used as non-volatile cache and non-volatile to deposit Reservoir.But, each in described non-volatile cache and described nonvolatile memory can be all to remove Memorizer outside NAND quick-flash memory, premise is that described memorizer meets described erasure unit region, said write Above-mentioned relation in the middle of unit area and described reading unit area.

When described non-volatile cache and described nonvolatile memory are NAND quick-flash memory, institute State erasure unit region corresponding to one piece.Said write unit area and described reading unit area are corresponding to one page.

In the present embodiment, for example, another units of such as two blocks can control described erasure unit region, This allows jointly to wipe data.

In the present embodiment, access instruction writes data into storage arrangement and reads both data from storage arrangement.

Fig. 1 is the frame of the profile instance of the information processor that displaying comprises cache device according to the present embodiment Figure.

Information processing system 35 comprises information processor 17 and SSD 5.Information processor 17 can be corresponding to SSD The host apparatus of 5.

Information processor 17 comprises processor 2, memorizer 3 and non-volatile cache 4.SSD 5 can It is contained in information processor 17, or may be connected to information processor 17 to launch via network etc. and receiving number According to.Replace SSD 5, another non-volatile memory devices such as such as hard disk drive (HDD) can be used.

Information processor 17 comprises cache device, and described cache device comprises the most slow Deposit control unit 9, the memorizer 3 of management information 61 to 64 and non-volatile cache 4.But, Cache control unit 9, management information 61 to 64, memorizer 3 and non-can be provided outside information processor 17 All or part of of volatile cache memory 4.

Non-volatile cache 4 comprises block group BG₁To BG₄.Non-volatile cache 4 There is the access speed that the access speed than SSD 5 is high.

Block group (the first group) BG₁Comprise block (the first erasure unit region) B_1,1To B_1,K.Block group BG₁Storage The data (that is, processor 2 data used) accessed by processor 2.

In the present embodiment, as block group BG₁When meeting erased conditions (the first erased conditions), based on first in first out (FIFO) And from block group BG₁In block B_1,1To B_1,KSelect cleaning block (to be discarded or injection block) (the first region to be erased).

For example, as block group BG₁Block B_1,1To B_1,KIn the data volume of each when exceeding predetermined value, Meet erased conditions.For example, when being written to block group BG₁Block B_1,1To B_1,KIn the number of pages of each When mesh exceedes predetermined number, erased conditions can be met.

When being written to based on FIFO selected from block B_1,1To B_1,KThe data of cleaning block be in the first low use state Time (for example, reach less than set first number or to be accessed less than set first frequency when described data are accessed Time), described data are written to block group BG₂.By contrast, when being written to selected from block B_1,1To B_1,KWait wipe When being in the first high use state except the data of block (for example, when described data be accessed reach first number more or with First frequency or when being accessed more greatly), described data are written to block group BG₃.It is written to selected from block B_1,1To B_1,K The data of cleaning block be that every piece of ground is wiped free of (that is, abandon or release).

Block group (the second group) BG₂Comprise block (the second erasure unit region) B_2,1To B_2,L.Block group BG₂Storage It is written to selected from block group BG₁Cleaning block data in the data being in the first low use state.

In the present embodiment, as block group BG₂When meeting erased conditions (the 3rd erased conditions), based on FIFO from block Group BG₂In block B_2,1To B_2,LSelect cleaning block (the 3rd region to be erased).

When being written to according to FIFO selected from block B_2,1To B_2,LThe data of cleaning block be in the 3rd low use state Time (for example, reach less than set third time number or to be accessed less than set 3rd frequency when described data are accessed Time), wipe described data.By contrast, when being written to selected from block B_2,1To B_2,LThe data of cleaning block be in Three-hypers (for example, reaches third time number or more or with the 3rd frequency or bigger quilt when described data are accessed when using state During access), described data are written to block group BG₃.Subsequently, it is written to selected from block B_2,1To B_2,LTo be erased The data of block are by every piece of ground erasing.

Block group (the 3rd group) BG₃Comprise block (the 3rd erasure unit region) B_3,1To B_3,M.Block group BG₃Storage It is written to selected from block group BG₁Cleaning block data in the data being in the first low use state.Block group BG₃ Also storage is written to selected from block group BG₂Cleaning block data in be in three-hypers use state data.

In the present embodiment, as block group BG₃When meeting erased conditions (the second erased conditions), based on FIFO from block Group BG₃In block B_3,1To B_3,MSelect cleaning block (the second region to be erased).

When being written to according to FIFO selected from block B_3,1To B_3,MThe data of cleaning block be in the second low use state Time (for example, reach less than set second number or to be accessed less than set second frequency when described data are accessed Time), described data are written to block group BG₄.By contrast, when being written to selected from block B_3,1To B_3,MWait wipe When being in the second high use state except the data of block (for example, when described data be accessed reach second number more or with Second frequency or when being accessed more greatly), again described data are written to block group BG₃In another block.Subsequently, write Enter to selected from block B_3,1To B_3,MCleaning block data by every piece ground erasing.

Block group (the 4th group) BG₄Comprise block (the 4th erasure unit region) B_4,1To B_4,N, block group BG₄Storage It is written to selected from block group BG₃Cleaning block data in the data being in the second low use state.

In the present embodiment, as block group BG₄When meeting erased conditions (the 4th erased conditions), based on FIFO from block Group BG₄In block B_4,1To B_4,NSelect cleaning block (the 4th region to be erased).

Erasing is written to according to FIFO selected from block B_4,1To B_4,NThe data of cleaning block.

In the present embodiment, FIFO is with acting on from block group BG₁To BG₄In each select cleaning block side Method.By selecting cleaning block according to FIFO, at block group BG₁To BG₄In each in from having with the oldest The BOB(beginning of block) of write time and write order performs erasing sequentially.But, for example, can be randomly or based on recently Minimum use (LRU) or the most commonly used (LFU) select cleaning block.For example, management information 61 to 64 bag Whether identification information containing data, instruction data are information and the use status information of data of data to be deleted.Can be based on Management information 61 to 64 and select there is the block of maximum invalid data amount or there is the block of the invalid data amount more than scheduled volume As cleaning block.For example, can select to have maximum invalid data and to be deleted based on management information 61 to 64 Block that data (delete target data) are measured or there is the block more than the invalid data of scheduled volume and data volume to be deleted as waiting to wipe Except block.

Memorizer 3 stores various types of control data, such as, manage information (list) 61 to 64 and information of address conversion 7.Memorizer 3 can be that such as dynamic random access memory (DRAM) or static RAM (SRAM) etc. are easy The property lost memorizer, or can be nonvolatile memory.Memorizer 3 may be included in non-volatile cache 4 In.

In the present embodiment, cache control unit 9 can be based on management information 61 to 64 and information of address conversion 7 Identification information (logical address (for example, the logical block for example, provided from main frame of the cached data of identification Addressing)), position that described data are written to and the use state of described data.For example, cache controls single Unit 9 can select based on management information 61 to 64 and information of address conversion 7 to cache to block group BG₁To BG₄ In each data and according to FIFO erasing block.

Management information 61 to 64 is written to block group BG respectively₁To BG₄The metadata of data.For example, Management information 61 to 64 comprises instruction processor 2 and corresponding data uses the information of state.For example, management letter Whether identification information, instruction data that breath 61 to 64 comprises corresponding data are the deletion information of data to be deleted, indicated number According to being whether the invalidating information of valid data and in order to determine whether to meet the high speed of the erased conditions for wiping block Caching determines information.

Described deletion information is the information that the delete command to data is issued in instruction.More particularly, described deletion information is Instruction receives the information etc. of the delete command to data from the application program performed by processor 2 or operating system (OS). In the present embodiment, for example, described deletion information comprises the identification information making each piece and is written to each piece with instruction The relevant information of the logical address of data to be deleted.

Described invalidating information refer to example as when identical data being written to multiple position latest data be significant figure According to and data in addition to latest data be the information of invalid data.In other words, such as, perform to be written to non-easily In the case of the renewal of the data of the property lost cache memory 4, valid data are to be updated over data.For example, exist Performing in the case of renewal, invalid data is the data not being updated over.In the present embodiment, for example, described effectively / invalid information comprises the identification information making each piece and is written to the valid data of each piece or the logic of invalid data with instruction The information that address is relevant.

Described cache determine information be such as comprise at least one in the write information of every data and reading information or The information etc. of at least one in the write information of every piece and reading information.

For example, write information comprises at least one in write time, write number of times, write frequency and write order.

For example, reading information comprises reading time, reading times, reading frequency and reads at least one in order.

For example, information of address conversion 7 makes the logical address of data corresponding with non-volatile cache 4 Physical address in described logical address is relevant (for example, physical block addressing).For example, information of address conversion 7 Manage with sheet form.

Processor 2 is stored in the memorizer of processor 2, memorizer 3, non-volatile cache by execution Program in 4 or SSD 5 and serve as address conversioning unit 8 and cache control unit 9.

In the present embodiment, for example, in order to cause processor 2 to serve as address conversioning unit 8 and cache control The program of unit 9 can be OS, middleware or firmware.In the present embodiment, address conversion can be implemented by hardware single All or part of of all or part of or cache control unit 9 of unit 8.

Address conversioning unit 8 produces the logical address making write data and indicates in non-volatile cache 4 The information that the physical address of the position of storage said write data is relevant, and by generation information deposit information of address conversion 7。

When receiving, from processor 2, the logical address reading data, address conversioning unit 8 is based on information of address conversion 7 And logical address is converted to physical address.

Cache control unit 9 is higher than the non-volatile cache of the access speed of SSD 5 for access speed 4 perform cache controls.For example, cache control unit 9 is managed by tracing method or write-back method Data and indicate logical address and the physical address of described data.

In tracing method, data are stored in non-volatile cache 4 and are also stored in SSD 5.

In write-back method, it is stored in the data in non-volatile cache 4 and is stored in SSD 5 the most together In.First described data are stored in non-volatile cache 4, and will delay from non-volatile cache subsequently The data rushing memorizer 4 release are stored in SSD 5.

Cache control unit 9 comprises generation unit 10, control unit 11 to 14 and change unit 15 and 16.

Generation unit 10 produces corresponding to block group BG₁To BG₄Management information 61 to 64 and by management information 61 It is written to memorizer 3 to 64.

Control unit 11 to 14 is respectively block group BG₁To BG₄Control data write and block erasing.

Control unit 11 comprise writing unit 111, determine unit 112, select unit 113, determine unit 114 and wipe Except unit 115.

The data accessed by processor 2 are written to block group BG by writing unit (the first writing unit) 111₁。

Determine that unit (first determines unit) 112 determines block group BG₁Whether meet erased conditions (the first erased conditions).

As block group BG₁When meeting erased conditions, select unit (first selects unit) 113 from block group BG₁Select Cleaning block (the first region to be erased).

Determine that unit (second determines unit) 114 determines each data item being written to cleaning block based on management information 61 Whether each item being in the first high use state or the first low use state and described data is data to be deleted.

When each data item being written to cleaning block can be written to block group BG because of each data item₂To BG₃Or Data to be deleted and when being dropped, erasing unit (the first erasing unit) 115 erasing cleaning blocks.

Control unit 12 comprise writing unit 121, determine unit 122, select unit 123, determine unit 124 and wipe Except unit 125.

It is written to block group BG when determining that unit 114 determines₁The data of cleaning block be in the first low use state and also During non-data to be deleted, described data are written to block group BG by writing unit (the second writing unit) 121₂。

Determine that unit (the 5th determines unit) 122 determines block group BG₂Whether meet erased conditions (the 3rd erased conditions).

As block group BG₂When meeting erased conditions, select unit (the 3rd selects unit) 123 from block group BG₂Select Cleaning block (the 3rd region to be erased).

Determine based on management information 62, unit 124 determines that each data item being written to cleaning block is in three-hypers Whether each item of use state or the 3rd low use state and described data is data to be deleted.

The data being written to cleaning block of state and data the most to be deleted are used to be written to block group when being in three-hypers Group BG₃Time, erasing unit (the second erasing unit) 125 erasings are written to the data of cleaning block.

Control unit 13 comprises writing unit 131, determines unit 132, selects unit 133, determines unit 134, writes Enter unit 135, erasing unit 136 and writing unit 137.

It is written to block group BG when determining that unit 114 determines₁The data of cleaning block be in the first high use state and also During non-data to be deleted, described data are written to block group BG by writing unit (the 3rd writing unit) 131₃。

When being written to block group BG₂Data be in three-hypers and use state and during data the most to be deleted, writing unit Described data are written to block group BG by (the 6th writing unit) 137₃.For example, when being written to block group BG₂'s Data are when the data accessed by processor 2, and writing unit 137 can be by block group BG₂Data to be accessed be written to Block group BG₃。

Determine that unit (the 3rd determines unit) 132 determines block group BG₃Whether meet erased conditions (the second erased conditions).

As block group BG₃When meeting erased conditions, select unit (second selects unit) 133 from block group BG₃Select Cleaning block (the second region to be erased).

Determine that unit (the 4th determines unit) 134 determines each data item being written to cleaning block based on management information 63 Whether each item being in the second high use state or the second low use state and described data is data to be deleted.

When being written to block group BG₃The data of cleaning block be determined to be in the second high use state and not wait to delete Divisor according to time, described data are written to block group BG by writing unit (the 5th writing unit) 135 again₃In another can Write-in block.

When each item of the data being written to cleaning block can be written to block group BG because of each data item₄, again write Enter to block group BG₃Or data to be deleted and when being dropped, erasing unit (the 3rd erasing unit) 136 erasings are to be erased Block.

Control unit 14 comprises writing unit 141, determines unit 142, selection unit 143 and erasing unit 144.

It is written to block group BG when determining that unit 134 determines₃The data of cleaning block be in the second low use state and also During non-data to be deleted, described data are written to block group BG by writing unit (the 4th writing unit) 141₄。

Determine that unit (the 6th determines unit) 142 determines block group BG₄Whether meet erased conditions (the 4th erased conditions).

As block group BG₄When meeting erased conditions (the 4th erased conditions), select unit (the 4th selects unit) 143 from block Group BG₄Select cleaning block (the 4th region to be erased).

Erasing unit (the 4th erasing unit) 144 erasings are written to block group BG₄The data of cleaning block.

When being written to block group BG₂Data reach three-hypers use state time, change unit (the first change unit) 15 Increase block group BG₁Included in block number and reduce block group BG₃Included in the number of block.Citing comes Say, when being written to block group BG₂Data when being accessed by processor 2, change unit 15 increases block group BG₁Middle institute The number of the block comprised and minimizing block group BG₃Included in the number of block.

When being written to block group BG₄Data when reaching the 4th high use state, change unit (the second change unit) 16 Increase block group BG₃Included in block number and reduce block group BG₁Included in the number of block.Citing comes Say, when being written to block group BG₄Data when being accessed by processor 2, change unit 16 increases block group BG₃Middle institute The number of the block comprised and minimizing block group BG₁Included in the number of block.

Fig. 2 is the flow chart of the example showing the first cache control according to the present embodiment.Fig. 2 exemplarily shows Wherein write data into block group BG₁, write data into block group BG₂Or BG₃And wipe block group BG₁In The process of cleaning block.

In step s 201, processor 2 data accessed are written to block group BG by writing unit 111₁。

In step 202., determine that unit 112 determines block group BG₁Whether meet erased conditions.

As block group BG₁When being unsatisfactory for erased conditions, described process proceeds to step S206.

As block group BG₁When meeting erased conditions, in step S203, select unit 113 from block group BG₁Select Cleaning block.

In step S204, determine that unit 114 determines each data being written to cleaning block based on management information 61 Item is in whether each item of the first high use state or the first low use state and described data is data to be erased (delete target data).

When data item is in the first low use state and data data the most to be deleted (non-delete target data), in step In S301, described data item is written to block group BG by writing unit 121₂。

When data item is in the first high use state and data data the most to be deleted, in step S401, write is single Described data item is written to block group BG by unit 131₃。

When each item of the data being written to cleaning block each item of factor data can be written to block group BG₂Or block group Group BG₃Or data to be deleted and when being dropped, in step S205, erasing unit 115 wipes cleaning block.

In step S206, cache control unit 9 determines whether described for end process.

When cache control unit 9 does not terminates described process, described process returns to step S201.

When cache control unit 9 terminates described process, described process just terminates.

Fig. 3 is the flow chart of the example showing the second cache control according to the present embodiment.Fig. 3 exemplarily shows Wherein write data into block group BG₂And wipe block group BG₂In the process of cleaning block.

When, in step S204, being written to block group BG₁The data of cleaning block be determined to be in the first low use When state and data the most to be deleted, in step S301, described data are written to block group BG by writing unit 121₂。

In step s 302, determine that unit 122 determines block group BG₂Whether meet erased conditions.

As block group BG₂When being unsatisfactory for erased conditions, described process proceeds to step S306.

As block group BG₂When meeting erased conditions, in step S303, select unit 123 from block group BG₂Select Cleaning block.

In step s 304, determine that unit 124 determines each data being written to cleaning block based on management information 62 Item is in three-hypers use state or whether each item of the 3rd low use state and described data is data to be deleted.

When data item is in the 3rd low use state or data to be deleted, described process proceeds to step S305.

When data item is in three-hypers use state and data the most to be deleted, in step S401, writing unit 137 Described data item is written to block group BG₃。

In step S305, erasing unit 125 erasing is written to block group BG₂The data of cleaning block.

In step S306, cache control unit 9 determines whether described for end process.

When cache control unit 9 does not terminates described process, described process returns to step S301.

Fig. 4 is the flow chart of the example showing the 3rd high speed buffer control according to the present embodiment.Fig. 4 exemplarily shows From writing data into block group BG₃To erasing block group BG₃In the process of data.

When, in step S204, being written to block group BG₁The data of cleaning block be determined to be in first and high use When state and data the most to be deleted, in step S401, described data are written to block group BG by writing unit 131₃。 When in step s 304, being written to block group BG₂Data be determined to be in three-hypers use state (for example, Described data are accessed by processor 2) and during data the most to be deleted, writing unit 137 is by block group BG₂Data write Enter to block group BG₃。

In step S402, determine that unit 132 determines block group BG₃Whether meet erased conditions.

As block group BG₃When being unsatisfactory for erased conditions, described process proceeds to step S407.

As block group BG₃When meeting erased conditions, in step S403, select unit 133 from block group BG₃Select Cleaning block.

In step s 404, determine that unit 134 determines each data being written to cleaning block based on management information 63 Item is in whether each item of the second high use state or the second low use state and described data is data to be deleted.

When data item is in the second low use state and data the most to be deleted, in step S501, writing unit 141 Described data are written to block group BG₄。

When data are in the second high use state and data the most to be deleted, in step S405, writing unit 135 Again it is written to block group BG₃The data of cleaning block be written to block group BG₃In another block.

In step S406, when each item of the data being written to cleaning block can be written to block group because of each data item Group BG₄, be again written to block group BG₃Or data to be deleted and when being dropped, erasing unit 136 is wiped and is waited to wipe Except block.

In step S 407, cache control unit 9 determines whether described for end process.

When cache control unit 9 does not terminates described process, described process returns to step S401.

Fig. 5 is the flow chart of the example showing the 4th cache control according to the present embodiment.Fig. 5 exemplarily shows Wherein write data into block group BG₄And wipe block group BG₄In the process of data.

When in step s 404, being written to block group BG₃The data of cleaning block be determined to be in the second low state And during data the most to be deleted, in step S501, described data are written to block group BG by writing unit 141₄。

In step S502, determine that unit 142 determines block group BG₄Whether meet erased conditions.

As block group BG₄When being unsatisfactory for erased conditions, described process proceeds to step S505.

As block group BG₄When meeting erased conditions, in step S503, select unit 143 from block group BG₄Select Cleaning block.

In step S504, erasing unit 144 erasing is written to block group BG₄In the data of cleaning block.

In step S505, cache control unit 9 determines whether described for end process.

When cache control unit 9 does not terminates described process, described process returns to step S501.

Block group BG at the present embodiment₁In, for example, data are first to be written to block B_1,1, next in proper order It is written to block B_1,2, and it is similarly written block B subsequently_1,3To B_1,K.As block group BG₁Included in block B_1,1 To B_1,KData volume when exceeding predetermined amount of data, wherein wipe the block B that first write completes according to FIFO_1,1, And again data are sequentially write erased piece of B_1,1.Complete to block B_1,1Write after, according to FIFO and wipe Except block B_1,2.Subsequently, again data are sequentially write erased piece of B_1,2.Repeat identical control.

At block group BG₁In, determine be written to block group BG based on management information 61₁In the data of cleaning block Whether (such as) is accessed reaches less than first number or to be accessed less than first frequency.When being written to block group BG₁In The data of cleaning block are accessed and reach less than first number or during to be accessed less than first frequency, select block group BG₂ Write destination as data.

By contrast, when being written to block group BG₁In the data of cleaning block be accessed reach first number more or with First frequency or when being accessed more greatly, selects block group BG₃Write destination as data.

When being written to block group BG₁In the data of cleaning block when being data to be deleted, abandon described data.

Block group BG at the present embodiment₂In, from block group BG₁The data being in the first low use state first First sequentially write block B_2,1, next sequentially write block B_2,2, and it is similarly written block B subsequently_2,3To B_2,L。 As block group BG₂Included in block B_2,1To B_2,LData volume when exceeding predetermined amount of data, wipe according to FIFO Except wherein writing the block B first completed_2,1And again data are sequentially write erased piece of B_2,1.Complete to block B_2,1 Write after, according to FIFO and wipe block B_2,2.Subsequently, data are sequentially write erased piece of B_2,2.Repeat Identical control.

At block group BG₂In, determine be written to block group BG based on management information 62₂In the data of cleaning block Whether (such as) is accessed reaches less than third time number or to be accessed less than the 3rd frequency.When being written to block group BG₂In The data of cleaning block are accessed and reach less than third time number or during to be accessed less than the 3rd frequency, wipe described data.

By contrast, when being written to block group BG₂In the data of cleaning block be accessed reach third time number more or with 3rd frequency or when being accessed more greatly, selects block group BG₃Write destination as data.

When being written to block group BG₂In the data of cleaning block when being data to be deleted, abandon described data.

Block group BG at the present embodiment₃In, from block group BG₁The data being in the first high use state, come From block group BG₂The three-hypers that is in use the data of state or from block group BG₃Re-write data by first Sequentially write block B_3,1, next sequentially write block B_3,2, and it is similarly written block B subsequently_3,3To B_3,M。 As block group BG₃Included in block B_3,1To B_3,MData volume when exceeding predetermined amount of data, wipe according to FIFO Except wherein writing the block B first completed_3,1And again data are sequentially write erased piece of B_3,1.Complete to block B_3,1 Write after, according to FIFO and wipe block B_3,2.Subsequently, again data are sequentially write erased piece of B_3,2。 Repeat identical control.

At block group BG₃In, determine be written to block group BG based on management information 63₃In the data of cleaning block Whether (such as) is accessed reaches less than second number or to be accessed less than second frequency.When being written to block group BG₃In The data of cleaning block are accessed and reach less than second number or during to be accessed less than second frequency, select block group BG₄ Write destination as data.

By contrast, when being written to block group BG₃In the data of cleaning block be accessed reach second number more or with Second frequency or when being accessed more greatly, writes data into block group BG again₃。

When being written to block group BG₃In the data of cleaning block when being data to be deleted, abandon described data.

Block group BG at the present embodiment₄In, from block group BG₃The data being in the second low use state first First sequentially write block B_4,1, next sequentially write block B_4,2, and it is similarly written block B subsequently_4,3To B_4,N。 As block group BG₄Included in block B_4,1To B_4,NData volume when exceeding predetermined amount of data, wipe according to FIFO Except wherein writing the block B first completed_4,1And again data are sequentially write erased piece of B_4,1.Complete to block B_4,1 Write after, according to FIFO and wipe block B_4,2.Subsequently, data are sequentially write erased piece of B_4,2.Repeat Identical control.

In the present embodiment, control unit 14 can determine that and is written to block group BG₄The data of cleaning block whether be in 5th high use state.When being written to block group BG₄The data of cleaning block be determined to be in the 5th high use state Time, for being held in non-volatile cache 4 by described data dimension, control unit 13 can be by described number According to being written to block group BG₃Writable purpose plot.In this case, processor 2 can reduce block group BG₁'s Size.

In the present embodiment, based on four Ge Kuai group BG₁To BG₄And manage data.

For example, at block group BG₁Middle management is accessed the first data once (through primary access data) by processor 2.

For example, if block group BG₁In the second data accessed two or more times and based on FIFO by processor 2 And by from block group BG₁Release, then by the second data from block group BG₁Move to block group BG₃。

It should be noted that in the present embodiment, block group BG₁Size more than block group BG₃Size.

For example, as block group BG₁In the 3rd data in the case of not accessed by processor 2 based on FIFO By from block group BG₁During release, by the 3rd data from block group BG₁Move to block group BG₂。

For example, if block group BG₃In the 4th data in the case of not accessed by processor 2 based on FIFO And by from block group BG₃Remove, then by the 4th data from block group BG₃Move to block group BG₄。

For example, at block group BG₂And BG₄In, cacheable metadata rather than cached data.Unit's number According to comprising information associated with the data.In other words, metadata is the high abstraction about data and extra data and quilt It is attached to described data.

In the present embodiment, for example, when the 5th data are stored in block group BG₁Time middle, can push away based on FIFO Chu Kuai group BG₂In the 6th data.

For example, as block group BG₁In the 7th data be accessed and based on FIFO by from block group BG₁Push away When going out, can be by the 7th data from block group BG₁Move to block group BG₃, can be based on FIFO by block group BG₃ In the 8th data from block group BG₃Move to block group BG₄, and can be based on FIFO from block group BG₄Release Block group BG₄In the 9th data.

For example, as access block group BG₂In ten data time, block group BG can be increased₁Size.If Block group BG₁Size increase, then based on FIFO by block group BG₃In the 11st data move to block group Group BG₄。

For example, as block group BG₄In the 12nd data be accessed and based on FIFO by from block group BG₄ During release, the 12nd data are moved to block group BG₃, and block group BG can be reduced₁Size.

In the present embodiment mentioned above, maintain and determine that transmission is write to whether the data maintaining block unit being determined Enter and blocks of data to be maintained is written to purpose plot, and the data being written to non-volatile cache 4 are every Wiped block.

In the present embodiment, effective cache capacity can be increased, the position of non-volatile cache 4 can be promoted Speed, and the speed of information processor 17 can be increased.

In the present embodiment, garbage collection (garbage is not being performed for non-volatile cache 4 Collection), in the case of, the reduction of performance can be avoided.Owing to garbage collection is not necessary, therefore can reduce Writing number of times and the life-span of non-volatile cache 4 can be increased to non-volatile cache 4. Additionally, due to garbage collection is not necessary, therefore it is not necessary to guaranty that setting area (provisioning area). Therefore, the data capacity that can be used as cache memory can be increased, and service efficiency can be improved.

For example, when using the nonvolatile memory border as cache memory and block the most all to abandon During data, may frequently perform garbage collection so that the valid data in the block of nonvolatile memory are moved to another Block.In the present embodiment, it is not necessary in non-volatile cache 4, perform garbage collection.Therefore, As described above, in the present embodiment, the life-span of non-volatile cache 4 can be increased.

[the second embodiment]

The present embodiment is the modified example of first embodiment.In the present embodiment, it is described in and comprises cache and control single Data and information between the information processor 17 and SSD 5 of unit 9 are launched and receive.

In the present embodiment, use logical address as the identification information of data.But, can be identified by out of Memory Data.

Fig. 6 is the block diagram of the profile instance showing the information processing system 35 according to the present embodiment.

In addition to the element described in first embodiment, cache control unit 9 comprises transmitter unit further 18, unit 19, writing unit 20 and transmitter unit 21 are received.

Transmitter unit 18 launches the write data for SSD 5 and the address of said write data to SSD 5.In this reality Execute in example, for example, the address being transmitted into SSD 5 from transmitter unit 18 is logical address.

Receive unit 19 and receive the valid data comprising the block that instruction is written to garbage collection to be subjected from SSD 5 The block message of logical address.

In the present embodiment, described block message can comprise the identification information of each piece made in SSD 5 and be written to each piece The relevant information of the identification information of data.

Writing unit 20 will be wrapped by block message based on the block message received from SSD 5 and management information 61 to 64 All or part of write (transcribing) of the valid data of the logical address instruction contained is to unless outside volatile memory 24 Memorizer.For example, another memorizer can be non-volatile cache 4.

For example, in the case of receiving delete command, instruction is that data to be deleted (are deleted and waited by writing unit 20 The person of choosing) the logical address of instruction valid data included in block message of the logical address of data get rid of.Therefore, optional Select block and the valid data of data the most to be deleted being written to garbage collection to be subjected.Writing unit 20 will be selected Data are written to another memorizer.

Transmitter unit 21 produces the deletion information comprising the logical address indicating data to be deleted and described deletion information is sent out It is mapped to SSD 5.For example, described deletion information can comprise the valid data included in instruction block message logically In location, instruction is the logical address of the data being not written into the delete target that unit 20 is written to another memorizer.Replacement is deleted Except information, the maintenance information of the logical address comprising data to be maintained can be transmitted into SSD 5 from transmitter unit 21.

SSD 5 comprises processor 22, memorizer 23 and nonvolatile memory 24.

For example, memorizer 23 stores various types of control data, such as information of address conversion 32, invalidating Information 33 and deletion information 34.Memorizer 23 can be the volatile memory such as such as DRAM or SRAM, or can For nonvolatile memory.Memorizer 23 may be included in nonvolatile memory 24.

Program that processor 22 is stored in the memorizer in processor 22 by execution, it is stored in memorizer 23 Program or be stored in the program in nonvolatile memory 24 and serve as address conversioning unit 25, writing unit 26, effectively / invalid generation unit 27, selection unit 28, transmitter unit 29, reception unit 30 and garbage collection unit 31.

In the present embodiment, for example, in order to cause processor 22 serve as address conversioning unit 25, writing unit 26, Invalidating generation unit 27, selection unit 28, transmitter unit 29, reception unit 30 and garbage collection unit The program of 31 can be OS, middleware or firmware.In the present embodiment, can by hardware implement address conversioning unit 25, Writing unit 26, invalidating generation unit 27, select unit 28, transmitter unit 29, receive unit 30 and useless All or part of of unit collector unit 31.

When receiving the logical address of write data and said write data from cache control unit 9, address is changed Unit 25 produces the logical address making write data and the storage said write data in instruction nonvolatile memory 24 The information that the physical address of position is relevant, and described information is deposited information of address conversion 32.

In the present embodiment, address conversioning unit 25 is implemented by processor 22.But, address conversioning unit 25 can be with Processor 22 separately configures.

Address conversioning unit 25 changes address based on (such as) sheet form information of address conversion 32.Instead, can pass through Address is changed in key-value retrieval.For example, as keyword and physical address can be used by using logical address Address conversion is implemented by means of key-value retrieval as value.

Write data are written to the position indicated by physical address obtained by address conversioning unit 25 by writing unit 26.

Invalidating generation unit 27 produces instruction be written to nonvolatile memory based on such as information of address conversion 32 Each item of the data of 24 is the invalidating information 33 of valid data or invalid data.Subsequently, invalidating produces Invalidating information 33 is stored in memorizer 23 by unit 27.

Unit 28 is selected to select the block of garbage collection to be subjected.

For example, unit 28 is selected block from nonvolatile memory 24 can to select the block with the oldest write time It is used as the block of garbage collection to be subjected.

For example, unit 28 is selected can to select garbage to be subjected by the block from nonvolatile memory 24 randomly The block collected.

For example, unit 28 is selected can to select based on invalidating information 33 to have maximum invalid data amount or have More than the invalid data amount of scheduled volume as the block of garbage collection to be subjected.

For example, unit 28 is selected can to select have maximum nothing based on invalidating information 33 and deletion information 34 Imitate data and data volume to be deleted or have more than the block of the invalid data of scheduled volume and data volume to be deleted as to be subjected The block of garbage collection.

Transmitter unit 29 is by being defined as the logical address of invalid invalid data from finger by instruction by invalidating information 33 Show that the logical address of the data of the block being written to garbage collection to be subjected is deleted and produced block message.In other words, institute State identification information that block message comprises the block making garbage collection to be subjected and instruction and be written to the valid data of described piece The relevant information of logical address.Described block message is transmitted into cache control unit 9 by transmitter unit 29.

Receive unit 30 receive deletion information from cache control unit 9 and be stored in non-by deletion information 34 In volatile memory 24.

Garbage collection unit 31 is based on invalidating information 33 and is stored in the deletion in nonvolatile memory 24 Information 34 and invalid data and data to be deleted are got rid of from the data of the block being written to garbage collection to be subjected, and The valid data being only data the most to be deleted perform garbage collection.

Fig. 7 is the flow chart of the example of the process that displaying is performed by information processing system according to the present embodiment.

In step s 701, write data and logical address are transmitted into SSD 5 by transmitter unit 18.

In step S702, address conversioning unit 25 receives write data and logical address, and will make patrolling of write data The information collecting address relevant to physical address deposits information of address conversion 32.

In step S703, writing unit 26 by write data be written in nonvolatile memory 24 by described thing The position of reason address instruction.

In step S704, invalidating generation unit 27 produces instruction and is written to each of nonvolatile memory 24 Data item is the invalidating information 33 of valid data or invalid data and invalidating information 33 is stored in storage In device 23.

In step S705, unit 28 is selected to select the block of garbage collection to be subjected.

In step S706, transmitter unit 29 is by being designated as invalid invalid number by instruction by invalidating information 33 According to logical address from instruction be written to garbage collection to be subjected block data logical address delete and produce block Information, and described block message is transmitted into cache control unit 9.

In step S707, receive unit 19 and receive block message from SSD 5.

In step S708, writing unit 20 is based on the block message received from SSD 5 and management information 61 to 64 Be written to by all or part of of data indicated by the logical address included in block message except SSD 5 is non-volatile Memorizer outside memorizer 24.

For example, in the case of receiving delete command, writing unit 20 will indicate data to be deleted logically Location logical address included in block message is got rid of, and the data to be maintained indicated by described logical address is written to separately One memorizer.

In step S709, the deletion information of the logical address comprising data to be deleted is transmitted into SSD by transmitter unit 21 5。

In step S710, receive unit 30 and receive deletion information and by deletion information 34 from cache control unit 9 It is stored in memorizer 23.

In step S711, garbage collection unit 31 based on invalidating information 33 and delete information 34 and by nothing Effect data and Data Data to be deleted are got rid of from the data of the block being written to garbage collection to be subjected, and for not treating The valid data deleting data perform garbage collection.

In the present embodiment as described above, cache control unit 9 can from SSD 5 obtain about be written to non-easily The information of the data of the block of the property lost memorizer 24.Cache control unit 9 can Identification Data be deposited non-volatile whereby Write state in the block of reservoir 24.For example, in the present embodiment, identification nonvolatile memory can be written to The data of the block of 24 are valid data or invalid data and whether can delete described data.

In the present embodiment, SSD 5 comprises to determine the invalidating information that data are valid data or invalid data 33 and in order to determine whether to delete the deletion information 34 of data.Whereby, may be in that SSD 5 performs garbage to receive Determine whether to be written to erasing the data of the block of garbage collection to be subjected during collection.Therefore, nonessential data can be avoided Write and can increase the life-span of nonvolatile memory 24.

In the present embodiment, cache control unit 9 can prevent by patrolling included in the block message that SSD 5 receives Collect the delete target data in the middle of the valid data of address instruction and be transcribed into another memorizer from nonvolatile memory 24. In the present embodiment, SSD 5 can will not be transcribed into the data (citing of another memorizer from cache control unit 9 Say, deletable invalid data or valid data) delete from SSD 5.

In the present embodiment as described above, the block message relevant to cleaning block is transmitted into information processing from SSD 5 Device 17.But, for example, described block message can comprise makes each piece in nonvolatile memory 24 and write To the information that the identification information of the data of each piece is relevant.Information processor 17 can be believed by receiving relation from SSD 5 Breath carrys out the storage relation between block and data in identification SSD 5.

[the 3rd embodiment]

In the present embodiment, explanation comprises at the information explained in first embodiment and the second embodiment in further detail The information processing system 35 of reason system 17 and SSD 5.

Fig. 8 is the block diagram of the example of the detailed construction showing the information processing system 35 according to the present embodiment.

Information processing system 35 comprises information processor 17 and accumulator system 37.

SSD 5 according to first embodiment and the second embodiment is corresponding to accumulator system 37.

The processor 22 of SSD 5 is corresponding to CPU 43B.

Information of address conversion 32 is corresponding to LUT (look-up table) 45.

Memorizer 23 is corresponding to DRAM 47.

Information processor 17 serves as host apparatus.

The controller 36 of accumulator system 37 comprises front end 4F and rear end 4B.

It is (senior that front end (main-machine communication unit) 4F comprises HPI 41, host interface controller 42, coding/decoding unit Encryption standard (AES)) 44 and CPU 43F.

HPI 41 communicate with information processor 17 with exchange request (writing commands, reading order, erasing order), LBA (LBA) and data.

Host interface controller (control unit) 42 control based on CPU 43F and control the communication of HPI 41.

The coding/decoding unit 44 write data (in plain text) to launching from host interface controller 42 in data write operation Encode.The coding/decoding unit 44 warp to launching from the read buffers RB of rear end 4B in data read operation Coding reads decoding data.It should be noted that can be according to interim order in the situation not using coding/decoding unit 44 The lower transmitting performing write data and reading data.

CPU 43F controls the components above 41,42 and 44 of front end 4F, to control the whole function of front end 4F.

Rear end (memory communication unit) 4B comprise write buffer WB, read buffers RB, LUT 45, DDRC 46, DRAM 47, DMAC 48, ECC 49, randomizer RZ, NANDC 50 and CPU 43B.

Write buffer (write data transfer unit) WB temporarily stores the write number launched from information processor 17 According to.Specifically, write buffer WB temporarily stores described data until it reaches to be suitable for nonvolatile memory Till the tentation data size of 24.

Read buffers (reading data transfer unit) RB temporarily stores the reading number read from nonvolatile memory 24 According to.Specifically, read buffers RB by read data and be rearranged into being suitable for information processor 17 order (by The order of logical address LBA that information processor 17 is specified).

LUT 45 is the data in order to logical address LBA to be converted into physical address PBA (physical block addressing).

DDRC 46 controls the Double Data Rate (DDR) in DRAM 47.

DRAM 47 is the nonvolatile memory storing such as LUT 45.

DMA controller (DMAC) 48 transmits write data via internal bus IB and reads data.? In Fig. 8, illustrate the most single DMAC 48；But, controller 36 can comprise two or more DMAC 48. DMAC 48 can be set in the various positions within controller 36.

ECC (error correction unit) 49 adds error-correcting code (ECC) to the write data launched from write buffer WB. When reading data are transmitted into read buffers RB, if necessary, then ECC 49 use added ECC correct from The reading data that nonvolatile memory 24 reads.

In data write operation, randomizer RZ (or Scrambler) spreads write data in such manner so that Said write data are not offset in certain one page or are not offset on the word-line direction of nonvolatile memory 24.Logical Cross and spread write data in this way, write number of times standardization can be made and the memorizer of nonvolatile memory 24 can be extended The cell life of unit MC.Therefore, the reliability of nonvolatile memory 24 can be improved.Additionally, at digital independent In operation, the reading data read from nonvolatile memory 24 can pass through randomizer RZ.

It is parallel that NAND controller (NANDC) 50 uses multiple passages (illustrating four channel C H0 to CH3 in figure) Access nonvolatile memory 24 in ground is to meet the demand to a certain speed.

CPU 43B controls each of the above assembly (45 to 50 and RZ) of rear end 4B, to control the whole function of rear end 4B.

It should be noted that the structure only example of controller 36 and be not intended to be limited by it.

Fig. 9 is the perspective view of the example showing the storage system according to the present embodiment.

Storage system 100 comprises accumulator system 37 and is used as SSD.

For example, accumulator system 37 is the relatively small module that outside size will be about 20mm × 30mm. It should be noted that size and the yardstick of accumulator system 37 are not limited to this and can at random change over all size.

Additionally, accumulator system 37 is applicable to information processor 17, using as in middle institutes such as companies (enterprise) Server in the data center used or cloud computing system.Therefore, accumulator system 37 can be enterprise SSD (eSSD).

For example, accumulator system 37 comprises multiple adapters (for example, slot) 38 of upward opening.Each Adapter 38 is serial attached SCSI (SAS) adapter etc..By SAS connector, can double via 6Gbps Port is set up between information processor 17 and each accumulator system 37 and is in communication with each other at a high speed.It should be noted that adapter 38 can be quick PCI (PCIe) or quick NVM (NVMe).

Multiple accumulator systems 37 are individually attached to the adapter 38 of information processor 17 and are arranged shape with one Formula supports and it is stood in an approximate vertical direction.This structure, multiple accumulator systems 37 is used jointly to be installed Become compact size, and accumulator system 37 miniaturization can be made.Additionally, the shape of each accumulator system 37 of the present embodiment Shape is the little form factor (SFF) of 2.5 inches.Due to this shape, accumulator system 37 can be with enterprise HDD (eHDD) Compatible and can to realize the single system with eHDD compatible.

It should be noted that accumulator system 37 is not limited in enterprise HDD use.For example, accumulator system 37 Can be used as the memory medium of consumer electronics (such as notes type portable computer or tablet PC terminal).

As from above it is understood that there is the information processing system 35 of the structure of the present embodiment and storage system 100 can be at tool Massive store advantage is realized in the case of having the same advantage of the second embodiment.

The structure of the accumulator system 37 according to the present embodiment can be applicable to the information processor 17 according to first embodiment. For example, may correspond to CPU 43B according to the processor 2 of first embodiment.Information of address conversion 7 may correspond to LUT 45.Memorizer 3 is corresponding to DRAM 47.Non-volatile cache 4 may correspond to non-volatile depositing Reservoir 24.

Although having been described for some embodiment, but these embodiments present the most by way of example and are not intended to limit this The scope of invention.It practice, novel embodiment described herein can embody with other form multiple；Additionally, can In the case of without departing substantially from the spirit of the present invention form to embodiment described herein make various omission, replacement and Change.Intend to make appended claims and equivalent thereof contain this type of and will belong to the shape in scope and spirit of the present invention Formula or amendment.

Claims

1. a cache device, it is characterised in that including:

Non-volatile cache, it include the first group comprising multiple first erasure unit region, comprise many Second group in individual second erasure unit region and comprise the 3rd group in multiple 3rd erasure unit region, described first arrives Each in 3rd erasure unit region all comprises multiple write unit area；

First writing unit, it writes data into described first group；

Generation unit, it produces the management information of the use state indicating the described data being written to described first group；

First determines unit, and it determines whether described first group meets the first erased conditions；

First selects unit, and it selects the when described first group meets described first erased conditions from described first group One region to be erased；

Second determines unit, and it determines the described data being written to described first region to be erased based on described management information It is in the first high use state or the first low use state；

Second writing unit, described data are write by it when described data are determined to be in described first low use state To described second group；

3rd writing unit, described data are write by it when described data are determined to be in described first high use state To described 3rd group；And

First erasing unit, its erasing is written to the described data in described first region to be erased.

Cache device the most according to claim 1, it is characterised in that

Described non-volatile cache farther includes to comprise the 4th group in multiple 4th erasure unit region, And

Described cache device farther includes:

3rd determines unit, and it determines whether described 3rd group meets the second erased conditions；

Second selects unit, and it selects the when described 3rd group meets described second erased conditions from described 3rd group Two regions to be erased；

4th determines unit, and it determines the described data being written to described second region to be erased based on described management information It is in the second high use state or the second low use state；

4th writing unit, it is determined to be in described second in the described data being written to described second region to be erased The described data being written to described second region to be erased during low use state are written to described 4th group；

5th writing unit, it is determined to be in described second in the described data being written to described second region to be erased The described data being again written to described second region to be erased during high use state are written to described 3rd group；And

Second erasing unit, its erasing is written to the described data in described second region to be erased.

Cache device the most according to claim 1, it is characterised in that

When the data volume of described first group exceedes scheduled volume, described first determines that unit determines meets described first erasing Condition.

Cache device the most according to claim 1, it is characterised in that

Described first selects unit to select described first region to be erased based on first in first out from described first group.

Cache device the most according to claim 2, it is characterised in that farther include:

First change unit, it reaches to increase institute when three-hypers uses state in the described data being written to described second group State the number in the described first erasure unit region included in the first group and reduce included in described 3rd group The number in described 3rd erasure unit region；And

Second change unit, it increases institute when the described data being written to described 4th group reach the 4th high use state State the described number in the described 3rd erasure unit region included in the 3rd group and reducing in described first group to be wrapped The described number in the described first erasure unit region contained.

Cache device the most according to claim 5, it is characterised in that farther include:

6th writing unit, it will when the described data being written to described second group reach described three-hypers use state The described data being written to described second group are written to described 3rd group.

5th determines unit, and it determines whether described second group meets the 3rd erased conditions；

3rd selects unit, and it selects the when described second group meets described three erased conditions from described second group Three regions to be erased；

3rd erasing unit, its erasing is written to the described data in described 3rd region to be erased；

6th determines unit, and it determines whether described 4th group meets the 4th erased conditions；

4th selects unit, and it selects the when described 4th group meets described four erased conditions from described 4th group Four regions to be erased；And

4th erasing unit, its erasing is written to the described data in described 4th region to be erased.

Cache device the most according to claim 7, it is characterised in that

Described 3rd selects unit the first write time based on the plurality of second erasure unit region or the first write time Sequence and selecting indicates described first write time or described first write order to be old erasure unit region as described the Three regions to be erased, and

Described 4th selects unit the second write time based on the plurality of 4th erasure unit region or the second write time Sequence and selecting indicates described second write time or described second write order to be old erasure unit region as described the Four regions to be erased.

9. a cache device, it is characterised in that including:

Non-volatile cache, it comprises multiple erasure unit region, each in described erasure unit region Person comprises multiple write unit area；

Writing unit, it writes data into described non-volatile cache；

Determining unit, it determines whether the plurality of erasure unit region meets erased conditions；

Select unit, from the plurality of erasure unit district when it meets described erased conditions in the plurality of erasure unit region Territory selects region to be erased；And

Erasing unit, its erasing is written to the described data in described region to be erased.

Cache device the most according to claim 9, it is characterised in that

Described erased conditions is that the data volume in the plurality of erasure unit region exceedes scheduled volume.

11. cache device according to claim 9, it is characterised in that

Described region to be erased is the region of erasure unit size, and

Described erasing cell erasure is written to all described data in described region to be erased.

12. cache device according to claim 9, it is characterised in that farther include:

Generation unit, it produces the management of the use state indicating the described data being written to the plurality of erasure unit region Information；

Maintenance determines unit, and it determines whether to be written to the described number in described region to be erased based on described management information According to being maintained in described non-volatile cache；And

Transmitting writing unit, it is confirmed as being maintained at described non-volatile in the described data being written to described region to be erased The described data being written to described region to be erased time in property cache memory are written to described non-volatile cache Destination's erasure unit region included in buffer storage.

13. cache device according to claim 12, it is characterised in that

Identification information that described management information comprises described data, the information indicating described data to be whether data to be deleted and The use status information of described data.

14. cache device according to claim 9, it is characterised in that

The described selection unit write time based on the plurality of erasure unit region or write order and from the plurality of wiping Except unit area selects the erasure unit region that instruction said write time or said write order are old to wipe as described waiting Except region.

15. cache device according to claim 9, it is characterised in that

Described selection unit is randomly from region to be erased described in the plurality of erasure unit regional choice.