CN106205685B

CN106205685B - The non-volatile content that can be planned can addressing memory and its operating method

Info

Publication number: CN106205685B
Application number: CN201510226561.8A
Authority: CN
Inventors: 王立中
Original assignee: FlashSilicon Inc
Current assignee: Xinlijia integrated circuit (Hangzhou) Co.,Ltd.
Priority date: 2015-05-06
Filing date: 2015-05-06
Publication date: 2018-08-28
Anticipated expiration: 2035-05-06
Also published as: CN106205685A

Abstract

The present invention provide a kind of non-volatile content planned can addressing memory and its operating method, the non-volatile content can addressing memory include a complementary non-volatile memory device pair and a MOSFET device.The non-volatile content of planning can addressed memory cells can be constructed to form a NOR type matched line nonvolatile memory array and a NAND type matched line nonvolatile memory array.Compared to using address code random access memory can only be accessed according to known storage address, the non-volatile content that the present invention can plan can addressing memory can plan nonvolatile memory contents data in advance and search the calculating process with triggering following using input content data.The non-volatile content that the present invention can plan can the uniqueness of addressing memory provide a key element for neural computing.

Description

The non-volatile content that can be planned can addressing memory and its operating method

Technical field

The present invention is that the non-volatile content in relation to that can plan can addressing memory (Configurable Non- Volatile Content Addressable Memory, CNVCAM), particularly, the non-volatile content that the present invention can plan Can addressing memory can be searched at storage non-volatile content data and using input content data by planning (configued) It seeks.Traditionally, user can only according to known storage address using address code (address code) come access be stored in it is volatile The memory data of property and non-volatile RAM.The non-volatile content that the present invention can plan can addressing memory device Array (array) can be formed multiple essential information processing units by planning, be similar to biological nervous system (biological Nervous system) in processing information gene planning neuronal layers (genetically configured neuron layer)；In biological nervous system, the information content is extracted from the propagation domain of information signal, and is generated from the neuronal layers Perception information and conduction to next connection neuronal layers, such as feedforward (feed-forward) signal processing.

Background technology

Modern Van Neumann type operation framework (von-Neumann computing architecture) as shown in Figure 1 In, central processing unit (CPU) 10 obtains instruction (instruction) by address indicator (pointer) from main memory 11 And data.CPU 10 include a main memory 11, an arithmetic and logic unit (arithmetic and logic unit) 12, Input-output device (equipment) 13 and procedure control unit 14.Before calculating process (process), CPU 10 is directed toward The initial order of main memory 11 and the address code of data are stored in execute.Later, primary storage is accessed according to address indicator The instruction of device 11 and data, sequentially being handled with the clock pulse step (clock steps) of the arithmetic and logic unit 12 of CPU 10 should A little numerical datas.Power (power) that a calculating process is consumed is completed using being represented mathematically as P~f C V_DD ², wherein F indicates clock frequency, C indication circuits total capacitance value (capacitance) and V_DDIndicate the positive supply voltage of digital circuit.Cause This, runs the energy needed for a calculating process program and is proportional to the clock pulse number of steps for completing all instructions, accessing main memory 11 number and charge/discharge starts the total capacitance value of (active) circuit.The instruction step for completing the calculating process is got over Much more with memory data access number, digital circuit must just consume more multipotency amount and time.For example, in memory into The digital content search running of row one needs have multiple data transmission between arithmetic and logic unit 12 and main memory 11 With comparison step.As in current Van Neumann type arithmetic system execute program software along with multiple memory data access with The general implementation of comparison step carries out the energy and search that a content-data search is consumed in a large memories database Time can become there be not very much efficiency.

Operational paradigm is searched to improve, content addressable memory (CAM) has been used in quickly searching for computer system It seeks, such as：World-wide web package route the touching (tagging) in (packet routing) or cache (cache) memory Operational order and parameter.For typical case's CAM runnings, propagation (broadcast) digital content, which enters to have, to prestore The memory cell of multiple memory contents.If the number stored by digital content matching (match) memory cell of the propagation Word content as soon as just will produce matched signal, and is entirely searched running and is completed within a clock pulse step.The matched signal into One step is applied to connect the data channel path (channel pathway) of (switch on) next stage data processing, or opens An instruction begin to execute one group of instruction of the arithmetic system.

In traditional CAM cell (cell), static RAM (SRAM) is applied primarily to memory content Storage.Fig. 2A shows that NOR type matches traditional 10T (10 transistors (transistor)) in linear array, based on SRAM CAM memory cell.Fig. 2 B show that NAND type matches traditional 9T (9 transistors) in linear array, based on SRAM CAM memory cell.When the coupling interaction reverser (crossed inverter) of SRAM stores a digit order number (bit) " 0 " When, connecting has voltage Vss on the node of bit line (BL), and connects paratope lineComplementary node on have voltage V_DD； When the coupling interaction reverser of SRAM stores digit order number " 1 ", there is voltage V on the node of connection bit line (BL)_DD, and even Connect paratope lineComplementary node on have voltage Vss.When to search a digit order number " 0 ", apply voltage V respectively_DDAnd Vss is in search line (SL) and complementary search lineWhen to search digit order number " 1 ", then apply voltage Vss and V respectively_DDIn searching Hunting (SL) and complementary search lineIn the NOR type cam array unit of Fig. 2A, if an input digit order number matches the content The storage position of memory cell, that is, " 1 " matching " 1 " and " 0 " matching " 0 ", the transistor M1 and M3 and transistor M2 of match bit And M4 cannot be simultaneously turned on (turn on) and is grounded so that matched line (ML) is connected.As for the matched NOR type CAM of a line (row) Unit is joined to form single matched line (ML), and the voltage of the matched line can not be pulled low to ground voltage, and the CAM of the row Any of unit, which mismatches position, can lead to connect the matched line to ground voltage.

In the NAND type cam array unit of Fig. 2 B, if an input digit order number matching is stored in the content memorizer unit Position, transistor M2 or M3 in CAM cell are switched on to transmit V_DDTo the grid (gate) of transistor M1.The grid of transistor M1 Extremely possessed voltage (V_DD–V_th) M1 has been connected to connect the left side of the matched line with right side enough, wherein V_thIt is The critical voltage (threshold voltage) of M2 and M3.It is multiple in a line of NAND type matched line cam array by being connected All M1 of match bit form single lead in the row between multiple CAM cells by a plurality of interrupt match line that multiple M1 are connected Logical matched line, and any of row mismatch position can lead to an electrical interrupt match line (ML).

When CPU executes memory content search running, although the CAM cell based on SRAM is in power and speed side Face is very efficient, due to big unit size (cell size) (NOR type 10 transistors of need of the CAM cell based on SRAM And NAND type needs 9 transistors) many silicon areas of integrated circuit (IC), the cost of the CAM cell based on SRAM can be occupied Limit the application of large memories array.It is only limited to smaller kilobit group (kilo-byte) range since the high cost of CAM results in Triggering application to CPU L1 and L2 memory caches, therefore, in terms of more highdensity CAM memory applications, have compared with The smaller CAM unit areas of few device assembly are that quite have the market demand.

In the another aspect of arithmetic system CAM applications, the non-volatile CAM cell that can be planned can provide advising for memory Draw property and it is non-volatile.In other words, the property planned of CAM and one algorithm of non-volatile offer (algorithm) are adjusted with self The arithmetic path learnt from the history (previous recorded history) of precedence record is planned suitablely, and is stored non- The content and path data of volatibility, and without power demand (power requirement) to maintain memory data.

Invention content

The main purpose of the embodiment of the present invention is to provide a kind of non-volatile content can addressing memory and its operation side Method, to realize that the CAM cell by the smaller CAM unit areas with less device assembly stores non-volatile content and road Diameter data, and can be without power demand to maintain memory data.

To achieve the goals above, the embodiment of the present invention provide a kind of non-volatile content can addressing memory, it is described non- Volatile content can addressing memory include：One NOR type matched line nonvolatile memory array, includes multiple NVCAM Unit, is configured with the circuit configurations of row and column, and each NVCAM units include a switching transistor；A plurality of level is prolonged The matched line stretched, each matched line are connected to multiple NVCAM units in a correspondence row；And multiple bit lines pair and a plurality of common source Polar curve extends vertically, and each bit line is to being connected to multiple NVCAM units in a respective column, each common source line connection Multiple NVCAM units in adjacent column are corresponded to two；Wherein, it is divided into multiple lists positioned at the multiple NVCAM units of same a line Member pairing so that the source electrode of the switching transistor of the unit pairing of same row is joined to form a corresponding common source Line, and the drain electrode with the switching transistor of the unit of a line pairing is joined to form a corresponding matched line.

The embodiment of the present invention also provide a kind of non-volatile content can addressing memory, the non-volatile content can addressing Memory includes：One NAND type matched line nonvolatile memory array, includes multiple NVCAM units, has been configured as Multiple NAND strings of row and column arrange, and each NVCAM units include a switching transistor；A plurality of matched line, each matched line It is formed by multiple concatenated switching transistors in a correspondence NAND string row；Multiple bit lines pair, each bit line is to being connected to Multiple NVCAM units in one respective column；And a vertically extending common source line, to connect a plurality of matched line The same side endpoint is to a predeterminated voltage end.

The embodiment of the present invention also provide a kind of non-volatile content can addressing memory operating method, it is described non-volatile Content addressable memory includes a NOR type matched line nonvolatile memory array, and the NOR type matched line is non-volatile to be deposited Memory array includes multiple NVCAM units, is configured with the circuit configurations of row and column, and each NVCAM units include One switching transistor, the operating method comprise the steps of：A plurality of matched line is coupled to the one the of one first voltage of carrying One voltage end, each matched line horizontal extension and is connected to multiple NVCAM units in a correspondence row；It is a plurality of in the coupling Matched line to one first voltage of carrying a first voltage end the step of after, carry out one and search running, it is one defeated by applying Enter serial data in multiple bit lines pair and a plurality of common source line is coupled to a second voltage end of one second voltage of carrying, it is each described Bit line is extended vertically and is connected to extending vertically and being connected to multiple NVCAM units in a respective column, each common source line Multiple NVCAM units in adjacent column are corresponded to two, wherein be divided into positioned at the multiple NVCAM units of same a line multiple Unit matches so that the source electrode of the switching transistor of the unit pairing of same row is joined to form a corresponding common source Line, and the drain electrode with the switching transistor of the unit of a line pairing is joined to form a corresponding matched line；And if The input data string mismatches the serial data stored by multiple NVCAM units described in a line, and conducting at least a pair should switch Transistor is equal to the second voltage with the voltage for changing a correspondence matched line, otherwise closes all corresponding switching transistors to tie up The voltage for holding the Corresponding matching line is the first voltage.

The embodiment of the present invention also provide a kind of non-volatile content can addressing memory operating method, which is characterized in that The non-volatile content can addressing memory include a NAND type matched line nonvolatile memory array, the NAND type Wiring nonvolatile memory array includes multiple NVCAM units, is configured as multiple NAND strings row of row and column, each institute It includes a switching transistor to state NVCAM units, and the operating method comprises the steps of：A plurality of matched line is coupled to carrying one One first voltage end of first voltage, each matched line horizontal extension and concatenated is cut by multiple in a correspondence NAND string row Transistor is changed to be formed；After the step of coupling a first voltage end of a plurality of matched line to one first voltage of carrying, into Row one searches running, and one second electricity of carrying is coupled in multiple bit lines pair and by a common source line by one input data string of application One second voltage end of pressure, for each bit line to multiple NVCAM units for being connected in a respective column, the common source line is vertical Extend to connect the same side endpoint of a plurality of matched line to the second voltage end；And if the input data string is not With the stored serial data of NAND string row, close the NAND string row at least one corresponds to switching transistor to remain described right It is the first voltage to answer the voltage of matched line, and all corresponding switching transistors of the NAND string row are otherwise connected to change The voltage for stating Corresponding matching line is equal to the second voltage.

Description of the drawings

To more fully understand the present invention and its specific implementation mode, below with reference to the attached drawing of the embodiment of the present invention, to this Technical solution in inventive embodiments is clearly and completely described, wherein：

Fig. 1 shows the Van Neumann type operation framework of an existing CPU；

Fig. 2A shows the cam array unit based on SRAM of existing NOR type matched line；

Fig. 2 B show the cam array unit based on SRAM of existing NAND type matched line；

Fig. 3 show one embodiment of the invention the non-volatile content planned can addressing memory (CNVCAM) unit, Including a complementary non-volatile memory device pair and a N-type MOSFET device；

Fig. 4 shows the NMOSFET NOR type matching linear array of the positions the n- x m- rows of the CNVCAM units using Fig. 3；

Fig. 5 shows the non-volatile ternary of NMOSFET NOR type (ternary) CAM cell operation scheme：It plans non-volatile Property the definition (top row) of data, the definition (center row) of input data 1 and the definition (bottom of input data 0 when being operated into line search Row)；

Fig. 6 shows the NMOSFET NAND type matching linear array of the positions the n- x m- rows of the CNVCAM units using Fig. 3；

Fig. 7 shows the non-volatile ternary CAM cell operation scheme of NMOSFET NAND type：Plan Nonvolatile data The definition (center row) of input data 1 and the definition (bottom row) of input data 0 when defining (top row), being operated into line search；

Fig. 8 show one embodiment of the invention the non-volatile content planned can addressing memory (CNVCAM) unit, Including a complementary non-volatile memory device pair and a p-type MOSFET device；

Fig. 9 shows the PMOSFET NOR type matching linear array of the positions the n- x m- rows of the CNVCAM units using the 8th figure；

Figure 10 shows the non-volatile ternary CAM cell operation scheme of PMOSFET NOR type：Plan Nonvolatile data The definition (center row) of input data 1 and the definition (bottom row) of input data 0 when defining (top row), being operated into line search；

Figure 11 shows the PMOSFET NAND type matching linear array of the positions the n- x m- rows of the CNVCAM units using Fig. 8；

Figure 12 shows the non-volatile ternary CAM cell operation scheme of PMOSFET NAND type：Plan Nonvolatile data Definition (top row), the definition (center row) of input data 1 and the definition (bottom row) of input data 0 when being operated into line search；

Figure 13 shows the NMOSFET NOR type matched lines of the one unit born of the same parents of use (unit cell) of one embodiment of the invention The schematic diagram of CNVCAM arrays, unit born of the same parents include complementary floating boom (floating gate) nonvolatile memory dress It sets pair and a N-type MOSFET device；

Figure 14 shows CNVCAM gusts of the NMOSFET NAND type matched lines of the one unit born of the same parents of use of another embodiment of the present invention The schematic diagram of row, unit born of the same parents include a complementary floating gate non-volatile memory device pair and a N-type MOSFET device；

Figure 15 shows the PMOSFET NOR type matched line CNVCAM arrays of the one unit born of the same parents of use of another embodiment of the present invention Schematic diagram, unit born of the same parents include a complementary floating gate non-volatile memory device pair and a p-type MOSFET device；

Figure 16 shows CNVCAM gusts of the PMOSFET NAND type matched lines of the one unit born of the same parents of use of another embodiment of the present invention The schematic diagram of row, unit born of the same parents include a complementary floating gate non-volatile memory device pair and a p-type MOSFET device.

Reference numeral

10 CPU

11 main memories

12 arithmetic and logic units

13 input-output devices

14 procedure control units

40 NMOSFET NOR type matched line cam array

60 NMOSFET NAND type matched line cam array

90 PMOSFET NOR type matched line cam array

110 PMOSFET NAND type matched line cam array

The NMOSFET NOR type matched line cam array of 130 n- x m- row

The NMOSFET NAND type matched line cam array of 140 n- x m- row

The PMOSFET NOR type matched line cam array of 150 n- x m- row

The PMOSFET NAND type matched line cam array of 160 n- x m- row

131,141,154,164 PMOSFET devices

151,161,134,144 NMOSFET devices

132,142,152,162 reverser

133,143,153,163 Data buffer

135,145,155,165 node

300, the 800 non-volatile CAM cell that can be planned

310,320 two complementary non-volatile memory devices

330 NMOSFET devices

311,321,811,821 input node

315,815 output node

The grid of 331 NMOSFET devices

The source electrode of 332 NMOSFET devices

The drain electrode of 333 NMOSFET devices

400, Unit 900 match

810,820 two complementary non-volatile memory devices

830 PMOSFET devices

The grid of 831 PMOSFET devices

The source electrode of 832 PMOSFET devices

The drain electrode of 833 PMOSFET devices

Specific implementation mode

It is described further below merely illustrative, and it is unrestricted.It is to be understood that other embodiment can be used, and can to structure Various modifications or change are carried out, the range of claims of the present invention should all be fallen into.And, it will thus be appreciated that this specification used Grammer and term are only to illustrate, without that should be viewed as a limitation.Those skilled in the art, it is to be appreciated that in this specification method and The embodiment of schematic diagram is merely illustrative, and unrestricted.Spirit of that invention is understood because of the exposure of this specification is familiar with this field Person can be used other embodiment, should all fall into the range of the claims in the present invention.

The present invention is using a complementary non-volatile memory device to (pair) and a metal-oxide semiconductor (MOS) Field-effect transistor (Metal Oxide Semiconductor Field Effect, MOSFET) is mono- to form a basic CAM First (cell).One digital content position can be planned in the complementary non-volatile memory device centering, by the way that the complementation is non-easily Two device ends of each non-volatile memory device of the property lost memory device pair are set as " conducting (conducting) shape Two device ends are electrical connected by state ", and by by each non-volatile of the complementary non-volatile memory device pair Two device ends of memory device are set as " nonconducting state " and two device ends electrically disconnect (disconnect). Those non-volatile CAM cells can be planned and be respectively formed NOR type matching linear array (match line array) and one NAND type matches linear array.A string of input digital content data signals (such as a hyte, a word or a sentence) can be simultaneously The non-volatile cam array that can be planned is spread into carry out a digital content matching.Later, matched signal is used to touch Sending out data processing, instruction execution or the two continuous has.

Referring to FIG. 3, the non-volatile CAM cell 300 that can be planned includes two complementary nonvolatile memories (NVM) Device 310,320 and N-type MOSFET (NMOSFET) device 330.One end of each complementary non-volatile memory device It is connected together to output node 315 of the complementary non-volatile memory device to (pair) 310,320, and the complementation is non-volatile Other both ends of property memory device pair are respectively formed two input nodes 311,321.Output node 315 is connected to source electrode The gate electrode 331 of electrode (source electrode) 332 and the NMOSFET devices 330 of drain electrode (drain) electrode 333.Such as NMOSFET NOR type matched line cam array (n- x m- rows) 40 shown in Fig. 4, per the multiple of a line (row) CAM cell 300 NMOSFET devices 330 are connected to the circuit configurations of multiple unit pairing (cell pair) 400 so that each unit pairing 400 There are one common source electrode 332 and two drain electrodes 333, two drain electrodes 333 to be connected to multiple lists of the row for tool The matched line of member pairing 400.NMOSFET NAND type matched line cam array (n- x m- rows) 60 as shown in FIG. 6, per a line Multiple NMOSFET devices 330 of CAM cell 300 are formed the matched line of the row by series connection.

The complementary non-volatile memory device pair 310,320 can be programmed, one of them is made to be in " conducting shape State ", and another is then in " nonconducting state ".For example, being related NMOSFET NOR type matched line as shown in the top row of Fig. 5 Cam array 40 is to deposit the complementary non-volatile for being connected to bit line B and B to planning (or storage) Nonvolatile data 1 Reservoir device pair 310,320 distinguishes sequencing to " nonconducting state " and " conducting state "；It is non-volatile to planning (or storage) Property data 0, then will be connected to bit line B andThe complementary non-volatile memory device pair 310,320 distinguish sequencing to " leading Logical state " and " nonconducting state "；To planning (or storage) random position (don ' t care bit), then by two complementations The all sequencing of non-volatile memory device 310,320 export section to " nonconducting state " with (floating) with a suspension joint Point M.

The case where one input digital data 1 is to apply V as shown in the center row of Fig. 5_DDAnd V_SSTo bit line B andWith It is operated into line search；The case where being then input digital data 0 shown in bottom row as Fig. 5 is to apply V_SSAnd V_DDTo position Line B andTo be operated into line search.When the storage data phase of the input digital data and the non-volatile CAM cell 300 of a line When matching, each output node of jth row as shown in Figure 4, those complementary non-volatile memory devices pair of the row exports V_SS With all NMOSFET devices 330 of matched non-volatile CAM cell 300 in closing (turn off) row.As a result, matching The matched line ML (j) of the row of non-volatile CAM cell 300 electrically disconnect be connected to the common source line of ground voltage completely CSL.Any one non-match bit can cause the output node 315 for not matching CAM cell at this to generate voltage V in the row_DDTo lead Lead to its corresponding NMOSFET device 330, and then is electrically connected the matched line one of to those CSL lines.Pass through any one non-match bit The matched line is electrically connected to those CSL lines, the voltage of the NMOSFET NOR type matched lines of non-matching row can be pulled low to ground connection electricity Pressure.The case where as random position, the suspension joint that the output node M of the complementary non-volatile memory device pair 310,320 has are electric Its corresponding NMOSFET device 330 can not be connected to be electrically connected the matched line to the CSL lines of its connection, so can be considered as in pressure " match bit ".

NMOSFET NAND type matched lines cam array 60 is related to as shown in the top row of Fig. 7, to planning (or storage) Nonvolatile data 1, be will be connected to bit line B andThe complementary non-volatile memory device pair 310,320 distinguish program Change to " conducting state " and " nonconducting state "；To planning (or storage) Nonvolatile data 0, then will be connected to bit line B andThe complementary non-volatile memory device pair 310,320 distinguish sequencing to " nonconducting state " and " conducting state ".

The case where one input digital data 1, applies V as shown in the center row of Fig. 7_DDAnd V_SSTo bit line B andWith into Line search operates；The case where being input digital data 0 as shown in the bottom row of Fig. 7, applies V_SSAnd V_DDTo bit line B andWith It is operated into line search.When the data match of the input digital data and the non-volatile CAM cell 300 of a line, such as Fig. 6 institutes Show that the matched CAM cell 300 of jth row, each output node of those complementary non-volatile memory devices pair of the row are defeated Go out V_DDAll NMOSFET devices 330 in the row are connected.As a result, the matching of the row of matched non-volatile CAM cell 300 Line ML (j) is electrically connected right node 611 with left node 610 to form single conducting matched line.Any one is not in the row Coordination can cause an interruption that matched line is connected, because not matching the defeated of the complementary non-volatile memory device pair of CAM cell Egress 315 will produce voltage V_SSTo close its NMOSFET device 330.The interruption conducting matching of the row of CAM cell is not matched Line can not be electrically connected to form a right node from series connection NMOSFET NAND strings row (NAND-string) to left node Single conducting matched line.

As for the running of the random position of NAND type matched line cam array 60, for tool " random position " the CAM cell it is defeated Egress 315 must have voltage V_DDIt is set to be considered as in the NAND matched lines of the row " match bit ".In a search running, In order to make the 315 output voltage V of output node of the CAM cell with " random position "_DD, apply voltage V_DDAnd V_SSTo two bit line B AndAnd two complementary non-volatile memory devices 310,320 of the CAM cell are without forbidden (forbidden) group State, that is, two devices 310,320 are not simultaneously at " nonconducting state ".

Referring to FIG. 8, the non-volatile CAM cell 800 that can be planned includes two complementary non-volatile memory devices 810,820 and p-type MOSFET (PMOSFET) device 830.One end of each complementary non-volatile memory device is connected To form the output node 815 of the complementary non-volatile memory device pair 810,820, and the complementary non-volatile memory device It sets and two input nodes 811,821 is respectively formed to 810,820 other both ends.Output node 815 is connected to positioned at a N-type well (well) gate electrode 831 in, with source electrode 832 Yu the PMOSFET devices 830 of drain electrode 833.As shown in Figure 9 PMOSFET NOR type matched lines cam array (n- x m- rows) 90, per multiple PMOSFET devices of a line CAM cell 800 830 are connected to the circuit configurations of multiple units pairing 900 so that each unit pairing 900 have a common source electrode 832 and Two drain electrodes 833, two drain electrodes 833 are connected to the matched line of the row.PMOSFET NAND as shown in figure 11 Type matched line cam array (n- x m- rows) 110, multiple PMOSFET devices 830 per a line CAM cell 800 are formed by series connection The matched line of the row.

The complementary non-volatile memory device pair 810,820 can be programmed, one of them is made to be in " conducting shape State ", and another is then in " nonconducting state ".For example, relating to the matching of PMOSFET NOR type as shown in the top row of Figure 10 Line cam array 90, to planning (or storage) Nonvolatile data 1, be will be connected to bit line B andThe complementary non-volatile Memory device pair 810,820 distinguishes sequencing to " conducting state " and " nonconducting state "；It is non-easily to planning (or storage) Lose property data 0, then will be connected to bit line B andThe complementary non-volatile memory device pair 810,820 difference sequencing extremely " nonconducting state " and " conducting state "；To planning (or storage) random position, then by two complementary non-volatile storages The all sequencing of device device 810,820 are to " nonconducting state " with the output node M with a suspension joint.

The case where one input digital data 1, applies V as shown in the center row of Figure 10_DDAnd Vss to bit line B andWith It is operated into line search；The case where one input digital data 0, applies Vss and V as shown in the bottom row of Figure 10_DDTo bit line B andTo be operated into line search.When the data match of an input digital data and the non-volatile CAM cell 800 of a line, such as scheme Jth row shown in 9, the 815 output voltage V of each output node of those complementary non-volatile memory devices pair of the row_DDWith Close all PMOSFET devices 830 in the row of matched non-volatile CAM cell.As a result, those matchings are non-volatile in Fig. 9 The matched line ML (j) of the row of property CAM cell 800 electrically disconnects completely is connected to the right path (positive rail) voltage V_DD's CSL lines.Any one non-match bit can cause the output node 815 for not matching CAM cell at this to generate voltage V in the row_SSWith The PMOSFET devices 830 of the row are connected, and then are electrically connected the matched line one of to those CSL lines.Pass through any one non-match bit The matched line is connected to those CSL lines, the voltage of the PMOSFET NOR type matched lines of non-matching row can be charged to V_DD.As for The case where random position, the suspension joint voltage that the output node 815 of the complementary non-volatile memory device pair 810,820 has can not It is connected and corresponds to PMOSFET devices 830 to be electrically connected the matched line to the CSL lines of its connection, so " a matching can be considered as Position ".

PMOSFET NAND type matched lines cam array 110 is related to as shown in the top row of Figure 12, to planning (or storage Deposit) Nonvolatile data 1 is the complementary non-volatile memory device pair 810, the 820 difference journey that will be connected to bit line B and B Sequence is to " nonconducting state " and " conducting state "；To planning (or storage) Nonvolatile data 0, then bit line B will be connected to AndThe complementary non-volatile memory device pair 810,820 distinguish sequencing to " conducting state " and " nonconducting state ".

The case where one input digital data 1, applies V as shown in the center row of Figure 12_DDAnd Vss to bit line B andWith It is operated into line search；The case where one input digital data 0, applies Vss and V as shown in the bottom row of Figure 12_DDTo bit line B andTo be operated into line search.When the data match of an input digital data and the non-volatile CAM cell 800 of a line, such as The matched non-volatile CAM cell of jth row shown in Figure 11, those complementary non-volatile memory devices pair of the row it is each Output node exports V_SSAll PMOSFET devices 830 in the row are connected.As a result, those match non-volatile CAM cell The matched line ML (j) of 800 row is electrically connected to left node 1110 to form single conducting matched line from right node 1111. Any one non-match bit can cause an interruption that matched line is connected in the row, because the complementation for not matching CAM cell is non-volatile The output node 815 of property memory device pair will produce voltage V_DDTo close its PMOSFET device 830.It is mono- that those do not match CAM The interruption conducting matched line of the row of member can not be electrically connected to form a right node arranged from series connection PMOSFET NAND strings It is conducting to the single conducting matched line of left node.

As for the running of the random position of PMOSFET NAND type matched lines cam array 110, for the random of the CAM cell Position, output node 815 must have voltage V_SSIt is set to be considered as " match bit " in the PMOSFET NAND matched lines of the row. In a search running, in order to make the 815 output voltage Vss of output node of the CAM cell with " random position ", apply voltage V_SSTo two bit line B andAnd two complementary non-volatile memory devices 810,820 of the CAM cell are not forbidden Configuration, that is, two devices 810,820 are not simultaneously at " nonconducting state ".

Figure 13 shows the NMOSFET NOR type matched lines cam array 130 of the positions the n- x m- rows with m- row matching detectors Schematic diagram.The complementary non-volatile memory device of those in cam array 130 is to being complementary floating gate non-volatile memory Device pair.Using good fortune fowler-nordham tunneling (Fowler-Nordheim tunneling) method or it is exposed in Chinese patent application (contents of which patents are collectively referred to herein herein as this specification numbers 201410273261.0 second heat electron injection method The some of content), it can be by the supreme threshold voltage state V of those floating gate non-volatile memory program of deviceization_thH, to avoid Flagrant non-volatile memory device penetrates (punch-through) problem.Known to industry, tunneling method is utilized Electronics is removed from floating boom, can erase those floating gate non-volatile memory devices (erase) extremely low critical voltage shape State V_thL.As being exposed in Chinese Patent Application No. 201310145384.1, (contents of which patents are collectively referred to herein conduct herein The some of the content of the present specification) technology, complementary floating gate non-volatile memory device pair can be programmed, make therein One device is to be located at high threshold voltage state V_thH, and another device is then located at low threshold voltage state V_thL.When applying respectively Voltage bias (bias) V_CG(V_thH>V_CG>(V_thL+V_DD))、V_DDAnd V_SSTo complementary floating gate non-volatile memory device pair When controlling door and two input nodes so that a device therein is connected and closes another device, a digital voltage signal (V_DDOr V_SS) it is just shown delivered directly to the output node of complementary floating gate non-volatile memory device pair, and need not the amplification of any sensing Device (sensing amplifier) is to carry out digital signal conversion.

To plan the non-volatile CAM cell, initially by those complementary non-volatile memory devices to erasing To low threshold voltage state V_thL.Later, it is noted using the secondary thermoelectron for being exposed in Chinese Patent Application No. 201410273261.0 Enter method to plan those complementary non-volatile memory devices pair, that is, applies voltage bias V_DD(~3V) to programs device Drain electrode (B and), the drain electrode of the non-programs device of suspension joint and apply high voltage pulse wave (pulse) (amplitude >V_DD) to the row non-volatile memory device control grid, as shown in figure 13.It is fixed according to being planned shown in the row of the tops Fig. 5 Justice, the Nonvolatile data of array 130 in planning chart 13.In other words, to planning (or storage) Nonvolatile data 1, be by Be connected to bit line B andThe complementary non-volatile memory device to sequencing respectively to high threshold voltage state V_thHAnd dimension It holds in low threshold voltage state V_thL；To planning (or storage) Nonvolatile data 0, then will be connected to bit line B andThis mutually Non-volatile memory device is mended to being respectively maintained at low threshold voltage state V_thLAnd sequencing is to high threshold voltage state V_thH。 To planning (or storage) random position, by the complementary non-volatile memory device to all sequencing to high threshold voltage state V_thHAnd make the grid of NMOSFET devices that there is the output node of a suspension joint.

After the completion of the Nonvolatile data planning of array 130, when to input data 1 to be operated into line search, then apply Making alive V_DDAnd V_SSTo two bit line B andWhen to input data 0 to be operated into line search, then apply voltage V_SSAnd V_DDTo two Bit line B andThe positive voltage V of logic core Voltage rails (logic core voltage rail)_DDBe between 0.9V to 1.2V it Between, so transmitting V_DDWhen those floating gate non-volatile memory devices reading interference (read will not occur disturbance).Apply logic core voltage signal V_DDAnd V_SS, to be respectively turned on and close the NMOSFET of those CAM cells Device.As shown in figure 13, to search whether a digital content matches the Nonvolatile digital content planned, according to digital value, Apply a succession of comprising multiple 0 and 1 input digital signal to multiple bit lines B (1:N) and(1:n).When the CAM cell of a line When there are multiple non-match bits to generate, V is transmitted_DDIt does not match the NMOSFET devices of CAM cell with conducting, and then is electrically connected its matching Line is to those common source lines CSL (1:n/2).The case where all matching or part matching are together with random position for digital content, should A little complementary non-volatile memory devices are to that can transmit Vss to close the NMOSFET devices of all matching CAM cells of the row. The matched line of the matching row can fully electrically disconnect those common source lines CSL.

Matched line per a line connects a matching detector, which includes that a PMOSFET devices 131, one are anti- To device (inverter) 132 and a Data buffer (data flip-flop) 133.The PMOSFET devices 131, to should Matched line charges to voltage V_DD；Reverser 132 is sensing the voltage of matched line；Data buffer 133 is capturing (catch) The matched data of Figure 13 matching detectors left.When on node 135 matching enable signal (match enable signal, MtchEnb) it is equal to voltage V_SS(regard as initial number value 0) and when not being activated (activated), all rows in array 130 Matching detector is all disabled (disabled), and all PMOSFET devices 131 are all switched on to charge and tie up in array 130 Matching line voltage is held to V_DD.When the matching enable signal (MtchEnb) becomes voltage V_DDWhen being operated into line search, NMOSFET Device 134 is switched on to connect those common source lines CSL to ground voltage.During being operated into line search, those PMOSFET dresses 131 are set all to be turned off to that those matching detectors is avoided to generate any DC electric current path by those matched lines.Search running Period, by those common source lines CSL and NMOSFET devices 134, the matching line voltage of non-matching row is by V_DDIt is discharged to V_SS.By The output end of reverser 132, Data buffer 133 capture to non-matching row and do not match line voltage V_DD, therefore, into line search During running, the signal for the non-matching row that Data buffer 133 captures is V_DD.For a matching row, matched line Voltage maintains V_DD, without electrical discharge path to ground.When being operated into line search, the Data buffer 133 of matching row is picked The signal got is V_SS, and the signal that the Data buffer 133 of non-matching row captures is V_DD.Because in an input number The non-volatile digital content of Rong Yuyi planning matches and the digital data signal V that is captured by Data buffer 133_SS, It can be used to connect a data path or triggering execute one group of operational order.

Figure 14 shows the NMOSFET NAND type matched lines cam array 140 of the positions the n- x m- rows with m row matching detectors Schematic diagram.The complementary non-volatile memory device of those in cam array 140 is to being complementary floating gate non-volatile memory Device pair.Using good fortune fowler-nordham tunneling method or it is exposed in the secondary thermoelectricity of Chinese Patent Application No. 201410273261.0 Sub- method for implanting, can be by the supreme threshold voltage state V of those floating gate non-volatile memory program of deviceization_thH, to avoid bad reputation Evident non-volatile memory device penetration problem.Electronics is removed from floating boom using tunneling method, those can be floated Gate nonvolatile memory device is erased to low threshold voltage state V_thL.As being exposed in Chinese Patent Application No. 201310145384.1 technology, complementary floating gate non-volatile memory device pair can be programmed, so that therein one Device is to be located at high threshold voltage state V_thH, and another device is then located at low threshold voltage state V_thL.It is inclined when applying respectively Press V_CG(V_thH>V_CG>(V_thL+V_DD))、V_DDAnd V_SSTo the control door of complementary floating gate non-volatile memory device pair and two When input node is to be connected a device therein and close another device, a digital voltage signal (V_DDOr V_SS) just direct It is transferred to the output node of complementary floating gate non-volatile memory device pair, and without any sensing amplifier to carry out number Signal is converted.

To plan the non-volatile CAM cell, initially by those complementary non-volatile memory devices to erasing To low threshold voltage state V_thL.Later, it is noted using the secondary thermoelectron for being exposed in Chinese Patent Application No. 201410273261.0 Enter method to plan those complementary non-volatile memory devices pair, that is, is biased V_DD(~3V) to the leakage of programs device Pole electrode (B and), the drain electrode of the non-programs device of suspension joint, and apply a high voltage pulse wave (amplitude>V_DD) to the row Non-volatile memory device control grid, as shown in figure 14.It is defined according to being planned shown in the row of the tops Fig. 7, planning chart 14 The Nonvolatile data of middle array 140.In other words, it is that will be connected to bit line B to planning (or storage) Nonvolatile data 1 AndThe complementary non-volatile memory device to being respectively maintained at low threshold voltage state V_thLAnd the supreme critical electricity of sequencing Pressure condition V_thH；To planning (or storage) Nonvolatile data 0, then will be connected to bit line B andThe complementary non-volatile deposit Reservoir device is to sequencing respectively to high threshold voltage state V_thHAnd maintain low threshold voltage state V_thL。

After the completion of the Nonvolatile data planning of array 140, when to input data 1 to be operated into line search, then apply Making alive V_DDAnd Vss to two bit line B andWhen to input data 0 to be operated into line search, then apply voltage Vss and V_DDExtremely Two bit line B and B.For random position, apply voltage V_DDTo two bit line B and B, and the complementary non-volatile memory device is not to having Forbidden configuration, that is, two complementary non-volatile memory devices are not simultaneously at " nonconducting state ".Logic Core electrocardio Press the positive voltage V of rail_DDIt is between 0.9V between 1.2V, so in transfer overvoltage V_DDWhen those floating gate non-volatile memories Reading interference will not occur for device.Apply logic core voltage V_DDAnd Vss, to be respectively turned on and close those CAM cells NMOSFET devices.As shown in figure 14, to search whether a digital content matches the Nonvolatile digital content planned, according to Digital value applies a succession of comprising multiple 0 and 1 input digital signal to multiple bit lines B (1:N) and(1:n).When a line When CAM cell has multiple non-match bits to generate, on the output node that transmits those complementary non-volatile memory devices pair V_SSTo close the NMOSFET devices that those do not match CAM cell, and then the matched line for the row that electrically disconnects.For digital content The case where all matching or part matching are together with random position, those complementary non-volatile memory devices are to that can transmit V_DDTo lead Lead to the NMOSFET devices of all matching CAM cells of the row.The matched line of the matching row can be electrically connected.

Matched line per a line connects a matching detector, which includes that a PMOSFET devices 141, one are anti- To device 142 and a Data buffer 143.The PMOSFET devices 141, matched line is charged to voltage V_DD；Reverser 142 To sense the voltage of matched line；Data buffer 143 is capturing the matched data of Figure 14 matching detectors left.Work as node Matching enable signal (MtchEnb) on 145 is equal to voltage V_SS(regard as initial number value 0) and when not being activated, in array 140 The matching detector of all rows is all disabled, and all PMOSFET devices 141 are all switched on to charge and maintain in array 140 Line voltage is matched to V_DD.As shown in figure 14, when matching enable signal (MtchEnb) becomes voltage V_DDWhen being operated into line search, NMOSFET devices 144 are switched on to be electrically connected common source line CSL and then vertically connect the left sibling of the respectively matched line to connecing Ground voltage.During being operated into line search, those PMOSFET devices 141 are all turned off to that those matching detectors is avoided to pass through Those matched lines generate any DC electric current path.The matching line voltage of non-matching row maintains V_DDTo form electrically interrupted Wiring.By the output end of reverser 142, Data buffer 143 captures to non-matching row and does not match line voltage V_SS.It note that To avoid the matching detector and part matched line charge share from generating significant V_DDVoltage drop causes erroneous matching interpretation, Capacitance with detector must be considerably larger than the capacitance of matched line.Therefore, during being operated into line search, Data buffer The signal of the 143 non-matching rows captured is V_SS.For the one completely matching row of electrical connection matched line, matched line and inspection The voltage of device input node is surveyed from V_DDIt is discharged to ground voltage.When being operated into line search, the Data buffer 143 of matching row is picked The signal got is V_DD.It is temporary by data because an input digital content and the non-volatile digital content of a planning match The digital data signal that device 143 captures can be used to connect a data path or triggering execute one group of operational order.

Figure 15 shows the PMOSFET NOR type matched lines cam array 150 of the positions the n- x m- rows with m row matching detectors Schematic diagram.The complementary non-volatile memory device of those in cam array 150 is to being complementary floating gate non-volatile memory Device pair.Using good fortune fowler-nordham tunneling method or it is exposed in the secondary thermoelectricity of Chinese Patent Application No. 201410273261.0 Sub- method for implanting, can be by the supreme threshold voltage state V of those floating gate non-volatile memory program of deviceization_thH, to avoid bad reputation Evident non-volatile memory device penetration problem.Known to industry, electronics is moved from floating boom using tunneling method It removes, those floating gate non-volatile memory devices can be erased to low threshold voltage state V_thL.Such as it is exposed in Chinese patent application Numbers 201310145384.1 technology, complementary floating gate non-volatile memory device pair can be programmed, so that therein One device is to be located at high threshold voltage state V_thH, and another device is then located at low threshold voltage state V_thL.When applying respectively Bias V_CG(V_thH>V_CG>(V_thL+V_DD))、V_DDAnd V_SSTo the control door and two of complementary floating gate non-volatile memory device pair When a input node is to be connected a device therein and close another device, a digital voltage signal (V_DDOr V_SS) just straight Connect the output node for being transferred to complementary floating gate non-volatile memory device pair, and need not any sensing amplifier with into line number Word signal is converted.

To plan the non-volatile CAM cell, initially by those complementary non-volatile memory devices to erasing To low threshold voltage state V_thL.Later, it is noted using the secondary thermoelectron for being exposed in Chinese Patent Application No. 201410273261.0 Enter method to plan those complementary non-volatile memory devices pair, that is, is biased V_DD(~3V) to the leakage of programs device Pole electrode (B and), the drain electrode of the non-programs device of suspension joint and with apply a high voltage pulse wave (amplitude>V_DD) extremely should The control grid of capable non-volatile memory device, as shown in figure 15.It is defined according to being planned shown in the row of the tops Figure 10, planning chart The Nonvolatile data of array 150 in 15.In other words, it is that will be connected to bit line to planning (or storage) Nonvolatile data 1 B andThe complementary non-volatile memory device to being respectively maintained at low threshold voltage state V_thLAnd sequencing is supreme critical Voltage status V_thH；To planning (or storage) Nonvolatile data 0, then the complementary non-volatile of bit line B and B will be connected to Memory device is to sequencing respectively to high threshold voltage state V_thHAnd maintain low threshold voltage state V_thL.To planning (or storage) random position, by two complementary non-volatile memory devices all sequencing to high threshold voltage state V_thHAnd So that the grid of PMOSFET devices has the output node of a suspension joint.

After the completion of the Nonvolatile data planning of array 150, when to input data 1 to be operated into line search, then apply Making alive V_DDAnd Vss to two bit line B andWhen to input data 0 to be operated into line search, then apply voltage Vss and V_DDExtremely Two bit line B andThe positive voltage V of logic core Voltage rails_DDIt is between 0.9V between 1.2V, so transmitting V_DDWhen those are floating Reading interference will not occur for gate nonvolatile memory device.Apply logic core voltage V_DDAnd Vss, to close and be connected respectively The PMOSFET devices of those CAM cells.As shown in figure 15, for search a digital content whether match planned it is non-volatile Digital content applies a succession of comprising multiple 0 and 1 input digital signal to multiple bit lines B (1 according to digital value:N) and (1:n).When there are multiple non-match bits to generate in the CAM cell of a line, V is transmitted_SSCAM cell is not matched with conducting PMOSFET devices, and then its matched line is electrically connected to those common source lines CSL (1:n/2).For digital content all matching or The case where part matching is together with random position, those complementary non-volatile memory devices are to that can transmit V_DDIt is all to close the row Match the PMOSFET devices of CAM cell.The matched line of the matching row can fully electrically disconnect those common source lines CSL.

Matched line per a line connects a matching detector, which includes that a NMOSFET devices 151, one are anti- To device 152 and a Data buffer 153.The NMOSFET devices 151, the matched line to be grounded；Reverser 152 is feeling Survey the voltage of the matched line；Data buffer 153 is capturing the matched data of Figure 15 matching detectors left.When node 155 On matching enable signal (MtchEnb) be equal to voltage V_SS(regard as initial number value 0) and when not being activated, institute in array 150 There is capable matching detector to be all disabled, and all NMOSFET devices 151 are all switched on so that matched line to discharge in array 150 To V_SS.When matching enable signal (MtchEnb) becomes voltage V_DDWhen being operated into line search, PMOSFET devices 154 are switched on To connect those common source lines CSL to positive voltage V_DD.During being operated into line search, those NMOSFET devices 151 are all closed To disconnect ground voltage, and then those matching detectors is avoided to generate any DC electric current path by those matched lines.It searches During running, by those common source lines CSL and PMOSFET devices 154, the matching line voltage of non-matching row is by V_SSIt charges to V_DD.By the output end of reverser 152, Data buffer 153 captures to non-matching row and does not match line voltage V_SS, therefore, into During line search operates, the signal for the non-matching row that Data buffer 153 captures is V_SS.For a matching row, The voltage of wiring maintains V_SS, without charge path to V_DD.When being operated into line search, 153 institute of Data buffer of matching row The signal captured is V_DD, and the signal that the Data buffer 153 of non-matching row captures is V_SS.Because of an input number The content and non-volatile digital content of a planning matches and the digital data signal that is captured by Data buffer 153 V_DD, can be used to connect a data path or triggering execute one group of operational order.

Figure 16 shows the PMOSFET NAND type matched lines cam array 160 of the positions the n- x m- rows with m row matching detectors Schematic diagram.The complementary non-volatile memory device of those in cam array 160 is to being complementary floating gate non-volatile memory Device pair.Using good fortune fowler-nordham tunneling method or it is exposed in the secondary thermoelectricity of Chinese Patent Application No. 201410273261.0 Sub- method for implanting, can be by the supreme threshold voltage state V of those floating gate non-volatile memory program of deviceization_thH, to avoid bad reputation Evident non-volatile memory device penetration problem.Electronics is removed from floating boom using tunneling method, those can be floated Gate nonvolatile memory device is erased to low threshold voltage state V_thL.As being exposed in Chinese Patent Application No. 201310145384.1 technology, complementary floating gate non-volatile memory device pair can be programmed, so that therein one Device is to be located at high threshold voltage state V_thH, and another device is then located at low threshold voltage state V_thL.It is inclined when applying respectively Press V_CG(V_thH>V_CG>(V_thL+V_DD))、V_DDAnd V_SSTo the control door of complementary floating gate non-volatile memory device pair and two When input node is to be connected the device of one of them and close another device, a digital voltage signal (V_DDOr V_SS) just straight Connect the output node for being transferred to complementary floating gate non-volatile memory device pair, and need not any sensing amplifier with into line number Word signal is converted.

To plan the non-volatile CAM cell, initially by those complementary non-volatile memory devices to erasing To low threshold voltage state V_thL.Later, it is noted using the secondary thermoelectron for being exposed in Chinese Patent Application No. 201410273261.0 Enter method to plan those complementary non-volatile memory devices pair, that is, applies voltage bias V_DD(~3V) to programs device Drain electrode (B and), the drain electrode of the non-programs device of suspension joint and apply a high voltage pulse wave (amplitude>V_DD) extremely The control grid of the non-volatile memory device of the row, as shown in figure 16.According to definition is planned shown in the row of the tops Figure 12, plan The Nonvolatile data of array 160 in Figure 16.In other words, it is that will be connected to position to planning (or storage) Nonvolatile data 1 Line B andThe complementary non-volatile memory device to sequencing respectively to high threshold voltage state V_thHAnd maintain low face Boundary voltage status V_thL；To planning (or storage) Nonvolatile data 0, then will be connected to bit line B andThe complementation it is non-volatile Property memory device is to being respectively maintained at low threshold voltage state V_thLAnd sequencing is to high threshold voltage state V_thH。

After the completion of the Nonvolatile data planning of array 160, when to input data 1 to be operated into line search, apply Voltage V_DDAnd Vss to two bit line B andWhen to input data 0 to be operated into line search, then apply voltage Vss and V_DDTo two Bit line B andFor random position, be apply voltage Vss to two bit line B andAnd the complementary non-volatile memory device is not to having There is forbidden configuration, that is, two complementary non-volatile memory devices are not simultaneously in nonconducting state.Logic Core electrocardio Press the positive voltage V of rail_DDIt is between 0.9V between 1.2V, so in transfer overvoltage V_DDWhen those floating gate non-volatile memories Reading interference will not occur for device.Apply logic core voltage V_DDAnd Vss, to close and be connected those CAM cells respectively PMOSFET devices.As shown in figure 16, to search whether a digital content matches the Nonvolatile digital content planned, according to Digital value applies a succession of comprising multiple 0 and 1 input digital signal to multiple bit lines B (1:N) and(1:n).When a line When CAM cell has multiple non-match bits to generate, on the output node that transmits those complementary non-volatile memory devices pair V_DDTo close the PMOSFET devices that those do not match CAM cell, and then the matched line for the row that electrically disconnects.For digital content The case where all matching or part matching are together with random position, those complementary non-volatile memory devices are to that can transmit V_SSTo lead Lead to the PMOSFET devices 830 of all matching CAM cells of the row.The matched line of the matching row can be electrically connected.

Matched line per a line connects a matching detector, which includes that a PMOSFET devices 161, one are anti- To device 162 and a Data buffer 163.The PMOSFET devices 161, the matched line is grounded to voltage V_SS；Reverser 162 sensing the voltage of the matched line；Data buffer 163 is capturing the matched data of Figure 16 matching detectors left. When the matching enable signal (MtchEnb) on node 165 is equal to voltage V_SS(regard as initial number value 0) and when not being activated, battle array The matching detector of all rows is all disabled in row 160, and all NMOSFET devices 161 are all switched on general in array 160 Wiring voltage ground is to V_SS.As shown in figure 16, when the matching enable signal (MtchEnb) on node 165 becomes voltage V_DDWith into When line search operates, PMOSFET devices 164 are switched on to be electrically connected common source line CSL and then vertically connect the respectively matching The left sibling of line is to positive voltage V_DD.During being operated into line search, those NMOSFET devices 161 are all turned off to avoid those Matching detector generates any DC electric current path by those matched lines.The matching line voltage of non-matching row maintains V_SSWith shape At the matched line electrically interrupted.By the output end of reverser 162, Data buffer 163 captures the non-matched line to non-matching row Voltage V_DD.Therefore, during being operated into line search, the signal for the non-matching row that Data buffer 163 captures is V_DD.Just One is electrically connected for the matching row of matched line completely, and the voltage of matched line and detector input node is charged to from ground voltage Voltage V_DD.When being operated into line search, the signal that the Data buffer 163 of matching row captures is V_SS.Because of an input number The content and non-volatile digital content of a planning matches and the digital data signal that is captured by Data buffer 163, It can be used to connect a data path or triggering execute one group of operational order.

Preferred embodiment provided above is only to illustrate the present invention, and have to limit the present invention to a specific type or The embodiment of demonstration.Therefore, this specification should be regarded as illustrative, and not restrictive.In preferred embodiment provided above, those The kenel of non-volatile RAM device is absorbed in dielectric layer (charge trap including but not limited to floating boom, charge Dielectrics) or nanocrystal (nano-crystals) is as charge stored substance (charge storage Material conventional MOS FET devices)；And those non-volatile RAM devices have " conducting state " with it is " non-conduction State " is to form a complementary pair, as Ovonics unified memory (phase change memory, PCM), programmable metallization are single First (programmable metallization cell, PMC), magnetic random access memory (magneto- Resistive random memories, MRAM), variable resistance type memory (resistive random access Memory, RRAM) and nanometer random access memory (nano-random access memory, NRAM), it is thus evident that it is non- The various modifications of volatile Random Access Memory device or change are obvious to those skilled in the art.It is provided above compared with Good embodiment is to use allowing those skilled in the art to effectively illustrate that the gist of the invention and its optimal mode can practice Various embodiments of the present invention and various changes are solved, to be adapted to specific use or implementation purpose.The scope of the present invention is wanted by right It asks and its equivalent (equivalent) defines, wherein all title (term) all means most rational connotation extensively, remove It is non-separately to specialize.Therefore, the similar term such as " present invention " does not limit the scope of the claims to a particular implementation Example, moreover, any bibliography of the specific preferred embodiment of the present invention is not intended to limit the present invention, and without so Limitation can be deduced.The present invention only scope of the claims and spirit define.The present invention is provided according to the requirement of regulation Abstract, so as to searcher can from this specification check and approve any patent quickly confirm this technology disclose book theme (subject Matter), not it is used for annotating or limiting the scope of the claims and connotation.Any advantage and benefit possibly can not be suitable for this Invent all embodiments.It is to be understood that the sector person can carry out various modifications or change, claim should all be fallen into and determined The scope of the present invention of justice.Furthermore all elements and component (component) in this specification all do not dedicate public meaning to Figure, no matter whether claim enumerates those elements and component.

Claims

1. a kind of non-volatile content can addressing memory, which is characterized in that the non-volatile content can addressing memory packet Contain：

One NOR type matched line nonvolatile memory array, includes multiple NVCAM units, is configured with row and column Circuit configurations, each NVCAM units include a switching transistor；

A plurality of horizontal-extending matched line, each matched line are connected to multiple NVCAM units in a correspondence row；And

Multiple vertically extending bit lines pair and a plurality of vertically extending common source line, each bit line is to being connected in a respective column Multiple NVCAM units, each common source line are connected to multiple NVCAM units in two correspondence adjacent columns；

Wherein, it is divided into multiple unit pairings positioned at multiple NVCAM units of same a line so that the unit pairing of same row is cut The source electrode for changing transistor is joined to form a corresponding common source line, and with the switching transistor of the unit of a line pairing Drain electrode be joined to form a corresponding matched line.

2. non-volatile content according to claim 1 can addressing memory, which is characterized in that each NVCAM units Including：

One first non-volatile memory device and one second non-volatile memory device, first non-volatile memories Device device be located at a conducting state and a nonconducting state first, and second non-volatile memory device be located at institute State the one of conducting state and the nonconducting state.

3. non-volatile content according to claim 2 can addressing memory, which is characterized in that each NVCAM units First non-volatile memory device first end and second non-volatile memory device first end phase It is connected to a gate electrode of itself switching transistor of each NVCAM units, first non-volatile memory device Second end be connected to one first bit line of a correspondence bit line pair and the second end of second non-volatile memory device It is connected to one second bit line of the corresponding bit line pair.

4. non-volatile content according to claim 2 can addressing memory, which is characterized in that when a NVCAM units The state of first non-volatile memory device and second non-volatile memory device matching one corresponds to bit line When complementary to upper a pair binary bit signal, the switching transistor of the NVCAM units is turned off to corresponding matched line The common source line connected from the NVCAM units electrically disconnects；And wherein described first when a NVCAM units is non-volatile Property memory device and the state of second non-volatile memory device mismatch one and correspond to bit line to upper a pair mutually When the binary bit signal of benefit, the switching transistors of the NVCAM units is switched on to be electrically connected corresponding matched line to described The common source line of NVCAM units connection.

5. non-volatile content according to claim 1 can addressing memory, which is characterized in that when each switching transistor is When N-type, a plurality of common source line is connected to a ground terminal；And wherein when each switching transistor be p-type when, it is described a plurality of Common source line is connected to an operation voltage end.

6. non-volatile content according to claim 1 can addressing memory, which is characterized in that the non-volatile content Can addressing memory further include：

Multiple matching detectors, are respectively coupled to a plurality of matched line, and each matching detector generates an output signal, institute Stating output signal tool, there are two logic states first, for representing the matching result of a correspondence matched line；And

One first switch unit, a plurality of common source line is coupled to a first voltage end；

Wherein, the output signal is used for connecting a data path or triggering executes one group of operational order.

7. non-volatile content according to claim 6 can addressing memory, which is characterized in that each matching detector packet Contain：

One second switch unit, the Corresponding matching line is coupled to a second voltage end；

One reverser is connected to second switch unit；And

One buffer is connected to the output end of the reverser, to generate the output signal；

Wherein, when not operated into line search, first switch unit, the reverser and the buffer are disabled, and Second switch unit is enabled；And

Wherein, when being operated into line search, first switch unit, the reverser and the buffer are enabled, and institute The second switch unit is stated to be disabled.

8. non-volatile content according to claim 7 can addressing memory, which is characterized in that when each switching transistor is When N-type, the first voltage end is a ground terminal and the second voltage end is an operation voltage end；And wherein when respectively cutting Change transistor be p-type when, the first voltage end is an operation voltage end and the second voltage end is a ground terminal.

9. a kind of non-volatile content can addressing memory, which is characterized in that the non-volatile content can addressing memory packet Contain：

One NAND type matched line nonvolatile memory array, includes multiple NVCAM units, is configured as row and column Multiple NAND string row, each NVCAM units include a switching transistor；

A plurality of horizontal-extending matched line, each matched line correspond to multiple concatenated switching transistors during NAND string arranges by one It is formed；

Multiple vertically extending bit lines pair, each bit line is to multiple NVCAM units for being connected in a respective column；And

One vertically extending common source line, to connect the same side endpoint of a plurality of matched line to a predeterminated voltage end.

10. non-volatile content according to claim 9 can addressing memory, which is characterized in that each NVCAM units Including：

11. non-volatile content according to claim 10 can addressing memory, which is characterized in that each NVCAM is mono- The first end of first non-volatile memory device of member and the first end of second non-volatile memory device One gate electrode of connected itself switching transistor for being connected to each NVCAM units, the first nonvolatile memory dress The second end set be connected to a correspondence bit line pair one first bit line and second non-volatile memory device second End is connected to one second bit line of the corresponding bit line pair.

12. non-volatile content according to claim 10 can addressing memory, which is characterized in that when a NVCAM units First non-volatile memory device and second non-volatile memory device state matching one correspond to position When the line binary bit signal complementary to upper a pair, the switching transistors of the NVCAM units is switched on by corresponding matching Line is electrically connected to the common source line；And wherein when a NVCAM units first non-volatile memory device and When the state of second non-volatile memory device mismatches the correspondence bit line binary bit signal complementary to upper a pair, The switching transistor of the NVCAM units is turned off to electrically disconnect corresponding matched line from the common source line.

13. non-volatile content according to claim 9 can addressing memory, which is characterized in that when each switching transistor For N-type when, the predeterminated voltage end be a ground terminal；And wherein when each switching transistor be p-type when, the predeterminated voltage End is an operation voltage end.

14. non-volatile content according to claim 9 can addressing memory, which is characterized in that it is described it is non-volatile in Hold can addressing memory further include：

One first switch unit, the common source line is coupled to a first voltage end；

15. non-volatile content according to claim 14 can addressing memory, which is characterized in that each matching detector packet Contain：

One reverser is connected to second switch unit；And

16. non-volatile content according to claim 15 can addressing memory, which is characterized in that when each switching transistor For N-type when, the first voltage end is a ground terminal and the second voltage end is an operation voltage end；And wherein when each When switching transistor is p-type, the first voltage end is an operation voltage end and the second voltage end is a ground terminal.

17. a kind of non-volatile content can addressing memory operating method, which is characterized in that the non-volatile content can be determined Location memory includes a NOR type matched line nonvolatile memory array, the NOR type matched line nonvolatile memory array Include multiple NVCAM units, be configured with the circuit configurations of row and column, each NVCAM units include that a switching is brilliant Body pipe, the operating method comprise the steps of：

A plurality of matched line is coupled to the first voltage end for carrying a first voltage, each matched line horizontal extension and is connected to One corresponds to multiple NVCAM units in row；

After the step of a plurality of matched line of coupling is to the first voltage end for carrying a first voltage, carries out one and search fortune Make, the one the of one second voltage of carrying is coupled in multiple bit lines pair and by a plurality of common source line by applying an input data string Two voltage ends, each bit line is to extending vertically and being connected to multiple NVCAM units in a respective column, each common source line It extends vertically and is connected to multiple NVCAM units in two correspondence adjacent columns, wherein be located at multiple NVCAM units with a line It is divided into multiple unit pairings so that the source electrode of the switching transistor of the unit pairing of same row is joined to form a pair The common source line answered, and the drain electrode with the switching transistor of the unit of a line pairing is joined to form a corresponding matching Line；And

If the input data string mismatches the serial data stored by multiple NVCAM units in a line, conducting at least a pair should be cut It is otherwise to close all corresponding switching transistors equal to the second voltage that transistor, which is changed, with the voltage for changing a correspondence matched line To maintain the voltage of the Corresponding matching line for the first voltage.

18. operating method according to claim 17, which is characterized in that answer switching transistor in conducting at least a pair to change Become after the step of voltage of a correspondence matched line is equal to the second voltage, the operating method further includes：

According to the voltage level of a plurality of matched line, multiple output signals are generated；And

Apply the multiple output signal and executes one group of operational order to connect a data path or triggering；

Wherein, there are two logic states first, to represent the matching result of a correspondence matched line for each output signal tool.

19. operating method according to claim 18, which is characterized in that the step of generating multiple output signals include：

Respectively by the voltage level of a plurality of matched line reversely to generate the multiple output signal；And

The multiple output signal is stored in multiple buffers.

20. operating method according to claim 17, which is characterized in that when each switching transistor is N-type, described first Voltage is an operation voltage and the second voltage end is a ground voltage；And wherein when each switching transistor be p-type when, The first voltage is a ground voltage and the second voltage is an operation voltage.

21. operating method according to claim 17, which is characterized in that each NVCAM units include：

22. operating method according to claim 21, which is characterized in that the input data string is included in the multiple position Line is to the serial data stored by multiple NVCAM units in upper multipair complementary binary bit signal and a line comprising more in a line The one of the state of a first non-volatile memory device and multiple second non-volatile memory devices is specific Combination, and if the wherein described input data string mismatch the serial data in a line stored by multiple NVCAM units, conducting is at least One correspondence switching transistor is otherwise to close all correspondences equal to the second voltage and cut with the voltage for changing a correspondence matched line Transistor is changed to include the step of maintaining the voltage of the Corresponding matching line to be the first voltage：

When first non-volatile memory device of a NVCAM units and second nonvolatile memory in a line When the state matching one of device corresponds to bit line to upper a pair of complementation binary bit signal, the switching of the NVCAM units is closed Transistor is electrically disconnected with the common source line for connecting the Corresponding matching line from the NVCAM units, otherwise described in conducting The Corresponding matching line to be electrically connected to the common source of the NVCAM units connection by the switching transistor of one NVCAM units Line.

23. operating method according to claim 21, which is characterized in that coupling a plurality of matched line to one first electricity of carrying Before the step of one first voltage end of pressure, the operating method further includes：

Multiple serial datas are stored among the multirow of the NOR type matched line nonvolatile memory array.

24. operating method according to claim 23, which is characterized in that store multiple serial datas and matched in the NOR type The step of among the multirow of line nonvolatile memory array includes：

According to corresponding serial data, respectively by the first non-volatile memory device of multiple NVCAM units in each row and Two non-volatile memory device sequencing are to corresponding state.

25. a kind of non-volatile content can addressing memory operating method, which is characterized in that the non-volatile content can be determined Location memory includes a NAND type matched line nonvolatile memory array, the NAND type matched line nonvolatile memory battle array Row include multiple NVCAM units, are configured as multiple NAND strings row of row and column, and each NVCAM units include all Transistor is changed, the operating method comprises the steps of：

A plurality of matched line is coupled to the first voltage end for carrying a first voltage, each matched line horizontal extension and by a pair Multiple concatenated switching transistors in answering NAND string to arrange are formed；

After the step of coupling a first voltage end of a plurality of matched line to one first voltage of carrying, carries out one and search fortune Make, the one second of one second voltage of carrying is coupled in multiple bit lines pair and by a common source line by one input data string of application Voltage end, to multiple NVCAM units for being connected in a respective column, the common source line is extended vertically to connect each bit line The same side endpoint of a plurality of matched line is to the second voltage end；And

If the input data string mismatches the stored serial data of NAND string row, at least a pair of of the NAND string row is closed Switching transistor is answered to maintain the voltage for corresponding to the matched line for the first voltage, the institute of the NAND string row is otherwise connected It is equal to the second voltage to have corresponding switching transistor with the voltage for changing the Corresponding matching line.

26. operating method according to claim 25, which is characterized in that corresponded in close the NAND string row at least one After the step of switching transistor is to maintain the voltage of the Corresponding matching line to be the first voltage, the operating method is more wrapped Contain：

27. operating method according to claim 26, which is characterized in that the step of generating multiple output signals include：

The multiple output signal is stored in multiple buffers.

28. operating method according to claim 25, which is characterized in that when each switching transistor is N-type, described first Voltage is an operation voltage and the second voltage is a ground voltage；And wherein when each switching transistor be p-type when, institute State that first voltage is a ground voltage and the second voltage is an operation voltage.

29. operating method according to claim 25, which is characterized in that each NVCAM units include：

30. operating method according to claim 29, which is characterized in that the input data string is included in the multiple position The line serial data stored to upper multipair complementary binary bit signal and NAND string row includes multiple in NAND string row One specific combination of the state of the first non-volatile memory device and multiple second non-volatile memory devices, Yi Jiqi The input data string mismatches the stored serial data of NAND string row in if, and close the NAND string row at least one corresponds to Otherwise all of the NAND string row are connected to maintain the voltage of the Corresponding matching line for the first voltage in switching transistor Corresponding switching transistor is to include equal to the step of second voltage with the voltage for changing the Corresponding matching line：

When first non-volatile memory device of a NVCAM units in NAND string row and described second non-volatile Property memory device state when mismatching one and corresponding to bit line to the complementary binary bit signal of upper a pair, close a NVCAM Otherwise the switching transistor of the NVCAM units is connected in the switching transistor of unit.

31. operating method according to claim 29, which is characterized in that coupling a plurality of matched line to carrying 1 the Before the step of one first voltage end of one voltage, the operating method further includes：

Multiple serial datas are stored among the multirow of the NAND type matched line nonvolatile memory array.

32. operating method according to claim 31, which is characterized in that store multiple serial datas and matched in the NAND type The step of among the multirow of line nonvolatile memory array includes：