CN105654987A - SONOS (silicon-oxide-nitride-oxide-silicon) structural EEPROM (electrically erasable programmable read-only memory) and memory array and operation method thereof, and SONOS device - Google Patents
SONOS (silicon-oxide-nitride-oxide-silicon) structural EEPROM (electrically erasable programmable read-only memory) and memory array and operation method thereof, and SONOS device Download PDFInfo
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
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Abstract
The invention relates to a memory array of an SONOS (silicon-oxide-nitride-oxide-silicon) structural EEPROM (electrically erasable programmable read-only memory), an SONOS structural EEPROM, a method of operation in the SONOS structural EEPROM, and an SONOS device, wherein the memory array comprises multiple byte storage units, each comprising 8 bit storage units; each bit storage unit comprises a first storage subunit and a second storage subunit for storing two opposite pieces of information, respectively, wherein the first and second storage subunits are adjacently arranged and equal in structure and size and are connected to respective bit lines, respectively. By implementing the invention, it is possible to use an SONOS process storage unit (normally less than 1/5 of a common floating gate structural EEPROM storage unit) and effectively saves chip area; it is possible to shorten erase/write time, and programing time is close to that of the floating gate structural EEPROM. Therefore, chip area and cost can be greatly reduced at the premise of a substantial approximation to the floating gate type EEPROM in terms of performance.
Description
Technical field
The present invention relates to EEPROM nonvolatile memory, more particularly, it relates to the memory array of a kind of SONOS structure EEPROM, SONOS structure EEPROM, the method being operated in SONOS structure EEPROM and SONOS device.
Background technology
Nonvolatile memory (Non-volatileMemory) does not lose at once remaining to maintenance data message in system cut out or non-transformer, and this chip is used for storing data or program, applies extremely extensive. Especially electric erasable programmable memory device, it is possible to repeatedly erasable more new data, is very important storage chip in current consumption electron-like even military project series products.
Non-volatile programmable memory can be divided into again two big classes: floating gate type and electric charge well-type. In floating gate type memory, electric charge is stored in floating boom, even if power failure data also can be maintained, a kind of representative applications of floating gate type device is exactly EEPROM (ElectricallyErasableandProgrammableReadOnlyMemory). Floating gate type EEPROM is made up of two transistors, and one is floating transistor, and one is select transistor. By adding suitable high pressure generation tunnel-effect in programming process, inject charge among floating boom. In electric charge well-type device, electric charge is stored among the nitrogen trap of separation, also can keep data when without electricity. A kind of typical case's application of electric charge well-type device is SONOS (SiliconOxideNitrideOxideSemiconductor), is also by adding high pressure generation tunnel-effect, injecting charge among nitrogen layer.
Above two non-volatile programmable memory, is respectively arranged with quality. It is summarized as follows: a) floating gate type structure is it is necessary to have floating gate layer, it is necessary to use the polysilicon process of at least 2 layers, technique relative complex;B) owing to floating boom result in higher Capacitance Coupled, wiping/write operation needs higher voltage, if memory cell size constantly diminishes, over-erasure and write can cause that unusual leakage current is existing increasingly severe, so memory element constantly can not be evolved to deep-submicron along with production technology and constantly diminish; C) floating-gate device stores a charge in floating gate layer, and floating boom is conductor, and any needle pore defect therein all can cause short circuit between floating boom and raceway groove, causes part or all of electric charge to lose. And in SONOS device, storage electric charge is insulator oxide silicon, the total amount of electric charge impact of storage can be ignored by needle pore defect; D) problem of SONOS memorizer is that wiping/writing rate is not high, and owing to memory element chi is very little, the ability of its draw current very weak, once there is leakage problem at a certain reading branch road of circuit, all can have a strong impact on the storage of data.
Due to floating gate type and the respective feature of electric charge well-type memorizer and Problems existing, way conventional at present is:
1) floating gate type device is usually used in producing EEPROM, is mainly used in some amount of storage little, to wiping/write number of times and fast place; Electric charge well-type SONOS is usually used in Flash chip, big for amount of storage, to wiping/write number of times and the not high place of rate request;
2) at material, the memory element of SONOS device is updated by the aspect such as technique and structural design;
3) it is insulating barrier owing to SONOS device stores charge layer, its anticreeping power and prevent from radiating much stronger than the EEPROM of FGS floating gate structure. Consider in the special applications such as space product, cost insignificant Consideration, combine the SONOS structure EEPROM that two class technological merits design and also begin to be devised and be applied in some special occasions.
The circuit design block diagram of conventional serial line interface SONOS structure EEPROM is as shown in Figure 1. Memory element adopts and is operated for minimum selection unit with byte, and every byte packet is containing the binary data of 8 bits. A large amount of memory arrays bitwise constitute memory element 101, and a byte is chosen after being decoded by X-direction and Y-direction in address every time, and byte chooses module to be 102. Among Serial output, the data of 8 bit storage must again pass by parallel-serial conversion selection circuit 103, and the information wherein stored, again through sense amplifier 104, is forwarded into binary data by the bit information chosen. When needs store data, each bit lines needs a latch, and latch arrays is 105. The circuit part that the present invention relates to includes 101-105, its information transfer circuit figure specifically is as shown in Figure 2, the circuit of 201-205 corresponding block diagram 101-105 respectively embodies: among memory array 201, each minimum operating unit is a byte, including 8 bit memory cell 2011 in each byte storage unit 2012, each bit memory cell 2011 is made up of two devices. The corresponding position of every bit lines BLX selects switch 2021, corresponding 8 the selection switches 202 of every 8 bit lines. Storage array has how many bit lines namely to have how many positions selection switches 2021. When each bit line needs write data, data need first to latch to enter data latches 2051, equally, have how many bit lines namely to need how many latch units 2051. All of bit line selects unit to need bit cell Serial output correspondence chosen through the circuit 203 being made up of 8 output devices 2031 when output, and whole circuit needs one group 203.The final unit selected, through a sensitive operational amplifier 204, converts the data into binary data.
Fig. 2 show the custom circuit of existing SONOS structure EEPROM, is only used at present the less demanding application scenario of chip cost and access time. Its essence reason is: even if adopting advanced manufacturing process, the memory element 2011 of restriction chip cost can not be sized too small. As it is shown on figure 3, the threshold voltage after the erasing of memory element and write is before saturation, its logarithm with the time is substantially linear. The charge information comprised inside memory element, after a series of path transmission, finally enters to sensitive operational amplifier 204, and cell current Icell is compared with reference current Iref two. If storage content is " 1 ", then Icell is substantially close to for 0; If storage content is " 0 ", Icell > Iref. So the size of Icell is extremely important. In memory circuitry, the wiping of each bit memory cell 2011/write first to wipe becomes " 1 ", decides whether write " 0 " according still further to demand. Current formula according to device: I=1/2K*W/L* (Vgs-Vth)2(wherein, K is dielectric constant, W/L is the breadth length ratio of memory element, Vgs is voltage difference between device gate source, and Vth is device threshold voltage) it can be seen that electric current is relevant to the size of device and threshold voltage, device size is relevant to technique, threshold voltage and wiping/write time correlation, and increase (EEPROM generally requires 1,000,000 times) along with what wipe/write number of times, threshold voltage can taper into. The information of storage element is delivered to sensitive amplifier, it is necessary to through multiple devices and very long path, and device therebetween is likely to itself there is also certain electric leakage, also likely to be present the interference of noise in path. Want the correctness guaranteeing stored contents, it is necessary at the memory element drop-down sufficiently large electric current of energy, namely need enough large-sized memory element and long programming time. These 2 key factors that restriction SONOS structure EEPROM cannot use in consumer electronics on a large scale just.
In field of consumer electronics, to the unusual height of the requirement of cost i.e. chip size. In summary, although traditional SONOS structure EEPROM has very strong anti-interference and capability of resistance to radiation, it also is able to be operated with byte (byte) for unit, but, under the premise having taken into account SONOS device and floating gate type EEPROM advantage, it must adopt very big memory element, and needs long very slowly wiping/write the time, can be used only in the special occasions that cost requirement is not high, be difficult to large batch of being used in the consumer electronics product that demand is maximum.
Therefore, it is badly in need of in the industry a kind of there is small size memory element and wipe/write time short SONOS structure EEPROM.
Summary of the invention
The technical problem to be solved in the present invention is in that, need adopt large scale memory element and wipe/write the defect of time length (namely wiping/writing rate is low) for traditional SONOS structure EEPROM, the memory array of a kind of SONOS structure EEPROM, SONOS structure EEPROM and the method being operated in SONOS structure EEPROM are provided.
The technical solution adopted for the present invention to solve the technical problems is: construct the memory array of a kind of SONOS structure EEPROM, and including multiple byte storage units, wherein each byte storage unit includes 8 bit memory cell; Wherein,
Each described bit memory cell includes the first storing sub-units for storing one of two contrary information respectively and the second storing sub-units;And
Described first storing sub-units and the second storing sub-units is adjacently positioned and structure and equivalently-sized;
Described first storing sub-units and the second storing sub-units are connected to respective bit line.
In the memory array of SONOS structure EEPROM of the present invention,
Described first storing sub-units and the second storing sub-units each include the memory device and the wordline selector part that are serially connected.
In the memory array of SONOS structure EEPROM of the present invention, in each described byte storage unit, the grid of described memory device is connected between two and the grid of described wordline selector part is connected between two.
This invention address that what its technical problem adopted another solution is that a kind of SONOS structure EEPROM of structure, memory array including SONOS structure EEPROM as above, the position line options switch corresponding with bit memory cell each described, input data latch and output device, and sensitive operational amplifier; Wherein,
The first storing sub-units in each bit memory cell connects corresponding first line options switch by the first bit line and then is connected to corresponding first output device and input data latch, and the second storing sub-units connects corresponding second line options switch by the second bit line and then is connected to corresponding second output device and input data latch; And
The outfan of the first output device and the second output device is respectively connecting to first input end and second input of described sensitive operational amplifier.
In SONOS structure EEPROM of the present invention, on domain:
Described first bit line and the second bit line are close to layout and structure and equivalently-sized;
Described first line options switch and second line options switch are close to layout and structure and equivalently-sized;
Described first output device and the second output device are close to layout and structure and equivalently-sized; And
Start via the first bit line, first line options switch to the track lengths of described first output device from described first storing sub-units, and start via the second bit line, second line options switch essentially identical to the track lengths of described second output device from described second storing sub-units.
In SONOS structure EEPROM of the present invention, described sensitive operational amplifier includes current mirror and benchmark comparison circuit, wherein:
One input of described current mirror is second input that another input is described sensitive operational amplifier of the described sensitive first input end of operational amplifier, described current mirror; And
One input of described benchmark comparison circuit is connected to the outfan of described current mirror, another input termination reference voltage of described benchmark comparison circuit; The outfan of described benchmark comparison circuit is used for exporting data.
In SONOS structure EEPROM of the present invention,
Input data latch comprises and enables described first storing sub-units and phase inverter that the stored information of the second storing sub-units is contrary information, one of first line options switch and second line options switch two outfans being connected to described input data latch altogether;
Or,
Input data latch includes enabling described first storing sub-units and the first input data latch that the stored information of the second storing sub-units is contrary information and the second input data latch; And first line options switch connects the first input data latch, second line options switch connects the second input data latch.
This invention address that the yet another aspect that its technical problem adopts is: provide a kind of method being operated in SONOS structure EEPROM as above, including:
Erasing step: when a bit being carried out erasing set, simultaneously the first storing sub-units and the second storing sub-units are set to high threshold level, or, the first storing sub-units and the second storing sub-units are set to low-threshold-level simultaneously;
Write step: when a bit is read operation, according to being intended to write data and pre-defined rule, bit line high input voltage and low-voltage respectively in the first storing sub-units and the second storing sub-units, or low-voltage and high voltage, the threshold level making one of them storing sub-units remains unchanged, and the thresholding of another storing sub-units changes over another state.
In the method being operated in SONOS structure EEPROM of the present invention, also include:
Read step: when a bit is read,
The threshold conditon information of the first storing sub-units is sent to the first output device, the threshold conditon information of the second storing sub-units is sent to the second output device;
Second electric current of the first electric current of the first output device output and the output of the second output device is amplified on year-on-year basis through current mirror;
The first electric current after amplification and the second electric current are compared mutually, and by comparative result output to benchmark comparison circuit;
The benchmark comparison circuit comparison output data according to described comparative result with reference voltage.
It addition, the present invention also provides for a kind of SONOS device, it includes multiple memory device for stored bits information, wherein,
Described memory device includes the grid being connected to wordline (WLS) and the source electrode and the drain electrode that are respectively used to store one of two contrary information;
Described SONOS device also includes:
The position line options switch corresponding with described memory device, input data latch and output device, and sensitive operational amplifier; Wherein,
The source electrode of each memory device connects corresponding first line options switch by the first bit line and then is connected to corresponding first output device and input data latch, and the drain electrode of each memory device connects corresponding second line options switch by the second bit line and then is connected to corresponding second output device and input data latch; And
The outfan of the first output device and the second output device is respectively connecting to first input end and second input of described sensitive operational amplifier.
Implement the method have the advantages that SONOS structure EEPROM and the memory array thereof of the present invention, it is possible to use very undersized SONOS technique memory element (is typically less than the 1/5 of common FGS floating gate structure EEPROM memory cell), effective saving chip area; Can shorten and wipe/write required time, close to FGS floating gate structure EEPROM on programming time. Thus, in performance substantially close under the premise of floating gate type EEPROM, chip area with become instinct and significantly reduced.
It addition, can effectively prevent storage element from reading electric leakage and the noise jamming of branch road device. Even if when reading branch road and there is certain electric leakage, also can normally read storage data.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the structural representation of existing SONOS structure EEPROM;
Fig. 2 is the circuit theory diagrams of existing SONOS structure EEPROM;
Fig. 3 is the curve chart of EEPROM storage element threshold voltage and programming time relation;
Fig. 4 is the circuit theory diagrams of SONOS structure EEPROM of the present invention.
Detailed description of the invention
The circuit design of a kind of brand-new difference coupling SONOS structure EEPROM device of present inventive concept. Adopt this circuit design, it is possible to use only small SONOS technique memory element (being typically less than the 1/5 of common FGS floating gate structure EEPROM memory cell) is saving chip area effectively;Can shorten and wipe/write required time, close to FGS floating gate structure EEPROM on programming time. It addition, can effectively prevent storage element from reading electric leakage and the noise jamming of branch road device.
The SONOS structure EEPROM of the present invention and memory array thereof, both the very little memory element (its size is typically less than the 1/5 of conventional floating gate type EEPROM memory cell) that more advanced deep sub-micron technique manufactures can have been used, it is also possible to wiping/writing rate is greatly improved, shortens and wipe/write required time and can improve and wipe/write number of times. In performance substantially close under the premise of floating gate type EEPROM, chip area with become instinct and significantly reduced.
As shown in Figure 4, the SONOS structure EEPROM of the present invention includes EEPROM memory array 1, bit line select circuitry 2, parallel-serial conversion data output circuit 3, sensitive operational amplifier 4 and input data-latching circuit. Wherein,
EEPROM memory array 1 is the memory array of SONOS structure EEPROM, and it includes multiple byte storage unit 10. Each byte storage unit 10 farther includes 8 bit memory cell 10i (i=0,1,2 ... 7).
Bit line select circuitry 2 includes 16 position line options switch 2i_a, 2i_b (i=0,1,2 ... 7).
Parallel-serial conversion data output circuit 3 includes 16 output devices 3i_a, 3i_b (i=0,1,2 ... 7).
Sensitive operational amplifier 4 includes current mirror and benchmark comparison circuit.
Input data-latching circuit includes 8 input data latch 5i (i=0,1,2 ... 7), wherein with phase inverter, two contrary outputs can be drawn respectively to the first storing sub-units 10i_a and the second storing sub-units 10i_b, enable the first storing sub-units 10i_a and the stored information of the second storing sub-units 10i_b is contrary information. Each input data latch 5i has an input and two outfans, first line options switch 2i_a and second line options switch one of 2i_b two outfans being connected to this input data latch 5i altogether. In another embodiment of the invention, input data latch includes enabling the first storing sub-units 10i_a and the first input data latch that the stored information of the second storing sub-units 10i_b is contrary information and the second input data latch. In this embodiment, first line options switch 2i_a connects the first input data latch, and second line options switch 2i_b connects the second input data latch.
Further, in each byte storage unit 10 of EEPROM memory array 1, each bit memory cell 10i includes the first storing sub-units 10i_a and the second storing sub-units 10i_b (so, each byte storage unit 10 includes 16 storing sub-units), it is respectively used to two contrary information of storage, such as when the first storing sub-units 10i_a is stored as the 0, then second storing sub-units 10i_b storage 1, vice versa. On domain, the first storing sub-units 10i_a and the second storing sub-units 10i_b is adjacently positioned and structure and equivalently-sized.
Each storing sub-units connects with corresponding bit line. Such as, the first storing sub-units 10i_a is connected to bit line BLi_a (i=0,1,2 ... 7), the second storing sub-units 10i_b is connected to bit line BLi_b (i=0,1,2 ... 7).
In an embodiment of the present invention, the first storing sub-units 10i_a and the second storing sub-units 10i_b each includes an a memory device Q1 and wordline selector part Q2, and memory device Q1 and wordline selector part Q2 is serially connected.For each bit memory cell 10i, the grid of two memory device Q1 therein is connected, and the grid of two wordline selector part Q2 is connected.
In each byte storage unit 10, the grid of whole 16 memory device Q1 is connected between two and the grid of whole 16 wordline selector part Q2 is connected between two.
Below, for i-th bit memory cell 10i, the annexation of various piece is described.
As shown in Figure 4, the first storing sub-units 10i_a in each bit memory cell 10i connects corresponding first line options switch 2i_a by the first bit line BLi_a and then is connected to corresponding first output device 3i_a and input data latch 5i, the second storing sub-units 10i_b and connects corresponding second line options switch 2i_b and then be connected to corresponding second output device 3i_b and input data latch 5i by the second bit line BLi_b. The outfan of the first output device 3i_a and the second output device 3i_b is respectively connecting to first input end and second input of sensitive operational amplifier 4.
In some embodiments of the invention, SONOS structure EEPROM is on domain:
First bit line BLi_a and the second bit line BLi_b is close to layout and structure and equivalently-sized;
First line options switch 2i_a and second line options switch 2i_b is close to layout and structure and equivalently-sized;
First output device 3i_a and the second output device 3i_b is close to layout and structure and equivalently-sized; And
The track lengths via the first bit line BLi_a, first line options switch 2i_a to first output device 3i_a is started from the first storing sub-units 10i_a, essentially identical with starting the track lengths via the second bit line BLi_b, second line options switch 2i_b to second output device 3i_b from the second storing sub-units 10i_b.
As shown in Figure 4, sensitive operational amplifier 4 includes current mirror and benchmark comparison circuit, and wherein an input of current mirror is second input that another input is sensitive operational amplifier 4 of the sensitive first input end of operational amplifier 4, current mirror; And an input of benchmark comparison circuit is connected to the outfan of current mirror, another input termination reference voltage of benchmark comparison circuit; The outfan of benchmark comparison circuit is used for exporting data.
The SONOS structure EEPROM of the present invention in operation, passes through to read branch road when reading data: information is transmitted to sensitive operational amplifier 4 from the first storing sub-units 10i_a, the first bit line BLi_a, first line options switch 2i_a, the first output device 3i_a; Transmit to sensitive operational amplifier 4 from the second storing sub-units 10i_b, the second bit line BLi_b, second line options switch 2i_b, the second output device 3i_b.
By writing branch road during write data: information is transmitted to the first storing sub-units 10i_a from input data latch 5i, first line options switch 2i_a, the first bit line BLi_a; Transmit to the second storing sub-units 10i_b from input data latch 5i, second line options switch 2i_b, the second bit line BLi_b.
In various embodiments of the present invention, the method being operated in SONOS structure EEPROM includes:
Erasing step: when a bit being carried out erasing set, first storing sub-units 10i_a and the second storing sub-units 10i_b is set to high threshold level simultaneously, or, the first storing sub-units 10i_a and the second storing sub-units 10i_b is set to low-threshold-level simultaneously;
Write step: when a bit is read operation, according to being intended to into writing data and pre-defined rule, different voltage is inputted respectively at bit line BLi_a, BLi_b of the first storing sub-units 10i_a and the second storing sub-units 10i_b, such as high voltage and low-voltage or low-voltage and high voltage, the threshold voltage making one of them storing sub-units remains unchanged, and the thresholding of another storing sub-units changes over another state. Such as, being intended to write data is 0 or 1. Pre-defined rule may is that 1) the first storing sub-units 10i_a sets low threshold level, the second storing sub-units 10i_b be set to this bit memory cell of high threshold level interval scale storage be 1; 2) the first storing sub-units 10i_a set high threshold level, the second storing sub-units 10i_b be set to this bit memory cell of low-threshold-level interval scale storage be 0. Or contrary: 1) the first storing sub-units 10i_a sets high threshold level, the second storing sub-units 10i_b is set to the storage of this bit memory cell of low-threshold-level interval scale is 1; 2) the first storing sub-units 10i_a set low threshold level, the second storing sub-units 10i_b be set to this bit memory cell of high threshold level interval scale storage be 0.
Read step: when a bit is read,
The threshold conditon information of the first storing sub-units 10i_a is sent to the first output device 3i_a, the threshold conditon information of the second storing sub-units 10i_b is sent to the second output device 3i_b;
Second electric current Icell_b of the first electric current Icell_a and the second output device 3i_b output of the first output device 3i_a output is amplified on year-on-year basis through current mirror;
The first electric current Icell_a after amplification and the second electric current Icell_b is compared mutually, and by comparative result output to benchmark comparison circuit;
The benchmark comparison circuit comparison output data according to this comparative result with reference voltage.
The present invention also provides for a kind of SONOS device, and it includes multiple memory device for stored bits information. This memory device includes the grid being connected to wordline WLS and the source electrode and the drain electrode that are respectively used to store one of two contrary information; And the position line options switch 2i_a corresponding with this memory device, 2i_b, input data latch 5i and output device 3i_a, 3i_b, and sensitive operational amplifier 4; Wherein,
The source electrode of each memory device connects corresponding first line options switch 2i_a by the first bit line BLi_a and then is connected to corresponding first output device 3i_a and input data latch 5i, and the drain electrode of each memory device connects corresponding second line options switch 2i_b by the second bit line BLi_b and then is connected to corresponding second output device 3i_b and input data latch 5i; And
The outfan of the first output device 3i_a and the second output device 3i_b is respectively connecting to first input end and second input of sensitive operational amplifier 4.
In this SONOS device, except with above-mentioned memory device source electrode and drain electrode alternate figures 4 in bit memory cell 10i in two storing sub-units 10i_a, 10i_b outside, other parts such as bit line select circuitry, parallel-serial conversion data output circuit, sensitive operational amplifier and input data-latching circuit all can adopt the bit line select circuitry 2 in Fig. 4, parallel-serial conversion data output circuit 3, sensitive operational amplifier 4, input data-latching circuit, and domain therein is arranged and connection also can follow.
Generally, the data programming of EEPROM first has to be set to " 1 " through erasing, namely shown in Fig. 3, by adding high pressure, memory element threshold voltage is become high level, in sensitive amplifier, it is impossible to have the ability of pull-down current, i.e. Icell=0. Then writing further according to needs, if wanting write data is " 1 ", then this bit will not add high pressure change thresholding, otherwise can add high pressure and thresholding is become low level, and Icell is more than reference current.
In the present invention, will carrying out data programming, first erasing is set to " 1 ", is added in Fig. 4 by high pressure selected byte storage unit 10, then 16 memory element are simultaneously disposable is erased into " 1 ". When write, bit line BLi_a and BLi_b is just contrary, such as: write data is 0, then bit line BLi_a is high level, bit line BLi_b is low level, first storing sub-units 10i_a and the second storing sub-units 10i_b is stored in two antipodal information, namely a thresholding is just, one is negative. When reading, the reading through parallel-serial conversion data output circuit 3 selects, and by the one group of output between two of data in 16 storing sub-units, namely output device 3i_a and 3i_b constitutes one group. Its data are finally passed in sensitive operational amplifier 4, and through the conversion of current mirror, two electric current Icell_a and Icell_b compare mutually. Comparing different with reference current with electric current Icell in traditional structure chart 2, in the present invention, ideally, always having one in electric current Icell_a and Icell_b is 0, also allows for when the electric current of memory element is less, and data remain able to be read out. And being 0 owing to wherein must there be data, two electric currents can amplify with multiple. Several advantage being implemented: one to allow for memory device smaller, two is that the threshold voltage needed can be less, and namely programming required time can be faster. Although number of devices is the twice of traditional approach, but owing to the size of each device can be greatly reduced, still there is very high cost advantage. Additionally, as previously mentioned, in the enforcement of domain, first storing sub-units 10i_a and the second storing sub-units 10i_b, first line options switch 2i_a and second line options switch 2i_b, the first output device 3i_a and the second output device 3i_b are next-door neighbour and place, the length of cabling and the interference received also are just the same, in the amplifier amplifier of the differential configuration 404, all of electric leakage, the unconventional factor such as interference can be cancelled completely. This allows for memory element and can have less electric current.
The important innovations point of SONOS structure EEPROM of the present invention is as follows:
1) constitute in the bit memory cell of storage array, two sizes and completely identical in structure storing sub-units constitute a bit. It is placed on adjacent place on domain is implemented.
2) in a byte storage unit, the grid of memory device Q1 is connected between two, the grid of wordline selector part Q2 is connected between two, operationally simultaneously selected. 8 groups of such storing sub-units constitute a byte, and namely 1 byte packet contains 16 traditional memory element.
3) bit is when wiping set, is set to into a certain threshold level simultaneously. When write, the bit line of two unit is input into two one high and one low voltages, and the threshold voltage of one of them is substantially without change, and another thresholding is changed to another state.
4) position line options switch is connected with respective bit line, in the same size on device size, and at domain is adjacent enforcement.
5) two unit constituting a bit can adopt same data latches. Alternatively, it would however also be possible to employ two latch, also in protection scope of the present invention.
6) 16 parallel datas are converted to 8 groups of antipodal storage information by parallel-serial conversion data output circuit 3, once choose a bit (i.e. one group of data).
7), in sensitive operational amplifier, two groups of electric currents of selected bit mutually compare after circuit conversion.
8) in sensitive operational amplifier, two groups of electric currents can pass through current mirror and amplify on year-on-year basis, and the power that draws of these memory element can be more weak, and also implying that can be less and faster.
Above example only for technology design and the feature of the present invention are described, its object is to allow person skilled in the art will appreciate that present disclosure and to implement accordingly, can not limit the scope of the invention. All equalizations done with the claims in the present invention scope change and modify, and all should belong to the covering scope of the claims in the present invention.
Claims (10)
1. a memory array of SONOS structure EEPROM, including multiple byte storage units (10), wherein each byte storage unit (10) includes 8 bit memory cell (10i);
It is characterized in that, each described bit memory cell (10i) includes the first storing sub-units (10i_a) for storing one of two contrary information respectively and the second storing sub-units (10i_b); And
Described first storing sub-units (10i_a) and the second storing sub-units (10i_b) is adjacently positioned and structure and equivalently-sized;
Described first storing sub-units (10i_a) and the second storing sub-units (10i_b) are connected to respective bit line (BLi_a, BLi_b);
Wherein, i=0,1,2 ... 7.
2. the memory array of SONOS structure EEPROM according to claim 1, it is characterised in that
Wherein, described first storing sub-units (10i_a) and the second storing sub-units (10i_b) each include the memory device (Q1) and the wordline selector part (Q2) that are serially connected.
3. the memory array of SONOS structure EEPROM according to claim 2, it is characterized in that, in each described byte storage unit (10), the grid of described memory device (Q1) is connected between two and the grid of described wordline selector part (Q2) is connected between two.
4. a SONOS structure EEPROM, it is characterized in that, memory array (1) including SONOS structure EEPROM as claimed any one in claims 1 to 3, the position line options switch (2i_a, 2i_b) corresponding with bit memory cell each described (10i), input data latch (5i) and output device (3i_a, 3i_b), and sensitivity operational amplifier (4), i=0,1,2 ... 7; Wherein,
The first storing sub-units (10i_a) in each bit memory cell (10i) connects corresponding first line options switch (2i_a) by the first bit line (BLi_a) and then is connected to corresponding first output device (3i_a) and input data latch (5i), and the second storing sub-units (10i_b) connects corresponding second line options switch (2i_b) by the second bit line (BLi_b) and then is connected to corresponding second output device (3i_b) and input data latch (5i); And
The outfan of the first output device (3i_a) and the second output device (3i_b) is respectively connecting to first input end and second input of described sensitive operational amplifier (4).
5. SONOS structure EEPROM according to claim 4, it is characterised in that on domain:
Described first bit line (BLi_a) and the second bit line (BLi_b) are close to layout and structure and equivalently-sized;
Described first line options switch (2i_a) and second line options switch (2i_b) are close to layout and structure and equivalently-sized;
Described first output device (3i_a) and the second output device (3i_b) are close to layout and structure and equivalently-sized; And
The track lengths via the first bit line (BLi_a), first line options switch (2i_a) extremely described first output device (3i_a) is started from described first storing sub-units (10i_a), essentially identical with starting the track lengths via the second bit line (BLi_b), second line options switch (2i_b) extremely described second output device (3i_b) from described second storing sub-units (10i_b).
6. SONOS structure EEPROM according to claim 5, it is characterised in that described sensitive operational amplifier (4) includes current mirror and benchmark comparison circuit, wherein:
One input of described current mirror is the described sensitive first input end of operational amplifier (4), another input of described current mirror is the second input of described sensitive operational amplifier (4); And
One input of described benchmark comparison circuit is connected to the outfan of described current mirror, another input termination reference voltage of described benchmark comparison circuit; The outfan of described benchmark comparison circuit is used for exporting data.
7. the SONOS structure EEPROM according to any one of claim 4-6, it is characterised in that
Input data latch (5i) comprises and enables one of common (2i_b) two outfans being connected to described input data latch (5i) of described first storing sub-units (10i_a) and phase inverter that the second storing sub-units (10i_b) stored information is contrary information, first line options switch (2i_a) and second line options switch;
Or,
Input data latch includes enabling described first storing sub-units (10i_a) and the first input data latch that the second storing sub-units (10i_b) stored information is contrary information and the second input data latch; And first line options switch (2i_a) connects the first input data latch, second line options switch (2i_b) connects the second input data latch.
8. the method being operated in the SONOS structure EEPROM according to any one of such as claim 4 to 7, it is characterised in that including:
Erasing step: when a bit being carried out erasing set, first storing sub-units (10i_a) and the second storing sub-units (10i_b) are set to high threshold level simultaneously, or, the first storing sub-units (10i_a) and the second storing sub-units (10i_b) are set to low-threshold-level simultaneously;
Write step: when a bit is read operation, according to being intended to write data and pre-defined rule, bit line (BLi_a, BLi_b) high input voltage and low-voltage respectively in the first storing sub-units (10i_a) and the second storing sub-units (10i_b), or low-voltage and high voltage, the threshold level making one of them storing sub-units remains unchanged, and the thresholding of another storing sub-units changes over another state.
9. the method being operated in SONOS structure EEPROM according to claim 8, it is characterised in that including:
Read step: when a bit is read,
The threshold conditon information of the first storing sub-units (10i_a) is sent to the first output device (3i_a), the threshold conditon information of the second storing sub-units (10i_b) is sent to the second output device (3i_b);
The second electric current (Icell_b) that the first electric current (Icell_a) exported by first output device (3i_a) and the second output device (3i_b) export amplifies on year-on-year basis through current mirror;
The first electric current after amplification and the second electric current are compared mutually, and by comparative result output to benchmark comparison circuit;
The benchmark comparison circuit comparison output data according to described comparative result with reference voltage.
10. a SONOS device, it includes multiple memory device for stored bits information, it is characterised in that
Described memory device includes the grid being connected to wordline (WLS) and the source electrode and the drain electrode that are respectively used to store one of two contrary information;
Described SONOS device also includes:
The position line options switch (2i_a, 2i_b) corresponding with described memory device, input data latch (5i) and output device (3i_a, 3i_b), and sensitive operational amplifier (4); Wherein,
The source electrode of each memory device is connected corresponding first line options switch (2i_a) by the first bit line (BLi_a) and then is connected to corresponding first output device (3i_a) and input data latch (5i), and the drain electrode of each memory device connects corresponding second line options switch (2i_b) by the second bit line (BLi_b) and then is connected to corresponding second output device (3i_b) and input data latch (5i); And
The outfan of the first output device (3i_a) and the second output device (3i_b) is respectively connecting to first input end and second input of described sensitive operational amplifier (4).
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