CN106204492B - FPGA-based real-time flat field correction method for area-array camera - Google Patents
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Abstract
The invention provides an optimized real-time flat field correction method of an area array camera based on FPGA (field programmable gate array) by combining the parallel operation characteristics of the FPGA and considering the resource limitation in the FPGA, the block-based operation method is adopted to carry out block operation on a sensor array, and an interpolation algorithm is combined on the basis of block division, so that each point is operated while the resource consumption is reduced. The invention provides possibility for realizing real-time FFC correction algorithm for the lower array camera with high resolution and high frame rate, and provides higher output image quality for the application occasions with high resolution and high frame rate. By using an optimization algorithm, PRNU and vignetting effects are successfully corrected in real time under the requirement of meeting high resolution and high frame rate.
Description
Technical Field
The invention relates to the technical field of image algorithms, in particular to a real-time flat field correction method for an area-array camera based on an FPGA (field programmable gate array).
Background
In a photoelectric imaging system, especially an area-array camera imaging system, an image signal cannot fully reflect an actual target, and the reason mainly includes two aspects: (1) response inconsistencies (also known as PRNU) caused by the CCD or CMOS sensor fabrication process; (2) vignetting effect due to optical diffraction phenomenon and various deviations of the optical system. In order to ensure the image output quality, the acquired original image generally needs to be modified by a Flat Field Correction (FFC) algorithm so as to meet the application requirements. Since PRNU and vignetting effects tend to be non-linear, in FFC algorithms, correction is mainly by multiplication. The FFC algorithm can be summarized in the form: yi ═ Xi ═ ai. Wherein Yi is data after FFC correction, Xi is sensor original output data, and i is a serial number of each pixel, namely each pixel corresponds to an ai element in the correction algorithm. The main difficulty of the FFC algorithm is that on one hand, an ai array with the same size as the image resolution needs to be preserved in advance, and on the other hand, a large number of multiplication operations need to be performed, which causes the real-time FFC algorithm under the high-resolution and high-frame rate to have high requirements on the processing speed and also have large requirements on storage resources.
For small target cameras, such as images on the order of 1 megapixels, the software approach at low frame rates is still marginal. The FFC correction algorithm needs to perform multiplication operation on each pixel point, and for application occasions requiring high frame rate of a high-resolution sensor, the real-time FFC correction algorithm realized by software cannot meet the requirements. For example, the resolution of KAI-47051 produced by ON Semiconductor company reaches 4 thousand 7 million, the conventional software method cannot meet the requirement, and the FFC algorithm implemented by ASIC method has poor flexibility, high cost and low practicability. This has the effect of having to sacrifice image quality for high resolution or high frame rate real-time applications. Under the circumstance, as a popular device at present, an FPGA (programmable gate array) has programmability, on one hand, which avoids the disadvantages of poor flexibility and high cost of an ASIC implementation mode, and on the other hand, a hardware implementation mode also avoids the disadvantage that the speed cannot keep up with the speed of a software implementation mode. However, for the high resolution FFC algorithm, the FPGA has its own disadvantages, that is, the internal resources are limited, and may not meet the requirement of the high resolution image for the storage resources. For example, for KAI-47051, the pixel number is 47.8MB, that is, 47.8MB of storage space is required for storing AI arrays corresponding to an image calculated according to the lowest 8-bit of each pixel; even if the purchase cost of the FPGA is not counted, the FPGA at the highest end at present can hardly meet the requirement. Therefore, the original FFC algorithm needs to be optimized under the condition of ensuring certain output image quality, so that the realization of the real-time FFC algorithm of the area-array camera under the high resolution and high frame rate based on the FPGA becomes possible.
Disclosure of Invention
The invention provides a real-time flat field correction method for an area-array camera based on FPGA (field programmable gate array), which provides possibility for realizing a real-time FFC (fringe field communication) algorithm for an area-array camera with high resolution and high frame rate and provides higher output image quality for high-resolution and high-frame-rate application occasions.
In order to solve the technical problems, the invention adopts the following technical scheme:
an area-array camera real-time flat field correction method based on FPGA comprises the following steps:
1) the sensor effective resolution is set as: horizontal colount, vertical rowcount, dividing the resolution into a plurality of basic blocks according to an NxN matrix, acquiring an image under the actual illumination condition, taking the image mean value of each basic block as input data, and calculating according to an FFC correction algorithm strategy to obtain a normalized ai array as follows:
2) the resolution boundaries are copied, and the extended ai array is:
3) the obtained basic blocks to which the pixel points belong are as follows: [ i ]][j]，
4) For each pixel point of the basic block, calculating to obtain an actual ai value of the pixel point based on a bilinear interpolation algorithm through FFC data of the current basic block and an adjacent basic block and coordinates (x, y) of the current pixel point;
5) equally dividing the current basic block into four quadrants from the center, and selecting ai values participating in operation according to the subordinate quadrants of the pixel points;
6) based on parallel operation of the FPGA, values of four quadrants are calculated simultaneously, a final correction result is obtained through sign bit selection output and combination of conversion from a one-dimensional matrix to a two-dimensional matrix of an ai array, and a conversion formula from the one-dimensional matrix to the two-dimensional matrix of the ai array is as follows:
further, in step 6), 8 pixels are used as a processing unit for parallel operation of the FPGA, and the specific calculation process includes the following steps:
61) calculating a basic block [ i ] [ j ] according to the 8 pixel unit address;
62) reading 9 units of the current basic block and the adjacent basic block from the ai array according to the basic block [ i ] [ j ], and then judging the quadrant of the 8 pixel unit according to y [ bit3] and x [ bit3] values;
63) calculate A, B, C, D, a from the quadrantoAnd a1；
64) The calculator sub-formula: a (N-a)0)*(N-a1)、B*a0*(N-a1)、C*(N-a0)*a1And D a0*a1；
65) The four sub-equations obtained by the above calculation are added to obtain ai _ out, and the ai _ out is shifted to the right by 8 bits to obtain the final result dout (din × ai _ out).
Preferably, in step 61), the basic block [ i ]][j]Is composed of
Wherein y is1The number of rows where the 8-pixel unit is located is N, which is the index number of the 8-pixel unit.
Preferably, in step 62), the 9 units are respectively: ai [ i-1] [ j-1], ai [ i-1] [ j +1], ai [ i ] [ j-1], ai [ i ] [ j +1], ai [ i +1] [ j-1], ai [ i +1] [ j ] and ai [ i +1] [ j +1 ].
Further, in the step 4), the pixel point is in the basic block [ i ]][j]In, calculate ai _ x0And ai _ x1：
Calculate ai _ out:
ai_out＝ai_x0+(ai_x1-ai_x0)/N*(N/2-y％*N)。
preferably, the N value of the basic block is 16-128.
According to the technical scheme, FPGA parallel operation is optimized, the possibility of realizing a real-time FFC correction algorithm for the area-array camera under high resolution and high frame rate is provided, and high output image quality is provided for high resolution and high frame rate application occasions. By using an optimization algorithm, PRNU and vignetting effects are successfully corrected in real time under the requirement of meeting high resolution and high frame rate.
Drawings
FIG. 1 is a schematic diagram of basic block partitioning and quadrant partitioning in the algorithm of the present invention;
FIG. 2 is a diagram illustrating the expansion of the array of boundary pixels ai after basic block segmentation in the algorithm of the present invention;
FIG. 3 is a three-dimensional graph of simulation effect before and after correction of ai algorithm with basic block size of 128x128 in the embodiment;
fig. 4 shows the image contrast before and after correction by the AI algorithm in the example.
Detailed Description
A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
The FFC algorithm is mainly used for correcting response inconsistency and non-ideal errors of the sensor array, and the basic algorithm is as follows: yi is Xi ai, where Yi is the corrected data and Xi is the raw data output by the sensor. Because the resolution of the area-array camera is too high, if the single-point FFC operation is directly performed, an ai array with the same size as the image resolution needs to be maintained, the resource consumption is excessive, the direct implementation in an FPGA is not feasible, and the algorithm needs to be optimized. The optimization aims at reducing the consumption of the algorithm on the storage resources, in order to reduce the requirement on the storage resources, a block-based operation method can be adopted, in the embodiment, a 16 × 16 pixel block is used as a basic unit, the sensor array is subjected to blocking operation, and each point can be operated while the resource consumption is reduced by combining an interpolation algorithm on the basis of blocking.
Using KAI-47051 as an example, with a full resolution of 8880x5392, cut into 555x337 matrices, each matrix corresponding to a basic block of 16x 16. The method comprises the steps of obtaining an image under an actual illumination condition, calculating to obtain a normalized array ai [ yi ] [ xi ] by taking the image mean value of each basic block as input data, enabling an FFC algorithm, calculating to obtain an actual ai coefficient for each pixel point of the actual image according to FFC data of current and adjacent blocks and coordinates of the current pixel point, and calculating based on a bilinear interpolation algorithm. The 4 ai data of each pixel point participating in the operation are from the nearest 4 blocks, namely, the current block is equally divided into 4 quadrants (A/B/C/D) from the center, and the ai parameters participating in the operation are selected according to the pixel subordinate quadrants.
As shown in FIG. 1, the light pixel is the current point, at the top left position of block [ i ] [ j ], i.e., in quadrant A.
First, ai _ x is calculated0And ai _ x1：
Recalculate ai _ out:
ai_out＝ai_x0+(ai_x1-ai_x0)/N*(N/2-y％*N)。
for the boundary pixels, to ensure the consistency of the operation process, the extended ai array is copied, as shown in fig. 2.
Taking the 16 × 16 block as an example, the derivation process is as follows: the sensor effective resolution is set as: horizontal colleunt, vertical rowcount, let ai array completed and boundary replication completed, ai array is represented as:
starting from 0, the array coordinates are (x, y), and starting from 0, it can be deduced that the block to which the pixel belongs is: [ i ]][j]，
Here plus 1 means that the boundary is copied.
Based on parallel operation of FPGA, the values of 4 quadrants are calculated simultaneously, the output is selected through sign bit, and the conversion from ai one-dimensional matrix to two-dimensional matrix is combined
The specific calculation results are as follows:
define x [ b'3] as the 3 rd bit taking x, which counts from 0.
Quadrant A: y [ b'3] ═ 0; x [ b'3] ═ 0
kya＝(8-y％8)；kxa＝(8-x％8)
ai_A＝{ai[i][j]*(16-kxa)*(16-kya)+a[i][j-1]*kxa*(16-kya)
+ai[i-1][j]*(16-kxa)*kya+ai[i-1][j-1]*kxa*kya}＞＞8
Quadrant B: y [ b'3] ═ 0; x [ b'3] ═ 1
kyb＝(8-y％8)；kxb＝x％8
ai_B＝{ai[i][j]*(16-kxb)*(16-kyb)+a[i][j+1]*kxb*(16-kyb)
+ai[i-1][j]*(16-kxb)*kyb+ai[i-1][j+1]*kxb*kyb}＞＞8
Quadrant C: y [ b'3] ═ 1; x [ b'3] ═ 0
kyc＝y％8；kxc＝(8-x％8)
ai_c＝{ai[i][j]*(16-kxc)*(16-kyc)+a[i][j-1]*kxc*(16-kyc)
+ai[i+1][j]*(16-kxc)*kyc+ai[i+1][j-1]*kxc*kyc}＞＞8
Quadrant D: y [ b'3] ═ 1; x [ b'3] ═ 1
kyd＝y％8；kxd＝x％8
ai_D＝{ai[i][j]*(16-kxd)*(16-kyd)+a[i][j+1]*kxd*(16-kyd)
+ai[i+1][j]*(16-kxd)*kyd+ai[i+1][j+1]*kxd*kyd}＞＞8
The final result is: dout Din ai _ X >12, where ai _ X selects ai _ a/ai _ B/ai _ C/ai _ D according to different quadrants.
With 16x16 blocks as basic units, the resource consumption is 0.39% under the single-point FFC algorithm. Based on the limitation of cost or other aspects, under the condition that the model of the FPGA device is selected, that is, under the condition that the amount of available storage resources is certain, the size of the block can be appropriately increased to continuously reduce the requirement on the resources, for example, when the size is increased to 32 × 32 blocks, the consumed resources are reduced to 0.097% under the single-point algorithm. As the basic unit blocks become larger, although the consumed resources are less, the algorithm effect is less ideal, so there is a trade-off between the effect and the resource consumption, which needs to be chosen according to the specific application scenario. From the simulation result of the algorithm in Matlab, the basic block unit still can obtain better effect under the condition of 128 × 128 (as shown in fig. 3), and at this time, the resource consumption is 0.006% under the single-point algorithm, even for 47.8MB high-resolution images, the storage resource consumption is only 2.9KB, and this resource consumption will have no problem for realizing the FFC algorithm in the FPGA.
In the FPGA implementation, the intermediate processing stages all use 8 pixels as a processing unit to increase the parallel efficiency. The FFC algorithm needs to calculate an index number according to a pixel coordinate, and let the pixel coordinate be (x, y), where x is a column number and y is a row number, so that for a unit ai [ i ] [ j ] in the ai array, i is (y/16) +1, and j is (x/16) + 1;
for an 8-pixel unit, y is the same, x is 8z to 8z +7, and z is 0,1,2, …, where the calculated i, j are all the same, i.e. the index numbers of the 8 pixels in a processing unit corresponding to the ai array are all the same.
According to the algorithm idea, each pixel needs to calculate 4 values, which respectively correspond to 4 cases. These 4 values require the use of 9 ai array elements, respectively: ai [ i-1] [ j-1], ai [ i-1] [ j ], ai [ i-1] [ j +1], ai [ i ] [ j-1], ai [ i ] [ j ], ai [ i ] [ j +1], ai [ i +1] [ j-1], ai [ i +1] [ j ] j, and ai [ i +1] [ j +1], for the 4-quadrant condition proposed in the algorithm document, 8 pixels in one processing unit belong to one quadrant at the same time, so that the 8 pixels do not need to be respectively judged, and only the first quadrant needs to be judged.
The judgment of the first pixel can be directly summarized as the judgment of the offset address of one processing unit, for example, if the index of an 8-pixel unit is even (counting from 0), and the pixel index in the unit is 0-7, then x [ bit3] ═ 0 is represented, and if the index of the 8-pixel unit is odd, then the pixel index in the unit is 8-15, then x [ bit3] ═ 1 is represented.
For the judgment of the number of rows, the judgment can be directly carried out by using the row number [3], and each 8-pixel unit is always in the same row.
In summary, for a quadrant cell, such as a 20MB camera, there are 5120 columns in a row, i.e., 640 8 pixel cells, with indices of 0-639. Assuming that the index number of a certain 8-pixel unit is N (N ∈ [0,639]), and the number of rows is y, the ai array index [ i, j ] is i ═ y/16+1, and j ═ N × (8/16 + 1) ═ N/2+ 1; i, j are both represented using 9-bit wide registers.
After [ i, j ] is obtained through calculation, 9 units need to be read from the ai array, the 9 units can be divided into 3 groups, all 3 units in a group are consecutive in address, at this time, the value of j needs to be seen, and as the knowledge that j is N/2+1, N is 0,1,2, …, that is, j is 1,2,3, …, it is impossible to read 3 units in a group at one time, and only a single read is possible, that is, 9 units need to consume 9 clock clocks. The total number of ai array units is 322 × 242 ═ 77924 (a 17-bit register is needed to represent the address), and each unit is 14-bit.
The number of cells in each row of the ai array is 5120/16+ 2-322 (indicated by a 9-bit width register), and the addresses of 9 read-out cells in the ai array (indicated by a 17-bit width register) can be calculated as follows:
(i-1)*322+(j-1)，(i-1)*322+(j)，(i-1)*322+(j+1)
(i)*322+(j-1)，(i)*322+(j)，(i)*322+(j+1)
(i+1)*322+(j-1)，(i+1)*322+(j)，(i+1)*322+(j+1)
since i, j corresponding to the internal 8 pixels are the same for an 8-pixel unit, this means that the ai elements used are the same for 8 pixels, i.e. only 9 ai units need to be read for an 8-pixel unit, and since 8 pixels are also located in the same frame, the same frame values are taken for 8 pixels for final calculation.
The formulas for the other 4 image systems can be unified as:
ai_out＝A*(16-a0)*(16-a1)+B*a0*(16-a1)+C*(16-a0)*a1+D*a0*a1；
a, B, C, D, a therein according to image systemoAnd a1The way of calculation is different.
The specific implementation details are as follows:
1. calculating i, j according to the line number lines _ rd, the 8-pixel unit number cnt _ rd:
i＝lines_rd/16+1,j＝cnt_rd/2+1；
2. calculate ram _ addr from i, j:
(i-1)*322+(j-1),(i)*322+(j-1),(i+1)*322+(j-1)；
3. judging the quadrants of 8 pixel units according to lines _ rd and the cnt _ rd corresponding to 8 pixel units, and acquiring A, B, C, D, a of each unitoAnd a1A value;
4. calculating the units
ai_out＝A*(16-a0)*(16-a1)+B*a0*(16-a1)+C*(16-a0)*a1+D*a0*a1；
5. The calculation final result dout ═ ai _ out) > > 12. Note that 8 pixel cells have different ai _ out values, but 8 pixels within an 8 pixel cell use the same ai _ out, i.e. a 64 pixel value can be output at the same time. The corrective effect is referred to the comparative result of fig. 4.
The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements made to the technical solution of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.
Claims (6)
1. A real-time flat field correction method of an area-array camera based on FPGA is characterized by comprising the following steps:
1) the sensor effective resolution is set as: horizontal, vertical, rowcount, dividing the resolution into a number of basic blocks according to an N × N matrix, acquiring an image under actual lighting conditions, and calculating the resolution of each basic blockTaking the image mean value as input data, and obtaining a normalized ai array by calculation according to an FFC correction algorithm strategy, wherein the normalized ai array is as follows:
2) the resolution boundaries are copied, and the extended ai array is:
3) the obtained basic blocks to which the pixel points belong are as follows: [ i ]][j]，
4) For each pixel point of the basic block, calculating to obtain an actual ai value of the pixel point based on a bilinear interpolation algorithm through FFC data of the current basic block and an adjacent basic block and coordinates (x, y) of the current pixel point;
5) equally dividing the current basic block into four quadrants from the center, and selecting ai values participating in operation according to the subordinate quadrants of the pixel points;
6) based on parallel operation of the FPGA, values of four quadrants are calculated simultaneously, a final correction result is obtained through sign bit selection output and combination of conversion from a one-dimensional matrix to a two-dimensional matrix of an ai array, and a conversion formula from the one-dimensional matrix to the two-dimensional matrix of the ai array is as follows:
2. the real-time flat-field correction method for the area-array camera according to claim 1, wherein in step 6), the parallel operation of the FPGA adopts 8 pixels as a processing unit, and the specific calculation process comprises the following steps:
61) calculating a basic block [ i ] [ j ] according to the 8 pixel unit address;
62) reading 9 units of the current basic block and the adjacent basic block from the ai array according to the basic block [ i ] [ j ], and then judging the quadrant of the 8 pixel unit according to y [ bit3] and x [ bit3] values;
63) calculate A, B, C, D, a from the quadrantoAnd a1；
64) The calculator sub-formula: a (N-a)0)*(N-a1)、B*a0*(N-a1)、C*(N-a0)*a1And D a0*a1；
65) The four sub-equations obtained by the above calculation are added to obtain ai _ out, and the ai _ out is shifted to the right by 8 bits to obtain the final result dout (din × ai _ out).
3. The real-time flat-field correction method for area-array camera according to claim 2, characterized in that in step 61), the basic block [ i ] is][j]Is composed of
Wherein y is1The number of rows where the 8-pixel unit is located is N, which is the index number of the 8-pixel unit.
4. The real-time flat-field correction method for area-array camera according to claim 2, wherein in step 62), the 9 units are respectively: ai [ i-1] [ j-1], ai [ i-1] [ j +1], ai [ i ] [ j-1], ai [ i ] [ j +1], ai [ i +1] [ j-1], ai [ i +1] [ j ] and ai [ i +1] [ j +1 ].
5. The real-time flat-field correction method for area-array camera according to claim 1, characterized in that in step 4), the pixel points are located in the basic block [ i ]][j]In, calculate ai _ x0And ai _ x1：
Calculate ai _ out:
ai_out＝ai_x0+(ai_x1-ai_x0)/N*(N/2-y％*N)。
6. the real-time flat-field correction method for the area-array camera according to claim 1, wherein the N value of the basic block is 16-128.
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