CN106204492A - The area array cameras flat field realized based on FPGA corrects real time algorithm - Google Patents
The area array cameras flat field realized based on FPGA corrects real time algorithm Download PDFInfo
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Abstract
The present invention combines FPGA concurrent operation feature and in view of resource finiteness in FPGA, propose a kind of optimization can correct real time algorithm based on the area array cameras flat field that FPGA realizes, use block-based operation method, sensor array is carried out piecemeal operation, on the basis of piecemeal, combine interpolation algorithm, while reducing resource consumption, click on row operation to each.The present invention is that under high-resolution high frame per second, area array cameras realizes real-time FFC correction algorithm and provides possibility, provides higher output image quality for high-resolution high frame per second application scenario.By using optimized algorithm, under the requirement meeting high-resolution and high frame per second, successfully PRNU and vignetting effect are carried out real-time rectification.
Description
Technical field
The present invention relates to image algorithm technical field, be specifically related to a kind of area array cameras flat field realized based on FPGA and correct
Real time algorithm.
Background technology
In photo electric imaging system, particularly in area array cameras imaging system, picture signal can not react actual mesh completely
Mark, its reason mainly includes two aspects: the response nonuniformity that (1) is caused by CCD or cmos sensor processing technology is (also referred to as
PRNU)；(2) vignetting effect caused due to optical diffraction phenomenon and the various deviation of optical system.For ensureing image output quality,
It is modified it is generally required to the original image collected to be carried out flat field rectification (FFC) algorithm, to reach application requirement.
Owing to PRNU and vignetting effect are the most nonlinear, therefore in FFC algorithm, mainly corrected by multiplying.FFC
Algorithm can be to be summarized as following form: Yi=Xi*ai.Wherein Yi is data after FFC corrects, and Xi is sensor original output number
According to, i is the corresponding ai element of each pixel in the serial number of each pixel, i.e. correction algorithm.FFC algorithm Major Difficulties is
On the one hand need to pre-save one and image resolution ratio an equal amount of ai array, on the other hand need to do substantial amounts of multiplication fortune
Calculate, this cause real-time FFC algorithm under high-resolution high frame per second except processing speed being proposed very in addition to high request, to storage resource
Demand is the biggest.
For little target surface camera, such as the image of 1 mega pixel magnitude, the software mode under low frame per second still can be answered reluctantly
Pay.FFC correction algorithm needs each pixel is carried out multiplying, the application required for high resolution sensor high frame per second
Occasion, uses software to realize real-time FFC algorithm and cannot meet requirement.The KAI-produced such as ON Semiconductor company
47051, its resolution reaches 4,000 7 million, and conventional software mode cannot meet requirement, and uses ASIC mode to realize
The on the one hand motility of FFC algorithm is very poor, and on the other hand cost is the highest, reaches far away practicality requirement.This allows for for high score
Resolution or the real-time application scenario of high frame per second, it has to sacrifice picture quality as cost.In this case, FPGA (can compile
Journey gate array) as the most popular a kind of device, on the one hand its programmability has evaded the flexible of ASIC implementation
The shortcoming of property difference high cost, the speed under on the other hand its hardware implementation mode has also evaded software realization mode cannot be caught up with
Shortcoming.But for high-resolution FFC algorithm, FPGA also has the shortcoming of himself, i.e. internal resource limited, possibly height cannot be tackled
The image in different resolution requirement to storage resource.As for KAI-47051, its pixel quantity is 47.8MB, i.e. by each pixel
Minimum 8-bit calculates, and preserving AI array corresponding to piece image needs the memory space of 47.8MB；Even if disregarding FPGA to buy into
This, the FPGA of current most significant end also is difficult to reach this requirement.This just requires in the situation ensureing certain output image quality
Under, need original FFC algorithm is optimized, so that it is real to realize area array cameras under high-resolution high frame per second based on FPGA
Time FFC algorithm be possibly realized.
Summary of the invention
The present invention provides a kind of area array cameras flat field realized based on FPGA to correct real time algorithm, for high-resolution, high frame
Rate area array cameras realizes real-time FFC algorithm and provides possible, provides higher output image for high-resolution high frame per second application scenario
Quality.
For solving above-mentioned technical problem, the present invention adopts the following technical scheme that
A kind of area array cameras flat field realized based on FPGA corrects real time algorithm, comprises the steps:
1) sensor effective resolution is set to: horizontal colcount, vertical rowcount, by resolution according to the square of N × N
Battle array is divided into multiple basic block, obtains image under the conditions of actual illumination, using the image average of each basic block as input number
According to, carrying out FFC rectification calculating acquisition normalization ai array is:
2) replicating multi-resolution boundary, extension ai array is:
3) obtaining basic block belonging to pixel is: [i] [j],
4) each pixel to basic block, by current basic block and the FFC data of adjacent basic block and current picture
(x y), is calculated, based on bilinear interpolation algorithm, the ai value that pixel is actual to vegetarian refreshments coordinate；
5) current basic block is divided into four quadrants from center, selects to participate in computing according to the subordinate quadrant of pixel
Ai value；
6) concurrent operation based on FPGA, calculates the value of four quadrants simultaneously, selects output by sign bit, in conjunction with ai number
The two-dimensional matrix of group, to the conversion of one-dimensional matrix, calculates final result, and formula is as follows:
Further, step 6) in, the concurrent operation of FPGA uses 8 pixels to be a processing unit, specifically calculates
Journey comprises the steps:
61) according to 8 pixel cells address computation basic block [i] [j]；
62) current basic block and adjacent basic block totally 9 unit, rear basis are read according to basic block [i] [j] from ai array
Y [bit3], N [bit0] value judges the quadrant at this 8 pixel cell place；
63) A, B, C, D, a are calculated according to place quadrantoAnd a1；
64) minor is calculated: A* (N-a0)*(N-a1)、B*a0*(N-a1)、C*(N-a0)*a1And D*a0*a1；
65) the most calculated four minors addition is obtained ai_out, and ai_out is moved to right 8, obtain final
Result dout=(din*ai_out).
Preferably, step 61) in, basic block [i] [j] isWherein y is this 8 pixel cell institute
In line number, N is the call number of this 8 pixel cell.
Preferably, step 62) in, described 9 unit are respectively as follows: ai [i-1] [j-1], ai [i-1] [j], ai [i-1] [j+
1], ai [i] [j-1], ai [i] [j], ai [i] [j+1], ai [i+1] [j-1], ai [i+1] [j] and ai [i+1] [j+1].
Further, step 4) in, pixel is in basic block [yi] [xj], calculates ai_x0And ai_x1:
ai_x0=ai [yi] [xi]+(ai [yi] [xi-1]-ai [yi] [xi])/N* (N/2-x%*N)；
ai_x1=ai [yi-1] [xi]+(ai [yi-1] [xi-1]-ai [yi-1] [xi])/N* (N/2-x%*N)
Calculating ai_out:
Ai_out=ai_x0+(ai_x1-ai_x0)/N* (N/2-y%*N).
Preferably, the N value of described basic block is 16～128.
From above technical scheme, present invention optimizes FPGA concurrent operation, for the face battle array under high-resolution, high frame per second
Camera realizes real-time FFC correction algorithm and provides possibility, provides higher output figure for high-resolution, high frame per second application scenario
Picture element amount.By using optimized algorithm, successfully to PRNU and vignetting effect under the requirement meeting high-resolution and high frame per second
Carry out real-time rectification.
Accompanying drawing explanation
Fig. 1 is basic block segmentation and the schematic diagram of quadrant segmented in inventive algorithm；
Fig. 2 is the schematic diagram that in inventive algorithm, after basic block segmentation, boundary pixel ai array extends；
Fig. 3 is the simulated effect graphics before and after the ai algorithm under basic block size is 128x128 in embodiment is corrected；
Fig. 4 is the image comparison in embodiment before and after AI algorithm is corrected.
Detailed description of the invention
Below in conjunction with the accompanying drawings a kind of preferred implementation of the present invention is described in detail.
FFC algorithm is mainly used in correcting the response nonuniformity of sensor array and non-ideal error, and rudimentary algorithm is as follows:
Yi=Xi*ai, wherein Yi is data after correcting, and Xi is the initial data of sensor output.Area array cameras is the highest due to resolution,
If directly doing single-point FFC computing, then need to maintain one and image resolution ratio an equal amount of ai array, consume resource mistake
Many, it is directly realized by infeasible in FPGA, needs algorithm is optimized.The primary and foremost purpose optimized is to reduce algorithm to storage money
The consumption in source, in order to reduce the demand to storage resource, can use block-based operation method, and the present embodiment is with 16x16 picture
Element block is elementary cell, and sensor array is carried out piecemeal operation, and combining interpolation algorithm on the basis of piecemeal can reduce money
Source clicks on row operation to each while consuming.
As a example by KAI-47051, full resolution is 8880x5392, cuts into the matrix of 555x337, and each matrix is corresponding
The basic block of one 16x16.Image is obtained, using the image average of each basic block as input number under the conditions of actual illumination
According to, calculate and obtain normalization array ai [yi] [xi], after enabling FFC algorithm, each pixel to real image, by currently
And the FFC data of adjacent block and current pixel point coordinates are calculated the ai coefficient of reality, the process that calculates is based on bilinearity
Interpolation algorithm.4 ai data of each pixel participation computing, from 4 nearest blocks, will be divided into 4 from center by current block
Individual quadrant (A/B/C/D), selects to participate in the ai parameter of computing according to pixel subordinate quadrant.
As it is shown in figure 1, light color pixel is current point, it is in the upper left position of block [yi] [xi], i.e. in quadrant A.
First, ai_x is calculated0And ai_x1:
ai_x0=ai [yi] [xi]+(ai [yi] [xi-1]-ai [yi] [xi])/N* (N/2-x%*N)；
ai_x1=ai [yi-1] [xi]+(ai [yi-1] [xi-1]-ai [yi-1] [xi])/N* (N/2-x%*N)
Calculate ai_out again:
Ai_out=ai_x0+(ai_x1-ai_x0)/N* (N/2-y%*N).
For boundary pixel, for ensureing the concordance of calculating process, replicate extension ai array, as shown in Figure 2.
As a example by 16x16 block, derivation is as follows: sensor effective resolution is set to: horizontal colcount, vertically
Rowcount, if having completed ai array, and has completed border duplication, and ai array representation is:
Array coordinate from the beginning of 0, if pixel coordinate be (x, y), from the beginning of 0, can derive block belonging to pixel is: [i] [j],Add 1 expression border is replicated herein.
Concurrent operation based on FPGA, calculates the value of 4 quadrants simultaneously, selects output by sign bit, in conjunction with ai two dimension
Matrix is to the conversion of one-dimensional matrixCalculating concrete outcome is as follows:
Definition x [b'3] is that the 3rd bit, bit taking x starts counting up from 0.
Quadrant A:y [b'3]=0；X [b'3]=0
Kya=(8-y%8)；Kxa=(8-x%8)
Ai_A={ai [i] [j] * (16-kxa) * (16-kya)+a [i] [j-1] * kxa* (16-kya)
+ ai [i-1] [j] * (16-kxa) * kya+ai [i-1] [j-1] * kxa*kya} ＞ ＞ 8
Quadrant B:y [b'3]=0；X [b'3]=1
Kyb=(8-y%8)；Kxb=x%8
Ai_B={ai [i] [j] * (16-kxb) * (16-kyb)+a [i] [j+1] * kxb* (16-kyb)
+ ai [i-1] [j] * (16-kxb) * kyb+ai [i-1] [j+1] * kxb*kyb} ＞ ＞ 8
Quadrant C:y [b'3]=1；X [b'3]=0
Kyc=y%8；Kxc=(8-x%8)
Ai_c={ai [i] [j] * (16-kxc) * (16-kyc)+a [i] [j-1] * kxc* (16-kyc)
+ ai [i+1] [j] * (16-kxc) * kyc+ai [i+1] [j-1] * kxc*kyc} ＞ ＞ 8
Quadrant D:y [b'3]=1；X [b'3]=1
Kyd=y%8；Kxd=x%8
Ai_D={ai [i] [j] * (16-kxd) * (16-kyd)+a [i] [j+1] * kxd* (16-kyd)
+ ai [i+1] [j] * (16-kxd) * kyd+ai [i+1] [j+1] * kxd*kyd} ＞ ＞ 8
Final result: Dout=Din*ai_X ＞ ＞ 12, wherein ai_X selects ai_A/ai_B/ai_C/ according to different quadrants
ai_D。
Using 16x16 block as elementary cell, resource consumption is 0.39% under single-point FFC algorithm.Based on cost or its
Restriction in terms of him, in the case of FPGA device model is selected, in the case of i.e. available storage resource quantity is certain, Ke Yishi
When the size increasing block continue to reduce demand to resource, during as increased to 32x32 block, the resource of consumption drops to single-point
Under algorithm 0.097%.Along with basic unit block becomes larger, although consumption resource is the fewest, but algorithm effect is the most undesirable,
So there being a compromise between effect and resource consumption, need to accept or reject according to concrete application scenarios.From among Matlab
After algorithm is emulated from the point of view of result, basic block unit in the case of 128x128, still can obtain preferable effect (as
Shown in Fig. 3), 0.006% under now resource consumption is single-point algorithm, even for the high-resolution image of 47.8MB, it is deposited
Storage resource consumption is only 2.9KB, and this resource consumption will without a doubt for realizing FFC algorithm in FPGA.
In FPGA realizes, intermediate treatment stage is all to be that a processing unit is to increase parallel efficiency with 8 pixels.
FFC algorithm needs according to pixel coordinate computation index number, and making pixel coordinate is that (x, y), wherein x is row number, and y is line number, then ai
In array for unit ai [i] [j], i=(y/16)+1, j=(x/16)+1；
For 8 pixel cells, y is identical, and x is 8z～8z+7, z=0,1,2 ..., now it is calculated
I, j be all identical, the corresponding call number in ai array of 8 pixels in i.e. one processing unit is all identical.
According to algorithm idea, each pixel needs to calculate 4 values, the most corresponding 4 kinds of situations.These 4 values need to use to 9
Individual ai array location, is respectively as follows: ai [i-1] [j-1], ai [i-1] [j], ai [i-1] [j+1], ai [i] [j-1], ai [i] [j],
Ai [i] [j+1], ai [i+1] [j-1], ai [i+1] [j], ai [i+1] [j+1], for 4 the quadrant feelings proposed in algorithm document
Condition, 8 pixels in a processing unit all belong simultaneously to a quadrant, so need not 8 pixels are judged respectively,
Have only to first quadrant is judged.
The judgement to a processing unit offset address can be directly attributed to for the judgement of first pixel, such as 8
The index of pixel cell is even number (starting counting up from 0), and now the pixel index in unit is 0～7, then mean that x
[bit3]=0, if the index of 8 pixel cells is odd number, now the pixel index in unit is 8～15, then mean that x
[bit3]=1.
For the judgement of line number, the most directly using line number [3] to judge, each 8 pixel cells one are scheduled on same row
In.
In a word, for a quadrant cell, for such as 20MB camera, a line has 5120 row, i.e. 640 8 pixel cells,
Call number is 0～639.The call number assuming certain 8 pixel cell is N (N [0,639]), and place line number is y, then ai array rope
Drawing [i, j] is i=y/16+1, j=N*8/16+1=N/2+1；I, j all use 9-bit bit wide depositor to represent.
After being calculated [i, j], needing to read 9 unit from ai array, these 9 unit are segmented into 3 groups, in group
3 unit be all address continuous print, now need to see the value of j, known j=N/2+1, N=0,1 from above, 2 ..., i.e. j value
It is 1,2,3 ..., this disposable reading that just cannot realize organizing interior 3 unit, can only single read, i.e. 9 unit need to consume
9 clock clocks.Ai array location sum is 322 × 242=77924 (needing 17-bit depositor to represent address), each unit
For 14-bit.
Ai array often row element number is 5120/16+2=322 (representing with a 9-bit bit wide depositor), can calculate
In obtaining ai array, 9 sensing element addresses (17-bit bit wide depositor represents) are respectively as follows:
(i-1) * 322+ (j-1), (i-1) * 322+ (j), (i-1) * 322+ (j+1)
(i) * 322+ (j-1), (i) * 322+ (j), (i) * 322+ (j+1)
(i+1) * 322+ (j-1), (i+1) * 322+ (j), (i+1) * 322+ (j+1)
Because for 8 pixel cells, the corresponding i, j of internal 8 pixels is identical, this mean that for
For 8 pixels, the ai element of use is identical, and i.e. one 8 pixel cells have only to read 9 ai unit, simultaneously because 8
Individual pixel also is located at identical as in system, so for 8 pixels, is all to take identical finally to calculate as set occurrence.
The formula of other 4 picture systems can be unified:
Ai_out=A* (16-a0)*(16-a1)+B*a0*(16-a1)+C*(16-a0)*a1+D*a0*a1；
According to as the difference of system, A, B, C, D, a thereinoAnd a1Calculation has difference.
Implement details:
1. according to line number lines_rd, 8 pixel cell cnt_rd calculating i, j:
I=lines_rd/16+1, j=cnt_rd/2+1；
2., according to i, j calculates ram_addr:
(i-1)*322+(j-1),(i)*322+(j-1),(i+1)*322+(j-1)；
3. according to lines_rd, the cnt_rd that 88 pixel cells are corresponding judges the quadrant of 88 pixel cells, obtains each
A, B, C, D, a of unitoAnd a1Value；
4. calculate each unit
Ai_out=A* (16-a0)*(16-a1)+B*a0*(16-a1)+C*(16-a0)*a1+D*a0*a1；
5. calculate final result dout=(din*ai_out) > > 12.Notice that 88 pixel cells have different ai_out
Value, but 8 pixels in 8 pixel cells use identical ai_out, can export the value of 64 pixels i.e. simultaneously.Rectification effect
Comparing result with reference to Fig. 4.
The above embodiment is only to be described the preferred embodiment of the present invention, the not model to the present invention
Enclose and be defined, on the premise of designing spirit without departing from the present invention, the those of ordinary skill in the art technical side to the present invention
Various deformation that case is made and improvement, all should fall in the protection domain that claims of the present invention determines.
Claims (6)
1. the area array cameras flat field realized based on FPGA corrects real time algorithm, it is characterised in that comprise the steps:
1) sensor effective resolution is set to: horizontal colcount, and resolution is divided by vertical rowcount according to the matrix of N × N
It is slit into multiple basic block, under the conditions of actual illumination, obtains image, using the image average of each basic block as input data, enter
Row FFC corrects calculating acquisition normalization ai array:
2) replicating multi-resolution boundary, extension ai array is:
3) obtaining basic block belonging to pixel is:
4) each pixel to basic block, by FFC data and the current pixel point of current basic block and adjacent basic block
(x y), is calculated, based on bilinear interpolation algorithm, the ai value that pixel is actual to coordinate；
5) current basic block is divided into four quadrants from center, selects to participate in the ai of computing according to the subordinate quadrant of pixel
Value；
6) concurrent operation based on FPGA, calculates the value of four quadrants simultaneously, selects output by sign bit, in conjunction with ai array
Two-dimensional matrix, to the conversion of one-dimensional matrix, calculates final result, and formula is as follows:
Area array cameras flat field the most according to claim 1 corrects real time algorithm, it is characterised in that step 6) in, FPGA's
Concurrent operation uses 8 pixels to be a processing unit, and concrete calculating process comprises the steps:
61) according to 8 pixel cells address computation basic block [i] [j]；
62) read current basic block and adjacent basic block totally 9 unit according to basic block [i] [j] from ai array, after according to y
[bit3], N [bit0] value judges the quadrant at this 8 pixel cell place；
63) A, B, C, D, a are calculated according to place quadrantoAnd a1；
64) minor is calculated: A* (N-a0)*(N-a1)、B*a0*(N-a1)、C*(N-a0)*a1And D*a0*a1；
65) the most calculated four minors addition is obtained ai_out, and ai_out is moved to right 8, obtain final result
Dout=(din*ai_out).
Area array cameras flat field the most according to claim 2 corrects real time algorithm, it is characterised in that step 61) in, basic block
[i] [j] isWherein y is this 8 pixel cell place line number, and N is the call number of this 8 pixel cell.
Area array cameras flat field the most according to claim 2 corrects real time algorithm, it is characterised in that step 62) in, described 9
Individual unit is respectively as follows: ai [i-1] [j-1], ai [i-1] [j], ai [i-1] [j+1], ai [i] [j-1], ai [i] [j], ai [i] [j
+ 1], ai [i+1] [j-1], ai [i+1] [j] and ai [i+1] [j+1].
Area array cameras flat field the most according to claim 1 corrects real time algorithm, it is characterised in that step 4) in, pixel
It is in basic block [yi] [xj], calculates ai_x0And ai_x1:
ai_x0=ai [yi] [xi]+(ai [yi] [xi-1]-ai [yi] [xi])/N* (N/2-x%*N)；
ai_x1=ai [yi-1] [xi]+(ai [yi-1] [xi-1]-ai [yi-1] [xi])/N* (N/2-x%*N)
Calculating ai_out:
Ai_out=ai_x0+(ai_x1-ai_x0)/N* (N/2-y%*N).
Area array cameras flat field the most according to claim 1 corrects real time algorithm, it is characterised in that the N value of described basic block
It is 16～128.
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