CN106200177A - Display and display floater thereof - Google Patents
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- CN106200177A CN106200177A CN201610728797.6A CN201610728797A CN106200177A CN 106200177 A CN106200177 A CN 106200177A CN 201610728797 A CN201610728797 A CN 201610728797A CN 106200177 A CN106200177 A CN 106200177A
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Abstract
The invention discloses a kind of display floater, it includes first substrate, second substrate, it is clamped in the liquid crystal layer between the first and second substrates, the first metal layer on the first substrate and the first common electrode layer are set, it is arranged on the gate insulator in the first metal layer and the first common electrode layer, the active layer being arranged on gate insulator, the interlayer dielectric layer being arranged on active layer and the second metal level being arranged on interlayer dielectric layer and active layer, second metal level includes the first sub-metal level and the second sub-metal level being set to one, first sub-metal level is turned on active layer by the via being arranged on interlayer dielectric layer, second sub-metal level is positioned at the region the most corresponding with the first common electrode layer and the second sub-metal level is arranged on active layer.The invention also discloses a kind of display.By the way, the present invention can reduce the difference of positive and negative frame gray scale voltage change, reduces scintillation.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of display and display floater thereof.
Background technology
Display panels, due to advantages such as its lightening and low-power consumption, is the main flow display device in existing market, hands
Machine screen often uses FFS (Fringe Field Switching, fringe field switching) this display pattern, because it has wider
Visual angle and the impact being susceptible to the thick slight change of liquid crystal cell, be commonly called as shielding into hard；For reducing power consumption, FFS display pattern generally requires
Relatively low source (source electrode) driving voltage, the pressure reduction of adjacent GTG can be less, is therefore more prone to GTG fluctuation, as dodged
Bright, crosstalk etc..
Flicker Producing reason has multiple, such as liquid crystal electric leakage, liquid crystal ion residues, thin film transistor (TFT) electric leakage etc.；Especially
The difference of positive and negative frame (i.e. pixel electrode is when connecing positive polarity voltage and reverse voltage respectively) thin film transistor (TFT) electric leakage causes
Flicker, often after solving problem of materials, becomes the main cause of flicker, also must designer keep a close eye on.Due to feedback voltage
Impact, the electric leakage of negative frame can be more serious, and the electric leakage of positive frame can be relatively slight, and this species diversity cannot be by adjusting reference voltage
Eliminate.
Accordingly, it is desirable to provide a kind of display and display floater thereof are to solve above-mentioned technical problem.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of display and display floater thereof, it is possible to reduce positive and negative frame ash
The difference of rank change in voltage, reduces scintillation.
For solving above-mentioned technical problem, the technical scheme that the present invention uses is: provide a kind of display floater, this display
Panel includes first substrate, second substrate, the liquid crystal layer being clamped between first substrate and second substrate, is arranged on first substrate
On the first metal layer and the first common electrode layer, the gate insulator that is arranged in the first metal layer and the first common electrode layer
Layer, the active layer, the interlayer dielectric layer being arranged on active layer that are arranged on gate insulator and be arranged on interlayer dielectric layer
With the second metal level on active layer, the second metal level includes the first sub-metal level and the second sub-metal level being set to one,
First sub-metal level is turned on active layer by the via being arranged on interlayer dielectric layer, and the second sub-metal level is positioned at public with first
Region and the second sub-metal level that common electrode layer is corresponding up and down are arranged on active layer.
Wherein, active layer include intrinsic portion, lay respectively at the first of both sides, intrinsic portion be lightly doped portion and second be lightly doped portion,
Be positioned at first be lightly doped portion away from side, intrinsic portion the first heavy doping portion, be positioned at second and portion be lightly doped away from side, intrinsic portion
Second heavy doping portion, the second sub-metal level is arranged in the first heavy doping portion.
Wherein, active layer is polysilicon semiconductor layer, first be lightly doped portion, second be lightly doped portion, the first heavy doping portion with
And second heavy doping portion be n-type doping.
Wherein, the width of the first heavily doped doping is more than the width in the second heavy doping portion.
Wherein, the first sub-metal level is turned on by via and the first heavy doping portion or the second heavy doping portion.
Wherein, display floater farther includes planarization layer, the setting being arranged on the second metal level and interlayer dielectric layer
The second common electrode layer on planarization layer, the passivation layer being arranged in planarization layer and the second common electrode layer and setting
Transparent electrode layer over the passivation layer.
Wherein, transparent electrode layer turns on by being arranged on the via on passivation layer and planarization layer and the first sub-metal level.
Wherein, display floater farther includes the colored filter being arranged on second substrate.
Wherein, display floater is fringe field switching display floater.
For solving above-mentioned technical problem, another technical solution used in the present invention is: provide a kind of display, this display
Device includes display floater and for providing the backlight module of backlight for described display floater, and this display floater is above-mentioned display surface
Plate.
The invention has the beneficial effects as follows: be different from the situation of prior art, the present invention includes by arranging display floater
One substrate, second substrate, the liquid crystal layer being clamped between first substrate and second substrate, setting the first gold medal on the first substrate
Belong to layer and the first common electrode layer, the gate insulator being arranged in the first metal layer and the first common electrode layer, be arranged on grid
Active layer, the interlayer dielectric layer being arranged on active layer on the insulating barrier of pole and be arranged on interlayer dielectric layer and active layer
Second metal level, the second metal level includes the first sub-metal level and the second sub-metal level, the first sub-metal level being set to one
Being turned on active layer by the via being arranged on interlayer dielectric layer, the second sub-metal level is positioned at upper and lower with the first common electrode layer
Corresponding region and the second sub-metal level are arranged on active layer, so that the second interest genus forms ohm with active layer and connects
Touching, the first common electrode layer forms MIS (metal-insulator semiconductor, Metal-Insulator-with active layer
Semiconductor) electric capacity, therefore between the second sub-metal level and the first common electrode layer formed one can power transformation storage hold
Device, specifically, when pixel electrode is positive voltage (positive frame), the second sub-metal level is positive voltage, and storage electric capacity is less, works as pixel
When electrode is negative voltage, the second sub-metal level is positive voltage (negative frame), storage electric capacity is relatively big, therefore can reduce the electric leakage of negative frame
The size of stream, reduces the difference of positive and negative frame gray scale voltage change, also can slacken because of the impact on voltage of leaking electricity simultaneously, reduce picture
Flicker, on the one hand reduce the feedback voltage of negative frame, on the other hand increase the storage capacitors amount of negative frame, strengthen its opposing electric leakage band
The ability of the gray scale variation come, such that it is able to reduce scintillation.
Accompanying drawing explanation
Fig. 1 is the structural representation of the display floater of the preferred embodiment of the present invention；
Fig. 2 is that the present invention second sub-metal level is formed between the second sub-metal level and the first common electrode layer when being negative voltage
The schematic diagram of storage electric capacity；
Fig. 3 is that the present invention second sub-metal level is formed between the second sub-metal level and the first common electrode layer when being positive voltage
The schematic diagram of storage electric capacity；
Fig. 4 is the structural representation of inventive display.
Detailed description of the invention
The present invention will be described in detail with embodiment below in conjunction with the accompanying drawings.
Refer to the structural representation that Fig. 1, Fig. 1 are the display floaters of the preferred embodiment of the present invention.In the present embodiment, aobvious
Show that panel includes first substrate 11, second substrate 12, the liquid crystal layer 13 being clamped between first substrate 11 and second substrate 12, sets
Put the first metal layer 14 on first substrate 11 and the first common electrode layer 15, to be arranged on the first metal layer 14 and first public
Gate insulator 16, the active layer 17 being arranged on gate insulator 16 on electrode layer 15 and first substrate 11, it is arranged on
Interlayer dielectric layer 18 in active layer 17 and the second metal level 19 being arranged on interlayer dielectric layer 18 and active layer 17, the second gold medal
Belonging to layer 19 and include being set to the first sub-metal level 191 and the second sub-metal level 192 of one, the first sub-metal level 191 is by setting
The via put on interlayer dielectric layer 18 turns on active layer 17.
Preferably, active layer 17 is polysilicon semiconductor layer 17.It will be understood by those skilled in the art that in other embodiments
Middle active layer can also be other semiconductor layer.
Second sub-metal level 192 is positioned at the region corresponding with the first common electrode layer about 15 and the second sub-metal level 192
It is arranged on polysilicon semiconductor layer 17.It is to say, the vertical throwing that the second sub-metal level 192 is in the first common electrode layer 15
Shadow and the first common electrode layer 15 are least partially overlapped, it is preferable that in the present embodiment, and the second sub-metal level 192 is public first
Upright projection in common electrode layer 15 is completely overlapped with the first common electrode layer 15.Second sub-metal level 192 is set directly at many
On crystal silicon semiconductor layer 17.
Incorporated by reference to Fig. 1 refering to Fig. 2 and Fig. 3, Fig. 2 be the sub-metal level of the present invention second be negative voltage time the second sub-metal level and
The schematic diagram of storage electric capacity is formed between first common electrode layer.Fig. 3 is that the present invention second sub-metal level is when being positive voltage second
The schematic diagram of storage electric capacity is formed between sub-metal level and the first common electrode layer.Due to the first common electrode layer 15 and the second son
Be sequentially laminated with gate insulator 16 and polysilicon semiconductor layer 17 between metal level 192, therefore constitute metal-insulator-
Semiconductor capacitance structure.Those skilled in the art are understood that the first sub-metal level 191 is drain-source layer, it is preferable that in Fig. 1 first
The part on sub-metal level 191 left side is source electrode, and the part on the right is drain electrode, in other embodiments, it is also possible to be the first interest
Belonging to the part on the right of layer 191 is source electrode, and the part on the left side is drain electrode.
As in figure 2 it is shown, when data signal is negative voltage (when being negative frame data), the voltage of the first sub-metal level 191
Being negative, so the voltage of the second sub-metal level 192 is negative, electric field E1 direction is pointed to the second interest by the first common electrode layer 15 and is belonged to
Layer 192, polysilicon semiconductor layer 17 is near the interface of gate insulator 16 gathering electronics S, and forming capacitance size is C1, its electricity
The thickness of container is the thickness of gate insulator 16.
As it is shown on figure 3, when data signal is positive voltage (when being positive frame data), the voltage of the first sub-metal level 191
For just, the voltage of the second sub-metal level 192 is just, direction of an electric field is pointed to the first common electrode layer 15 by the second sub-metal level 192,
Polysilicon semiconductor layer 17 forms depletion layer t near the interface of gate insulator 16, and its total capacitance can reduce, for C1 and C2 two
The series connection of individual electric capacity, i.e. size are C=1/ (1/C1+1/C2), and wherein C2 is for exhausting t layer capacitance.
As can be seen here, variable depositing of size is defined between the second sub-metal level 192 and the first common electrode layer 15
Storage electric capacity, when the second sub-metal level 192 is positive voltage, electric capacity is less, and when the second sub-metal level 192 is negative voltage, electric capacity is relatively
Greatly, therefore can reduce the size of the leakage current of negative frame, reduce the difference of positive and negative frame gray scale voltage change, also can slacken because of leakage simultaneously
The electricity impact on voltage, reduces the flicker of picture, on the one hand reduces the feedback voltage of negative frame, on the other hand increases the storage of negative frame
Capacitance, strengthens the ability of the gray scale variation that its opposing electric leakage brings, such that it is able to reduce scintillation.
Preferably, polysilicon semiconductor layer 17 includes intrinsic portion 171, lays respectively at the first of both sides, intrinsic portion portion is lightly doped
172 and second portion 173 is lightly doped, is positioned at first and portion 172 is lightly doped away from the first heavy doping portion 174 of side, intrinsic portion 171, position
Portion 173 second heavy doping portion 175 away from intrinsic portion 171 side being lightly doped in second, the second sub-metal level 192 is arranged on first
In heavy doping portion 174.It is to say, the polysilicon semiconductor layer 17 in Fig. 2 and Fig. 3 is particularly preferred as polysilicon semiconductor layer 17
The first heavy doping portion 174.
The most in other embodiments, the polysilicon semiconductor layer 17 in Fig. 2 and Fig. 3 specifically partly can also be led for polysilicon
Other parts of body layer 17, namely the second metal level 192 can also be arranged on other doping such as first be lightly doped portion 172,
Second is lightly doped in portion 173 or the second heavy doping portion 175.
Preferably, first portion 172 is lightly doped, second portion 173, first heavy doping portion 174 and second heavy doping is lightly doped
Portion 175 is n-type doping.
Preferably, the width of the first heavily doped doping 174 is more than the width in the second heavy doping portion 175.Preferably, the first weight
Width and first common electrode layer 15 width of doping 174 are equal.The width in the first heavy doping portion 174 is set greater than
The width of double doping 175, it is simple to form variable capacitance between the first common electrode layer 15 and the second sub-metal level 192.
Preferably, first portion 172 is lightly doped, second portion 173, first heavy doping portion 174 and second heavy doping is lightly doped
Portion 175 quantity is multiple, it will be appreciated by persons skilled in the art that polysilicon semiconductor layer 17 includes and TFT structure one
The polysilicon semiconductor unit of one respective amount, each polysilicon semiconductor unit includes that one first is lightly doped 172, one, portion
Second is lightly doped the first heavy doping portion 174 of 173, one, portion and a second heavy doping portion 175, it is notable that such as Fig. 1
Shown in, it will be understood by those skilled in the art that the second sub-metal level 192 TFT structure is corresponding is provided in another (phase
Adjacent) in the first heavy doping portion 174 of the polysilicon uniconductor unit of TFT structure.
Preferably, the first sub-metal level 191 is led by via and the first heavy doping portion 174 or the second heavy doping portion 175
Logical.The source electrode being preferably located at the first sub-metal level 192 left-hand component is turned on by via and the first heavy doping portion 174, is positioned at
The drain electrode of the first sub-metal level 192 right-hand component is turned on by via and the second heavy doping portion 175.It should be noted that first
Sub-metal level 191 is to turn on the first heavy doping portion 174 in same TFT structure or the second heavy doping portion 175.
Preferably, display floater farther includes the planarization layer being arranged on the second metal level 19 and interlayer dielectric layer 18
20, the second common electrode layer 21 of being arranged on planarization layer 20, it is arranged in planarization layer 20 and the second common electrode layer 21
Passivation layer 22 and the transparent electrode layer 23 that is arranged on passivation layer 22.Transparent electrode layer 23 is by being arranged on passivation layer 22 He
Via and the first sub-metal level 191 on planarization layer 20 turn on.
Preferably, display floater farther includes the colored filter 24 being arranged on second substrate 12.
Preferably, display floater is fringe field switching display floater.Certainly, in other embodiments, display floater also may be used
Think other type.
Preferably, display floater can also include being supported on the support column between first substrate 11 and second substrate 12 or
First substrate 11 or second substrate 12 can also include other film layers, such as polaroid etc..
Refer to the structural representation that Fig. 4, Fig. 4 are inventive display.In this example it is shown that device includes display surface
Plate 41 and for providing the backlight module 42 of backlight for display floater 41, this display floater 41 is any one embodiment institute above-mentioned
The display floater stated.
The present invention includes first substrate, second substrate by arranging display floater, is clamped in first substrate and second substrate
Between liquid crystal layer, arrange the first metal layer and the first common electrode layer on the first substrate, be arranged on the first metal layer and
Gate insulator in first common electrode layer, the active layer being arranged on gate insulator, the interlayer that is arranged on active layer
Dielectric layer and the second metal level being arranged on interlayer dielectric layer and active layer, the second metal level includes being set to the of one
One sub-metal level and the second sub-metal level, the first sub-metal level is led with active layer by the via being arranged on interlayer dielectric layer
Logical, the second sub-metal level is positioned at the region the most corresponding with the first common electrode layer and the second sub-metal level is arranged on active layer
On, so that the second interest belongs to forms Ohmic contact with active layer, the first common electrode layer and active layer form MIS (gold
Genus-insulator-quasiconductor, Metal-Insulator-Semiconductor) electric capacity, therefore the second sub-metal level and first
Formed between common electrode layer one can the storage container of power transformation, specifically, when pixel electrode is positive voltage (positive frame), second
Sub-metal level is positive voltage, and storage electric capacity is less, and when pixel electrode is negative voltage, the second sub-metal level is positive voltage (negative frame)
Time, storage electric capacity is relatively big, therefore can reduce the size of the leakage current of negative frame, reduce the difference of positive and negative frame gray scale voltage change, with
Time also can slacken because of the electric leakage impact on voltage, reduce the flicker of picture, on the one hand reduce the feedback voltage of negative frame, on the other hand
Increase the storage capacitors amount of negative frame, strengthen the ability of the gray scale variation that its opposing electric leakage brings, such that it is able to reduce scintillation.
The foregoing is only embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization is originally
Equivalent structure or equivalence flow process that description of the invention and accompanying drawing content are made convert, or are directly or indirectly used in what other were correlated with
Technical field, is the most in like manner included in the scope of patent protection of the present invention.
Claims (10)
1. a display floater, it is characterised in that described display floater includes first substrate, second substrate, is clamped in described
Liquid crystal layer between one substrate and described second substrate, the first metal layer being arranged on described first substrate and the first common electrical
Pole layer, the gate insulator being arranged in described the first metal layer and described first common electrode layer, to be arranged on described grid exhausted
Active layer, the interlayer dielectric layer being arranged on described active layer in edge layer and be arranged on described interlayer dielectric layer and described have
The second metal level in active layer, described second metal level includes the first sub-metal level and the second sub-metal level being set to one,
Described first sub-metal level is turned on described active layer by the via being arranged on described interlayer dielectric layer, described second interest
Genus layer is positioned at the region the most corresponding with described first common electrode layer and described second sub-metal level is arranged on described active layer
On.
Display floater the most according to claim 1, it is characterised in that described active layer includes intrinsic portion, lays respectively at institute
State the first of both sides, intrinsic portion portion and second is lightly doped portion to be lightly doped, is positioned at described first and portion is lightly doped away from described intrinsic portion one
First heavy doping portion of side, it is positioned at described second portion second heavy doping portion away from described intrinsic portion side be lightly doped, described
Two sub-metal levels are arranged in described first heavy doping portion.
Display floater the most according to claim 2, it is characterised in that described active layer is polysilicon semiconductor layer, described
First portion is lightly doped, described second portion, described first heavy doping portion and described second heavy doping portion are lightly doped are N-type and mix
Miscellaneous.
Display floater the most according to claim 2, it is characterised in that the width of described first heavily doped doping is more than described
The width in the second heavy doping portion.
Display floater the most according to claim 2, it is characterised in that described first sub-metal level is by via and described the
One heavy doping portion or described second heavy doping portion conducting.
Display floater the most according to claim 1, it is characterised in that described display floater farther includes to be arranged on described
Planarization layer on second metal level and described interlayer dielectric layer, the second common electrode layer being arranged on described planarization layer,
Be arranged on the passivation layer in described planarization layer and described second common electrode layer and be arranged on described passivation layer transparent
Electrode layer.
Display floater the most according to claim 6, it is characterised in that described transparent electrode layer is by being arranged on described passivation
Via on layer and described planarization layer and described first sub-metal level conducting.
Display floater the most according to claim 1, it is characterised in that described display floater farther includes to be arranged on described
Colored filter on second substrate.
Display floater the most according to claim 1, it is characterised in that described display floater is fringe field switching display surface
Plate.
10. a display, it is characterised in that described display includes display floater and for providing the back of the body for described display floater
The backlight module of light, described display floater is the display floater as described in claim 1-9 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610728797.6A CN106200177B (en) | 2016-08-25 | 2016-08-25 | Display and its display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610728797.6A CN106200177B (en) | 2016-08-25 | 2016-08-25 | Display and its display panel |
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| Publication Number | Publication Date |
|---|---|
| CN106200177A true CN106200177A (en) | 2016-12-07 |
| CN106200177B CN106200177B (en) | 2019-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610728797.6A Active CN106200177B (en) | 2016-08-25 | 2016-08-25 | Display and its display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114779543A (en) * | 2022-04-02 | 2022-07-22 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
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| CN103489824A (en) * | 2013-09-05 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, and display device |
| CN104409483A (en) * | 2014-10-16 | 2015-03-11 | 京东方科技集团股份有限公司 | Array substrate and production method thereof as well as display device |
| CN105679768A (en) * | 2016-01-25 | 2016-06-15 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20060062573A (en) * | 2004-12-03 | 2006-06-12 | 엘지.필립스 엘시디 주식회사 | Thin film transistor array substrate and manufacturing method of the same |
| CN103489824A (en) * | 2013-09-05 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, and display device |
| CN104409483A (en) * | 2014-10-16 | 2015-03-11 | 京东方科技集团股份有限公司 | Array substrate and production method thereof as well as display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114779543A (en) * | 2022-04-02 | 2022-07-22 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
| CN114779543B (en) * | 2022-04-02 | 2023-09-26 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
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| CN106200177B (en) | 2019-11-26 |
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