CN106168930A - 转换后备缓冲器 - Google Patents
转换后备缓冲器 Download PDFInfo
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- CN106168930A CN106168930A CN201610330320.2A CN201610330320A CN106168930A CN 106168930 A CN106168930 A CN 106168930A CN 201610330320 A CN201610330320 A CN 201610330320A CN 106168930 A CN106168930 A CN 106168930A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/652—Page size control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/684—TLB miss handling
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/715,117 US9830275B2 (en) | 2015-05-18 | 2015-05-18 | Translation lookaside buffer |
US14/715,117 | 2015-05-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106168930A true CN106168930A (zh) | 2016-11-30 |
Family
ID=56014889
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610330320.2A Pending CN106168930A (zh) | 2015-05-18 | 2016-05-18 | 转换后备缓冲器 |
CN201620454206.6U Expired - Fee Related CN206147599U (zh) | 2015-05-18 | 2016-05-18 | 物理转换后备缓冲器tlb和可配置为支持多个可用虚拟处理元件vpe的处理器 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201620454206.6U Expired - Fee Related CN206147599U (zh) | 2015-05-18 | 2016-05-18 | 物理转换后备缓冲器tlb和可配置为支持多个可用虚拟处理元件vpe的处理器 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9830275B2 (zh) |
EP (1) | EP3096230A1 (zh) |
CN (2) | CN106168930A (zh) |
GB (1) | GB2540255B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10162861B2 (en) * | 2015-09-04 | 2018-12-25 | Celonis Se | Method for the analysis of processes |
US10169407B2 (en) * | 2015-09-04 | 2019-01-01 | Celonis Se | Method for the efficient analysis of process data |
US10296465B2 (en) * | 2016-11-29 | 2019-05-21 | Board Of Regents, The University Of Texas System | Processor using a level 3 translation lookaside buffer implemented in off-chip or die-stacked dynamic random-access memory |
US11106596B2 (en) * | 2016-12-23 | 2021-08-31 | Advanced Micro Devices, Inc. | Configurable skewed associativity in a translation lookaside buffer |
US20190065202A1 (en) | 2017-08-31 | 2019-02-28 | MIPS Tech, LLC | Pointer-size controlled instruction processing |
US10915459B2 (en) | 2018-10-29 | 2021-02-09 | International Business Machines Corporation | Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes |
US10846239B2 (en) * | 2018-11-29 | 2020-11-24 | Marvell Asia Pte, Ltd. | Managing translation lookaside buffer entries based on associativity and page size |
US11080062B2 (en) | 2019-01-12 | 2021-08-03 | MIPS Tech, LLC | Address manipulation using indices and tags |
WO2023183495A1 (en) * | 2022-03-23 | 2023-09-28 | William Robert Reohr | Metamorphosing memory |
CN114595164B (zh) * | 2022-05-09 | 2022-08-16 | 支付宝(杭州)信息技术有限公司 | 在虚拟化平台中管理tlb高速缓存的方法和装置 |
Citations (9)
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US5437016A (en) * | 1991-07-05 | 1995-07-25 | Hitachi, Ltd. | Apparatus and method for translating logical addresses for virtual machines |
US20020144081A1 (en) * | 2001-03-30 | 2002-10-03 | Willis Thomas E. | Method and apparatus including heuristic for sharing TLB entries |
US20080172524A1 (en) * | 2007-01-11 | 2008-07-17 | Raza Microelectronics, Inc. | Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure |
CN101727405A (zh) * | 2008-10-20 | 2010-06-09 | 株式会社东芝 | 虚拟地址高速缓冲存储器和方法以及处理器 |
US20120079479A1 (en) * | 2010-09-27 | 2012-03-29 | James Robert Howard Hakewill | Microprocessor system for virtual machine execution |
CN102662860A (zh) * | 2012-03-15 | 2012-09-12 | 天津国芯科技有限公司 | 用于进程切换的旁路转换缓冲器(tlb)及在其中地址匹配的方法 |
CN103777926A (zh) * | 2012-10-25 | 2014-05-07 | 辉达公司 | 多线程处理单元中的高效存储器虚拟化 |
US20140189333A1 (en) * | 2012-12-28 | 2014-07-03 | Oren Ben-Kiki | Apparatus and method for task-switchable synchronous hardware accelerators |
US20150089116A1 (en) * | 2013-09-26 | 2015-03-26 | Cavium, Inc. | Merged TLB Structure For Multiple Sequential Address Translations |
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US5875464A (en) * | 1991-12-10 | 1999-02-23 | International Business Machines Corporation | Computer system with private and shared partitions in cache |
US5701432A (en) * | 1995-10-13 | 1997-12-23 | Sun Microsystems, Inc. | Multi-threaded processing system having a cache that is commonly accessible to each thread |
US5928352A (en) * | 1996-09-16 | 1999-07-27 | Intel Corporation | Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry |
US6256709B1 (en) * | 1997-06-26 | 2001-07-03 | Sun Microsystems, Inc. | Method for storing data in two-way set associative odd and even banks of a cache memory |
US5854761A (en) * | 1997-06-26 | 1998-12-29 | Sun Microsystems, Inc. | Cache memory array which stores two-way set associative data |
US7003630B1 (en) * | 2002-06-27 | 2006-02-21 | Mips Technologies, Inc. | Mechanism for proxy management of multiprocessor storage hierarchies |
US7017025B1 (en) * | 2002-06-27 | 2006-03-21 | Mips Technologies, Inc. | Mechanism for proxy management of multiprocessor virtual memory |
US6941442B2 (en) * | 2002-08-02 | 2005-09-06 | Arm Limited | Entry lockdown within a translation lookaside buffer mechanism |
US6922766B2 (en) * | 2002-09-04 | 2005-07-26 | Cray Inc. | Remote translation mechanism for a multi-node system |
US7577816B2 (en) * | 2003-08-18 | 2009-08-18 | Cray Inc. | Remote translation mechanism for a multinode system |
US20050055528A1 (en) * | 2002-12-12 | 2005-03-10 | International Business Machines Corporation | Data processing system having a physically addressed cache of disk memory |
US7082508B2 (en) * | 2003-06-24 | 2006-07-25 | Intel Corporation | Dynamic TLB locking based on page usage metric |
US7363463B2 (en) * | 2005-05-13 | 2008-04-22 | Microsoft Corporation | Method and system for caching address translations from multiple address spaces in virtual machines |
US7380068B2 (en) * | 2005-10-27 | 2008-05-27 | International Business Machines Corporation | System and method for contention-based cache performance optimization |
US7822941B2 (en) * | 2006-06-05 | 2010-10-26 | Oracle America, Inc. | Function-based virtual-to-physical address translation |
US7752417B2 (en) * | 2006-06-05 | 2010-07-06 | Oracle America, Inc. | Dynamic selection of memory virtualization techniques |
US7627744B2 (en) * | 2007-05-10 | 2009-12-01 | Nvidia Corporation | External memory accessing DMA request scheduling in IC of parallel processing engines according to completion notification queue occupancy level |
WO2008155851A1 (ja) * | 2007-06-20 | 2008-12-24 | Fujitsu Limited | 演算処理装置、エントリ制御プログラムおよびエントリ制御方法 |
US8180998B1 (en) * | 2007-09-10 | 2012-05-15 | Nvidia Corporation | System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations |
US7917725B2 (en) * | 2007-09-11 | 2011-03-29 | QNX Software Systems GmbH & Co., KG | Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer |
US8443156B2 (en) * | 2009-03-27 | 2013-05-14 | Vmware, Inc. | Virtualization system using hardware assistance for shadow page table coherence |
US8195883B2 (en) * | 2010-01-27 | 2012-06-05 | Oracle America, Inc. | Resource sharing to reduce implementation costs in a multicore processor |
US8239620B2 (en) * | 2010-09-27 | 2012-08-07 | Mips Technologies, Inc. | Microprocessor with dual-level address translation |
US20120096226A1 (en) * | 2010-10-18 | 2012-04-19 | Thompson Stephen P | Two level replacement scheme optimizes for performance, power, and area |
US8738860B1 (en) * | 2010-10-25 | 2014-05-27 | Tilera Corporation | Computing in parallel processing environments |
US8583874B2 (en) * | 2010-12-14 | 2013-11-12 | Lsi Corporation | Method and apparatus for caching prefetched data |
US8615636B2 (en) * | 2011-03-03 | 2013-12-24 | International Business Machines Corporation | Multiple-class priority-based replacement policy for cache memory |
US20120331265A1 (en) * | 2011-06-24 | 2012-12-27 | Mips Technologies, Inc. | Apparatus and Method for Accelerated Hardware Page Table Walk |
WO2013078085A1 (en) * | 2011-11-22 | 2013-05-30 | Mips Technologies, Inc. | Processor with kernel mode access to user space virtual addresses |
US9465748B2 (en) * | 2011-12-30 | 2016-10-11 | Advanced Micro Devices, Inc. | Instruction fetch translation lookaside buffer management to support host and guest O/S translations |
US20140006681A1 (en) * | 2012-06-29 | 2014-01-02 | Broadcom Corporation | Memory management in a virtualization environment |
US20140006747A1 (en) * | 2012-06-29 | 2014-01-02 | Broadcom Corporation | Systems and methods for processing instructions when utilizing an extended translation look-aside buffer having a hybrid memory structure |
-
2015
- 2015-05-18 US US14/715,117 patent/US9830275B2/en active Active
-
2016
- 2016-05-18 EP EP16170082.8A patent/EP3096230A1/en not_active Withdrawn
- 2016-05-18 CN CN201610330320.2A patent/CN106168930A/zh active Pending
- 2016-05-18 GB GB1608709.0A patent/GB2540255B/en not_active Expired - Fee Related
- 2016-05-18 CN CN201620454206.6U patent/CN206147599U/zh not_active Expired - Fee Related
-
2017
- 2017-11-28 US US15/824,613 patent/US10185665B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US5437016A (en) * | 1991-07-05 | 1995-07-25 | Hitachi, Ltd. | Apparatus and method for translating logical addresses for virtual machines |
US20020144081A1 (en) * | 2001-03-30 | 2002-10-03 | Willis Thomas E. | Method and apparatus including heuristic for sharing TLB entries |
US20080172524A1 (en) * | 2007-01-11 | 2008-07-17 | Raza Microelectronics, Inc. | Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure |
CN101727405A (zh) * | 2008-10-20 | 2010-06-09 | 株式会社东芝 | 虚拟地址高速缓冲存储器和方法以及处理器 |
US20120079479A1 (en) * | 2010-09-27 | 2012-03-29 | James Robert Howard Hakewill | Microprocessor system for virtual machine execution |
CN102662860A (zh) * | 2012-03-15 | 2012-09-12 | 天津国芯科技有限公司 | 用于进程切换的旁路转换缓冲器(tlb)及在其中地址匹配的方法 |
CN103777926A (zh) * | 2012-10-25 | 2014-05-07 | 辉达公司 | 多线程处理单元中的高效存储器虚拟化 |
US20140189333A1 (en) * | 2012-12-28 | 2014-07-03 | Oren Ben-Kiki | Apparatus and method for task-switchable synchronous hardware accelerators |
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Non-Patent Citations (2)
Title |
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Also Published As
Publication number | Publication date |
---|---|
GB201608709D0 (en) | 2016-06-29 |
CN206147599U (zh) | 2017-05-03 |
US20180089102A1 (en) | 2018-03-29 |
GB2540255B (en) | 2019-06-26 |
US20160342523A1 (en) | 2016-11-24 |
GB2540255A (en) | 2017-01-11 |
US10185665B2 (en) | 2019-01-22 |
EP3096230A1 (en) | 2016-11-23 |
US9830275B2 (en) | 2017-11-28 |
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Effective date of registration: 20180712 Address after: California, USA Applicant after: Imagination Technologies Ltd. Address before: Hertfordshire Applicant before: Mex Technology Co.,Ltd. Effective date of registration: 20180712 Address after: Hertfordshire Applicant after: Mex Technology Co.,Ltd. Address before: Hertfordshire Applicant before: Harrow Software Co.,Ltd. Effective date of registration: 20180712 Address after: Hertfordshire Applicant after: Harrow Software Co.,Ltd. Address before: Hertfordshire Applicant before: Imagination Technologies Ltd. |
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