CN106160994A - A kind of three-dimensional acoustic wave log data motor synchronizing transmitting device based on blind over-sampling - Google Patents
A kind of three-dimensional acoustic wave log data motor synchronizing transmitting device based on blind over-sampling Download PDFInfo
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- CN106160994A CN106160994A CN201610494346.0A CN201610494346A CN106160994A CN 106160994 A CN106160994 A CN 106160994A CN 201610494346 A CN201610494346 A CN 201610494346A CN 106160994 A CN106160994 A CN 106160994A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0091—Transmitter details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
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- Computer Networks & Wireless Communication (AREA)
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Abstract
The invention discloses a kind of three-dimensional acoustic wave log data motor synchronizing transmitting device based on blind over-sampling, realize the communication between control circuit and Acquisition Circuit by MLVDS the first and second switched circuit.Control circuit issues the parameter command of sampling to Acquisition Circuit by MLVDS first circuit, Acquisition Circuit receives sample command by MLVDS B circuit, and the data that sampling obtained are uploaded to control circuit by MLVDS B circuit, control circuit receives, by MLVDS B circuit, the data that sampling obtains, and finally data is uploaded to ground system.The core of whole device is MLVDS switched circuit, and MLVDS switched circuit realizes the transmission reliable and stable between control circuit and Acquisition Circuit of sample command and data based on blind oversampling technique, meets the requirement to data stability for the three-dimensional acoustic wave logging instrument.
Description
Technical field
The invention belongs to three-dimensional acoustic wave logging technique field, more specifically, relate to a kind of based on the three of blind over-sampling
Dimension sound wave measuring well curve motor synchronizing transmitting device.
Background technology
Three-dimensional acoustic wave well logging is the acoustic logging skill of new generation growing up in cross-dipole acoustic logging technical foundation
Art, its measuring principle is to utilize the current all of i.e. one pole of acoustic measurement pattern, dipole and Stoneley wave, the ripple to various frequency bands
Shape carry out composite measurement with obtain three-dimensional acoustic wave characteristic i.e. compressional wave time difference, shear wave and the Stoneley wave on stratum pit shaft axially, footpath
To with circumferential change, provide complete description to the directionality of formation characteristics.
Traditional acoustic logging is the acoustic signals measuring special frequency band, and the data volume of measurement is less, therefore low speed
Transmission means just can meet the requirement to data transmission bauds.And three-dimensional acoustic wave log measurement data volume is very huge, for number
Reliability requirement according to transmission is very high.
Currently, the physical dimension of three-dimensional acoustic wave logger has particular/special requirement, and columned instrument internal space extremely has
Limit, and need the quantity connecting up more, include power bus, LVDS order wire, LVDS data wire, LVDS clock line, answer
Position holding wire, startup acquisition line, and circuit connection quantity between Acquisition Circuit and control circuit of closely popping one's head in is restricted.If
Use the three-dimensional acoustic wave high speed serial transmission technology based on blind over-sampling data recovery technique, both can solve bus location, again
Well solve the limited problem of instrument space.
Content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, a kind of three-dimensional acoustic wave well logging based on blind over-sampling is provided
Data motor synchronizing transmitting device, utilizes blind over-sampling serial data recovery technology, enables three-dimensional acoustic wave log data motor synchronizing
High-speed transfer.
For achieving the above object, a kind of three-dimensional acoustic wave log data motor synchronizing transmission based on blind over-sampling of the present invention
Device, it is characterised in that include:
One control circuit, uses ICP/IP protocol to realize that control circuit communicates with the Ethernet of ground system, receives
The order that ground system issues, and this order is issued to MLVDS interchanger by the RS-485 interface based on Modbus agreement；
Meanwhile, control circuit uses the SPI controller with DMA function to obtain three-dimensional acoustic wave log data from MLVDS switched circuit, and
Send to ground system；
One MLVDS switched circuit, is divided into first, second two parts, uses high-speed bus to be attached between two parts；First part is born
The order that control circuit is issued by duty is sent to second part, and then configuration Acquisition Circuit；Second part is responsible for obtaining Acquisition Circuit
Three-dimensional acoustic wave log data be sent to first part, and then upload to control circuit and ground system；
Log data is in transmitting procedure, and MLVDS switched circuit carries out string according to MLVDS electrical standard to log data and turns
And standardize and BPRZ decoding, and blind oversampler is used to obtain the clock information that log data transmitting-receiving needs；
One Acquisition Circuit, is used for receiving the order that the first part of MLVDS circuit issues, and recycles FPGA resolve command,
To corresponding sampling parameter；Control resolution be the high-precision adc of 24 according to this sampling parameter to signal sampling,
Obtain three-dimensional acoustic wave log data, then three-dimensional acoustic wave log data is stored in the both-end RAM of FPGA, and be uploaded to MLVDS
The second part of switched circuit.
Further, first, second two parts circuit of described MLVDS switched circuit all contains:
One over-sampling circuit, the order that use multi-phase clock d type flip flop sampling control circuit issues or Acquisition Circuit upload
Three-dimensional acoustic wave log data, and be sent to the preliminary restoring circuit of data；
One preliminary data restoring circuit, after receiving the data that over-sampling circuit exports, and produces the preliminary recovery of 1
Data and two signals of add, drop；Wherein, the value of add, drop is 1 or 0, represents that when add value is 1 generation data are lost
Lose, represent generation data-reusing when drop value is 1, represent the data of preliminary recovery when the value of add, drop is 0
Correctly；
One data correction circuit, for the data tentatively recovered being moved in the shift register that bit wide is 2N+1, displacement
Register root shifts according to the value of add and drop；
If the i-th bit of shift register is for recovering data, N position is the recovery data of acquiescence；So when add is 1, move
Bit register moves to right two, and shift register active position moves to right one, and now i+1 position is the data recovering；Work as drop
When being 1, shift register shifts, and shift register active position moves to left one, now the i-th-1 number for recovering
According to；When add and drop is 0, shift register moves to right one, and the active position of shift register keeps constant；Finally handle
The data of shift register active position are as the output of blind over-sampling.
The goal of the invention of the present invention is achieved in that
The present invention, based on the three-dimensional acoustic wave log data motor synchronizing transmitting device of blind over-sampling, is exchanged by MLVDS first and second
Circuit realizes the communication between control circuit and Acquisition Circuit.Control circuit issues the parameter of sampling by MLVDS first circuit
Order receives sample command to Acquisition Circuit, Acquisition Circuit by MLVDS B circuit, and the data that sampling is obtained are passed through
MLVDS B circuit is uploaded to control circuit, and control circuit receives, by MLVDS B circuit, the data that sampling obtains, finally number
According to being uploaded to ground system.The core of whole device is MLVDS switched circuit, and MLVDS switched circuit is based on blind over-sampling skill
Art realizes the transmission reliable and stable between control circuit and Acquisition Circuit of sample command and data, meets three-dimensional acoustic wave well logging
The requirement to data stability for the instrument.
Meanwhile, the present invention also has following beneficial based on the three-dimensional acoustic wave log data motor synchronizing transmitting device of blind over-sampling
Effect:
(1), the three-dimensional acoustic wave log data recovery device based on oversampling technique, is a kind of self synchronous data transmission moulds
Type, the i.e. transmitting terminal at MLVDS circuit only send data or order, but comprise the information of tranmitting data register in data or order,
Receiving terminal at MLVDS circuit carries out over-sampling and recovers data or order；Therefore this device only devise MLVDS data wire and
Order wire, eliminates MLVDS clock line, reduces circuit connection with maximum possible.
(2), the three-dimensional acoustic wave logging instrument log data amount that Acquisition Circuit gathers in real work is very big, needs data
Receiver module guarantees to receive the accuracy of data；Oversampling technique solves this problem very well, and its technological core is MLVDS electricity
The transmitting terminal on road does not needs to issue the receiving terminal to MLVDS circuit for the clock, and therefore, receiving terminal is when receiving and recovering data, no
Need to consider transmitting terminal and the nonsynchronous problem of receiving terminal clock that clock causes after issuing through the clock line of distance, thus
The problem well solving the recovery corrupt data causing because clock is asynchronous, it is ensured that the reliability of data.
Brief description
Fig. 1 is the three-dimensional acoustic wave log data motor synchronizing transmitting device schematic diagram based on blind over-sampling for the present invention；
Fig. 2 is over-sampling sequential chart and over-sampling synchronous circuit figure；
Fig. 3 is preliminary data restoring circuit schematic diagram；
Fig. 4 is sequential chart when loss of data, multiplexing, mistake；
Fig. 5 is the schematic diagram of data correction module；
Fig. 6 is that shift register carries out shifting schematic diagram according to the value of add_drop.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described, in order to those skilled in the art is preferably
Understand the present invention.Requiring particular attention is that, in the following description, when known function and design detailed description perhaps
When can desalinate the main contents of the present invention, these are described in and will be ignored here.
Embodiment
Describe for convenience, first the relevant speciality term occurring in detailed description of the invention illustrated:
MLVDS (Multipoint low Voltage Differential Signaling): multiple spot low voltage difference is believed
Number；
TCP/IP (Transmission Control Protocol/Internet Protocol): network communication protocol；
Modbus: a kind of industrial Fieldbus protocols；
The standard of the electrical characteristic of the driver in RS-485: one definition balance digital multi-drop system and receiver；
DMA (Direct Memory Access): direct memory access；
BPRZ (Bipolar Return-to-Zero): bipolarity return-to zero system；
FPGA (Field-Programmable Gate Array): field programmable gate array；
RAM (Random-Access Memory): random access memory；
Fig. 1 is the three-dimensional acoustic wave log data motor synchronizing transmitting device schematic diagram based on blind over-sampling for the present invention.
In the present embodiment, as it is shown in figure 1, a kind of three-dimensional acoustic wave log data motor synchronizing based on blind over-sampling of the present invention
Transmitting device, mainly includes control circuit, MLVDS switched circuit and Acquisition Circuit.
Control circuit, uses ICP/IP protocol to realize that control circuit communicates with the Ethernet of ground system, receives ground
The order that plane system issues, and this order is issued to MLVDS switched circuit by the RS-485 interface based on Modbus agreement,
Wherein, the order that ground system issues specifically includes that sampling number and the sampling period etc. of three-dimensional acoustic wave；Meanwhile, control circuit
Use the SPI controller with DMA function to obtain three-dimensional acoustic wave log data from MLVDS switched circuit, and send to ground system
System.
MLVDS switched circuit, as it is shown in figure 1, be divided into first, second two parts, uses high-speed bus to be attached between two parts,
And all contain:
Over-sampling circuit, the order that use multi-phase clock d type flip flop sampling control circuit issues or Acquisition Circuit upload
Three-dimensional acoustic wave log data, and it is sent to the preliminary restoring circuit of data；
Preliminary data restoring circuit, is used for receiving the data of over-sampling circuit output, and produces the preliminary recovery data of 1
With two signals of add, drop；Wherein, the value of add, drop is 1 or 0, represents generation loss of data when add value is 1,
Represent generation data-reusing when drop value is 1, represent the data of preliminary recovery when the value of add, drop is 0 just
Really；
Data correction circuit, for moving into the data tentatively recovered in the shift register that bit wide is 2N+1, displacement is posted
Storage shifts according to the value of add and drop；
If the i-th bit of shift register is for recovering data, N position is the recovery data of acquiescence；So when add is 1, move
Bit register moves to right two, and shift register active position moves to right one, and now i+1 position is the data recovering；Work as drop
When being 1, shift register shifts, and shift register active position moves to left one, now the i-th-1 number for recovering
According to；When add and drop is 0, the active position of shift register keeps constant；Finally shift register active position
Data are as the output of blind over-sampling；
Wherein, the order that first part is responsible for issuing control circuit is sent to second part, and then configuration Acquisition Circuit；Second portion
Divide the three-dimensional acoustic wave log data being responsible for obtaining Acquisition Circuit to be sent to first part, and then upload to control circuit and ground system
System；
Log data is in transmitting procedure, and MLVDS switched circuit carries out specification according to MLVDS electrical standard to log data
Change and BPRZ coding, and use blind oversampler to obtain the clock information that log data transmitting-receiving needs；
Acquisition Circuit, is used for receiving the order that the first part of MLVDS circuit issues, and recycles FPGA resolve command, obtains
Corresponding sampling parameter；Control resolution be the high-precision adc of 24 according to this sampling parameter to signal sampling,
To three-dimensional acoustic wave log data, then three-dimensional acoustic wave log data is stored in the both-end RAM of FPGA, and is uploaded to MLVDS friendship
Change the second part of circuit.
Fig. 2 is over-sampling sequential chart and over-sampling synchronous circuit figure.
In the present embodiment, as shown in Fig. 2 (b), implementing of over-sampling circuit is to be completed by 4 d type flip flops,
The first row that this 4 d type flip flops are positioned in Fig. 2 (b), as shown in Fig. 2 (a), 4 multi-phase clock Clk0, Clk90, Clk180,
The sampling of the three-dimensional acoustic wave log data of order or the Acquisition Circuit upload issuing control circuit is completed under the triggering of Clk270,
Obtain 4 bit data.In order to improve the precision of sampling, the time delay of input data signal to this 4 d type flip flops is consistent as far as possible,
It is thus desirable to enter row constraint to the maximum deflection time of input data signal, and the position of sample register to be leaned on as far as possible
Nearly input data pin.In the present embodiment, the phase of each clock 90 degree, input data through global clock pin with
Guarantee the uniformity of trigger time delay.
It owing to the sampled value of 4 d type flip flops obtains under different clock-domains, thus is being used to detect edge
During change, it is necessary to standard time clock clk0, they are synchronized.From Fig. 1 (b) it can be seen that the sample register of each passage
Output all have passed through 3 triggers, so can eliminate the metastable issues of sample register, middle two triggers then increase
The data setup time adding.
Fig. 3 is preliminary data restoring circuit schematic diagram.
In the present embodiment, as it is shown on figure 3, preliminary data restoring circuit receives 4 output data of over-sampling circuit, produce
Bear the preliminary add_drop signal recovering data and two of 1.Marginal detector by 4 current over-sampling data and
Front over-sampling data D [3], finds out that interval that input data change in 4 adjacent multi-phase clocks are interval.
The marking signal that marginal detector sends 4 determines most preferably to phase selector, phase detectors according to this 4 bit flag signal
Sampling location.If 4 bit flag signals are 0, then mean that input data do not change, then sampling location and front once protect
Hold consistent.A work in 4 over-sampling data of sampling location signal behavior that multiplexer exports according to phase selector
For the preliminary data recovered and deliver to data correction module.Error detector is according to current sampling location and last sampling
Position judges that whether the data that current preliminary is recovered are correct, exports add_drop signal to data correction module simultaneously.Data
The time that two compensation of delay of signal marginal detector and phase selector synchronization over-sampling data are consumed to MUX.
Table 1 is the decision rule that sampling clock and sampled data select in single sampling window.
Table 1
Preliminary data recovery module, according to 4 the over-sampling data receiving in single sampling window, obtains them and changes
Position simultaneously determines sampling phase and sampled data according to above-mentioned decision rule.Sample window is defined as a sampling clock cycle,
Cycle, next clk0 rising edge was end position with the rising edge of clk0 as original position.In table 1 as a example by case2,
The change of discovery input data at the rising edge of clk0, then select clk270 to be sampling clock, because this moment is closest
The center of input data, thus obtain sampled data D [3] in this sampling window.
Fig. 4 is sequential chart when loss of data, multiplexing, mistake.
If there is deviation in clock frequency, input change location in single sample window for the data can monotonously to the left or
Move right.Accumulation over time, it will cross over the border of sample window.In this case data-reusing or data will be caused
Losing, now preliminary data recovery module by activation add_drop signal and is sent to data correction module.
When the clock frequency sending is less than the clock frequency receiving, data can be occurred to lose at the preliminary data recovered
Lose.As shown in Fig. 4 (a), the change edge inputting data in sample window SW2 is case3, and inputs the change of data in sample window SW3
Change edge is case2, obtains the data of the preliminary recovery of the D [0] in SW2 and the D [3] in SW3, SW2 and SW3 according to decision rule
Middle data will be lost.
When the clock frequency sending is higher than the clock frequency receiving, data can be occurred multiple at the preliminary data recovered
With.As shown in Fig. 4 (b), adjudicate sampled data D [3] obtaining and sample window SW3 adjudicate in sample window SW2 and sampled
Data D [0] are same input data, cause data-reusing.
The shake being simultaneously entered data will also result in loss or the multiplexing of data.In order to solve this class problem, such as Fig. 4
C, shown in (), error detector activates add_drop signal while output preliminary recovery data.Add_drop signal only can be
Sampling location sends specific activation after changing, and only lasts for a cycle, and when inputting data and not changing, add_
Drop signal will not be activated, and sampling location can keep constant.
Fig. 5 is the schematic diagram of data correction module.
As it is shown in figure 5, data correction module moves into the preliminary data recovered in the shift register that bit wide is 2N+1, and
Recover data queue adds according to add and drop signal preliminary or remove a data.The bit wide of shift register takes
Certainly in the exemplary frequency deviation values of the size of maximum data packet and transmitter and receiver.The value of shift register N position is acquiescence
Recovering data, due to the existence of frequency departure, the position that accumulation over time recovers data can move to left or move to right, and therefore adopts
Indicate the position of shift register output significance bit with outgoing position selector.
As shown in Figure 6, shift register shifts according to the value of add_drop.Show loss of data when add is 1,
The data lost necessarily recover negating of data for current preliminary, because activating the precondition that add is 1 is data changes to be had
Along generation.Therefore, after shift register moves to right two, its high two should move into～prd and prd (prd and～prd table respectively successively
Show current sample values and current sample values value of the inverted).It is 1 to be to show data-reusing as drop, at the beginning of being therefore currently entered
Step recovers data invalid to be needed to abandon, and shift register does not shifts.Show the data tentatively recovered when add/drop is 0
Correctly, shift register moves to right one, and highest order moves into prd.
If the i-th bit of present shift register is the data recovered, N position is the recovery data of acquiescence；When add is 1,
Shift register moves to right two, and shift register active position need to move to right one, as shown in the 2nd row in Fig. 6, and now i+1 position
For the data recovering.When drop is 1, shift register shifts, and active position need to move to left one, in Fig. 6
Shown in 3rd row, now the i-th-1 data for recovering.When add and drop is 0, shift register moves to right one, has
Effect position keeps constant, as shown in the 4th row in Fig. 6.
When active position exceeds the scope of shift register, data are recovered to make a mistake.In order to avoid this problem,
The bit wide of shift register must be sufficiently large, and its size is decided by the size of maximum frame data and transmission and reception clock frequency
Deviation.
N=frame_sizemax×Δfoffset+Nmargin
In three-dimensional acoustic wave well logging, single channel maximum data number is 600, and maximum data bit wide is 24, through 8B/10B coding
After add other overheads to obtain maximum data packet being 18060bits.The maximum frequency deviation sending and receiving is +/-
500ppm, the value being calculated N is 19, it is contemplated that the shake of input data, arranging margin value is 3.Therefore N in the present embodiment
Size is 22, a length of the 45 of shift register.
From the above analysis, the shake of sampling clock and input data signal may result in the mistake that data are recovered.
Shake is generally divided into Random jitter and this two big class of deterministic jitter.The former is difficult to predict, generally assumes that and presents Gaussian Profile,
Its peak-to-peak value does not has border, does not therefore consider in the design.Deterministic jitter be can reappear, foreseeable fixed
When shake, this shake peak-to-peak value there is bound, it particularly may be divided into periodic jitter, and duty cycle dither is related with data
Shake.Owing to working environment, particular hardware and the coded system phase taked are depended in duty cycle dither and data dependent jitter
Close, here do not consider.In order to ensure the correctness that data are recovered, sampling clock must is fulfilled in a sampling period T
The data adopted can not be less than 3 and can not be more than 5, and the therefore shake of sampling clock not can exceed that 0.25T.
Requiring that input data have enough change edges based on the data reconstruction method of over-sampling, specific requirement is for adopting
In sample clock skew 0.25T, input data at least to change once, is otherwise likely to result in loss of data or multiplexing cannot be tested
Measure, cause Data reception errors.A kind of it may happen that situation be when transmitter clock frequency less than receiver when
During clock frequency rate, if certain moment optimal judgement sampling clock is clk0, after 0.25T, inputs data do not change, then most preferably
Judgement sampling location may become clk180, has striden across the region that sampling location is clk270, thus has counted in causing this region
Being not detected according to loss, the data receiving necessarily make a mistake.
In the present embodiment, Acquisition Circuit and control circuit all use the product of Xilinx company Spartan3E series, profit
The logic control completing with FPGA, serial data is recovered function and is used VerilogHDL hardware description language to realize, develops flat
Platform is ISE13.2.
Although to the present invention, illustrative detailed description of the invention is described above, in order to the technology of the art
Personnel understand the present invention, the common skill it should be apparent that the invention is not restricted to the scope of detailed description of the invention, to the art
From the point of view of art personnel, as long as various change limits and in the spirit and scope of the present invention of determination in appended claim, these
Change is apparent from, and all utilize the innovation and creation of present inventive concept all at the row of protection.
Claims (4)
1. the three-dimensional acoustic wave log data motor synchronizing transmitting device based on blind over-sampling, it is characterised in that include:
One control circuit, uses ICP/IP protocol to realize that control circuit communicates with the Ethernet of ground system, receives ground
The order that system issues, and this order is issued to MLVDS interchanger by the RS-485 interface based on Modbus agreement；With
When, control circuit uses the SPI controller with DMA function to obtain three-dimensional acoustic wave log data from MLVDS switched circuit, concurrently
Deliver to ground system；
One MLVDS switched circuit, is divided into first, second two parts, uses high-speed bus to be attached between two parts；First part be responsible for by
The order that control circuit issues is sent to second part, and then configuration Acquisition Circuit；Second part is responsible for obtain Acquisition Circuit three
Dimension sound wave measuring well curve is sent to first part, and then uploads to control circuit and ground system；
Log data is in transmitting procedure, and MLVDS switched circuit carries out string according to MLVDS electrical standard to log data and turns and advise
Generalized and BPRZ decoding, and use blind oversampler to obtain the clock information that log data transmitting-receiving needs；
One Acquisition Circuit, is used for receiving the order that the first part of MLVDS circuit issues, and recycles FPGA resolve command, obtains phase
The sampling parameter answered；Control resolution rate be the high-precision adc of 24 according to this sampling parameter to signal sampling,
To three-dimensional acoustic wave log data, then three-dimensional acoustic wave log data is stored in the both-end RAM of FPGA, and is uploaded to MLVDS friendship
Change the second part of circuit.
2. a kind of three-dimensional acoustic wave log data motor synchronizing transmitting device based on blind over-sampling according to claim 1, its
Being characterised by, first, second two parts of described MLVDS switched circuit are all containing a blind over-sampling module:
One over-sampling circuit, the order that use multi-phase clock d type flip flop sampling control circuit issues or Acquisition Circuit uploads three
Dimension sound wave measuring well curve, and it is sent to the preliminary restoring circuit of data；
One preliminary data restoring circuit, after receiving the data of sample circuit output, and produce 1 preliminary recover data and
Two signals of add, drop；Wherein, the value of add, drop is 1 or 0, represents generation loss of data when add value is 1, when
Drop value represents generation data-reusing when being 1, represent that when the value of add, drop is 0 the data of preliminary recovery are correct；
One data correction circuit, for the data tentatively recovered being moved in the shift register that bit wide is 2N+1, shift LD
Device shifts according to the value of add and drop；
If the i-th bit of shift register is for recovering data, N position is the recovery data of acquiescence；So when add is 1, displacement is posted
Storage moves to right two, and shift register active position moves to right one, and now i+1 position is the data recovering；When drop is 1
When, shift register shifts, and shift register active position moves to left one, now the i-th-1 data for recovering；
When add and drop is 0, shift register moves to right one, and the active position of shift register keeps constant；Finally displacement
The data of register active position are as the output of blind over-sampling.
3. a kind of three-dimensional acoustic wave log data motor synchronizing transmitting device based on blind over-sampling according to claim 1, its
Being characterised by, the order that described ground system issues specifically includes that sampling number and the sampling period of three-dimensional acoustic wave.
4. a kind of three-dimensional acoustic wave log data motor synchronizing transmitting device based on blind over-sampling according to claim 2, its
Being characterised by, described multi-phase clock d type flip flop includes 4 d type flip flops, 4 multi-phase clock Clk0, Clk90, Clk180,
The sampling of the three-dimensional acoustic wave log data of order or the Acquisition Circuit upload issuing control circuit is completed under the triggering of Clk270,
Obtain 4 bit data.
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| CN107288624A (en) * | 2017-07-28 | 2017-10-24 | 电子科技大学 | A kind of underground high speed data bus device suitable for acoustic logging instrument |
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| WEI ZHANG ,YIBING SHI, YANJUN LI: "An Effective Detection Method Based on IPSO-WNN for Acoustic Telemetry Signal of Well Logging While Drilling", 《2014 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE, ELECTRONICS AND ELECTRICAL ENGINEERING》 * |
| ZHANG WEI, SHI YIBING, LI YANJUN: "Design of Acoustic Wireless Remote Transmission System for Logging-While-Drilling Data", 《THE 11TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107288624A (en) * | 2017-07-28 | 2017-10-24 | 电子科技大学 | A kind of underground high speed data bus device suitable for acoustic logging instrument |
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| CN106160994B (en) | 2019-04-02 |
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