CN106160753B - Weight multi-bit flipping LDPC decoding method suitable for SSD - Google Patents
Weight multi-bit flipping LDPC decoding method suitable for SSD Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
Abstract
The invention discloses a weight multi-bit flipping LDPC decoding method suitable for SSDThe first step is based on the read channel soft information Y ═ Y1,y2,y3,...,yN]Setting a codeword bit flipping weight factor U ═ U1,u2,u3,...,uN],ui＝α|yiL, |; the second step is to calculate the codeword bit reliability factor Ei(ii) a And thirdly, carrying out overturn decoding and updating the code word bit overturn weight factor according to the overturn rule. The invention effectively improves the throughput in the high-speed storage system; the global search operation with the maximum reliability factor of the prior bit flip search in the decoding process is overcome, and the error correction capability is improved; meanwhile, the restriction between the error correction capability and the operation speed is optimized, and the parallel decoding is effectively realized.
Description
Technical Field
The invention relates to a weight multi-bit flipping LDPC decoding method suitable for SSD.
Background
With the rapid development of information systems in various fields of the internet and society, data is growing explosively, so that a large-capacity storage system faces huge challenges in the aspects of reliability, read-write performance and the like. Solid-State Drive (SSD) using NAND Flash as a storage medium has excellent characteristics of high performance, low power consumption, and the like, and has been gradually applied to data storage in a plurality of fields such as internet, military, vehicle-mounted, and aviation, and provides more development opportunities for constructing a large-capacity storage system. The adoption of Flash media to construct a high-fault-tolerance and high-efficiency high-capacity solid-state storage system is one of the main development trends of storage systems. Although researchers have conducted various researches on solid state disks and achieved a series of related results, the Error Correction coding technology of the solid state storage system still continues to be the traditional Error Correction Code (ECC) technology of the traditional magnetic storage system, and the related researches on the Error characteristics of Flash media and solid state disks are not extensive and intensive.
Meanwhile, with the continuous expansion of cloud computing applications, more IT manufacturers establish their own data centers, and not only internet enterprises, but also some traditional IT manufacturers begin to emphasize the development of the data centers. Due to the fact that the data center is large in scale, energy consumption cost caused by tens of thousands of traditional magnetic medium storage devices is large, and the problem of bottleneck of I/O performance is prominent, the solid state disk provides wide market space for the solid state disk, and the characteristics of low power consumption, high performance, low noise and the like of the solid state storage system provide larger space for development of a large-scale data center, and the solid state disk becomes a preferred configuration of a data center or cloud computing in the future. Therefore, the adoption of a high-performance solid-state storage system to construct a large-scale data center is one of the main development trends of the storage system in the future. Research reports on IDC predict that sales of solid-state storage systems will increase at 105% per year from 2010 (24 billion dollars) and will reach 100 billion dollars per year, being evaluated by IDC as one of ten new technologies in the storage field. Meanwhile, IDC research data show that the total amount of global data storage will increase to 2.16ZB in 2014.
Currently, NAND Flash is widely used in various fields related to storage, plays a key role as a storage medium with excellent performance, especially in application of a solid state disk, but is limited by the internal structural features of NAND Flash, and how to improve and ensure the reliability of NAND Flash is one of the major issues of Flash memory research. The NAND Flash solves the problem of bit errors through an error correcting Code ECC, RS codes (Reed-Solomon) and BCH codes (Bose-Chauhuri-Hocquenghem) are used as error correcting codes [2] [3] in the development process, however, as the Flash technology progresses, the bits stored in a Single Flash memory Cell increase, the storage Density is greatly increased from the first SLC (Single-Level-Cell) to the MLC (Multi-Level-Cell) and TLC (thin-Level-Cell), the storage space is continuously reduced, particularly, the technology reaches below 25nm, the NANDFlash bit error rate is rapidly increased, the traditional error correcting Code mechanism can not meet the increasingly developed Flash memory requirements, and the Low-Density-Parity-Check Code (LDPC) is widely applied in the field of channel coding as an error correcting Code with the characteristics of excellent error correcting performance, parallel quick decoding and the like, LDPC codes have also been adopted in recent years in the field of flash error correction. The NAND Flash memory has the characteristics of high storage density, low cost and the like, and the requirements of high code rate, long code, high performance and low complexity are provided for the LDPC code. Therefore, the research on a new high-efficiency decoding technology suitable for the NAND Flash is of great significance.
In a word, as the Flash technology is deep to 25nm or below, and the structure is from SLC to MLC to TLC, the storage capacity is larger and larger, the data error rate is higher and higher, but the data fault tolerance of the current solid-state storage system still depends on some error correction technologies of the traditional magnetic storage system, which does not completely conform to the technical characteristics of the solid-state storage medium, and the performance advantage is difficult to be fully exerted. Therefore, researching the error correction coding technology which accords with the random error characteristic of the solid-state storage system and researching and developing a high-fault-tolerance error correction coding chip have very important significance for ensuring the reliability of the large-capacity solid-state storage system.
An LDPC Code, i.e., Low Density Parity Check Code, is a linear block Code defined based on a Parity Check matrix proposed by Gallager in the last 60 th century, and its name is obtained because the Check matrix contains a small number of non-zero elements. LDPC codes have been the focus of research in recent years due to their advantages of high coding rate, fast decoding speed, few undetectable errors, simple hardware implementation, and low error occurrence platform.
Bit-Flipping is a representative hard decoding method of LDPC, and has a plurality of versions, and the basic idea is to perform a Flipping decision based on the hard decoding proposed by Gallager according to the comparison between the number of unsatisfied equations and the number of satisfied equations of information bits. The Bit-Flipping decoding process only has simple operation, and is characterized by low hardware overhead, low computation complexity, high operation speed, relatively poor error correction performance and slow decoding convergence speed.
Zhao improves the traditional Bit-Flipping method, called NBF (Novel Bit-Flipping) method, which solves the problem of global search in the decoding process of the traditional method, and adopts a method of dynamically changing a Flipping threshold value, and experiments show that the method can effectively improve the decoding speed and simultaneously save the hardware design cost, but has the defect of further loss of error correction performance.
Yu PengHu et al propose a decoding strategy based on a main error interval of a Flash memory according to the characteristics of errors of NAND Flash, and effectively distinguish error bits from correct bits through the error interval strategy.
Zhang T et al proposed a Hybrid Hard/Soft decision decoding strategy method according to the error characteristics of different stages of the life cycle of a flash memory, and because the error rates of different stages of the life cycle of the flash memory are different, a Hybrid decoding strategy is proposed, a Hard decision Bit-Flipping or Min-Sum decoding method is adopted in the early stage of the life cycle, and when the decoding is unsuccessful, a high-precision decision Min-Sum decoding method is called, so that the whole decoding error correction capability and the decoding speed are improved to a certain extent, but the obvious defects are that the hardware overhead is large, and the decoding performance is improved to a limited extent.
Wu and the like adopt different correction factors to correct the minimum sum method according to whether a check equation is satisfied or not, and obtain better decoding performance than that of the minimum sum method adopting a single correction factor under the condition of low signal-to-noise ratio, but the method has higher floor effect when being applied to LDPC codes with small code length, namely, the error rate of more than 10-6 orders of magnitude still exists under the condition of higher signal-to-noise ratio.
As described above, these researchers have studied the decoding method of the LDPC code from different aspects, and under specific conditions, the decoding performance is relatively good.
At present, decoding technologies in the LDPC error correcting code mainly comprise Soft decoding Soft-decision, hard decoding hard-decision and mixed decoding. Soft-decision takes Soft information as input, and carries out decoding through operations of summation, multiplication, even logarithm and the like, and the Soft-decision has the characteristics of strong error correction capability, high decoding parallelism, high convergence speed and high hardware realization difficulty, but is close to the Shannon limit. In a high-speed storage system, because high-precision soft information is needed, delay caused by accurately reading the voltage value of a storage unit occupies most of time spent in the whole decoding process, the improvement of decoding speed is restricted, and the improvement of throughput is difficult.
The Hard-precision decoding takes simple 0 and 1 as input, and the decoding process only has simple integer operation, so the Hard-precision decoding method has the characteristics of low hardware overhead, low calculation complexity and high operation speed. However, it has a fatal defect, poor error correction capability and slow decoding convergence rate for the following reasons: firstly, based on an exclusive or operation check matrix, in the decoding process, error syndrome information is introduced by even number of bit inversion, and the error syndrome information is propagated in the subsequent decoding process, so that the syndrome information is only depended on, the decoding is difficult to be accurate, and the correct convergence is difficult; secondly, the process of searching the maximum reliability factor in the middle bit turning mode of hard-decision decoding is global, and the global searching process enables the decoding to be pseudo-parallel decoding; third, the hard decision operation may lose most of the channel information, resulting in a low utilization of the channel information.
Hybrid decoding is an ideal decoding method because it combines soft information of soft-decision and decoding speed of hard-decision. The method effectively improves the decoding error correction capability by introducing the channel soft information, and has little difference with the BF method in the decoding calculation complexity. The decoding method of the invention is improved and proposed on the basis of the method.
Recently, a series of research results on improving the error correction performance and convergence rate of BF hybrid decoding methods have been proposed, such as Weighted BF (WBF), Modified WBF (MWBF), Combined Modified WBF (CMWBF), Parallel WBF (PWBF), and robust bit BF (CBBF), which are also called soft information Weighted bit flipping based decoding methods. Because improving the convergence rate of the decoding method and reducing the average iteration number of decoding is an effective method for improving the throughput rate of the decoder, the improvement of the parallelism of decoding is realized, the hardware cost of decoder design is reduced, and the key of decoder research is to effectively ensure that the decoder has higher error correction capability.
The basic decoding process of the existing various conventional BF and WBF decoding methods is shown in fig. 1, and it can be seen that each iterative decoding process includes three main steps: step1 for all bits of each given hard-decision codeword, calculating confidence information from the check equation for each bit, set to Ei(ii) a Step 2 Global search has maximum Ei(or a maximum of q Ei) (ii) a Step 3 flips all with maximum Ei(or a maximum of q Ei) Corresponding bits. Wherein Step 3 can be executed after Step 2 completes the global search, and the decoder needs to store all E in the processiAnd the serial design, which is executed asynchronously, limits the decoding speed.
As can be seen from the analysis of FIG. 1, the existing various improved BF or WBF methods involve a global search operation (search with maximum E) in each iterative decoding processiBit of) and then the weight flips the particular bit. Such serial design would result in a number of disadvantages in the decoder design process: (i) the decoder needs to store a large amount of intermediate data, resulting in a large amount of silicon cache space overhead; (ii) it should be noted that the global search operation must be completed first in the decoding process of the decoder, and then the flip operation can be performed, so that parallel decoding is hindered, resulting in a limited decoding throughput. In order to solve the above two defects, especially, decoding cannot be performed in parallel, and the weight of the existing weight WBF decoding method cannot be updated, so that decoding easily enters the trapping of the same bit cycle inversion, which seriously affects the decoding convergence speed.
Disclosure of Invention
The invention aims to solve the technical problem of providing a weight multi-bit flipping LDPC decoding method suitable for SSD aiming at the defects of the prior art.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a weight multi-bit flipping LDPC decoding method suitable for SSD comprises the following steps:
1) initializing a non-negative parameter factor alpha and a codeword bit flipping weight sequence U ═ U1,u2,u3,...,un]，
ui＝α|yiIn which the maximum number of iterations K is setmaxThe initial iteration number k is 1;
i＝1,2,…n；
2) obtaining a syndrome S according to the initial decision sequence Z by calculation, wherein S is ZHTIf S is 0 or K reaches the maximum number of iterations KmaxIf yes, stopping decoding and outputting a decoding result; if none of the above conditions is met, calculating a reliability intermediate parameter factor wm：
Wherein N (m) ═ n: hm,n＝1}；hm,nIs an element in the check matrix H, H ═ Hm,n) M is more than or equal to 1and less than or equal to M, N is more than or equal to 1and less than or equal to N, M is a row of the check matrix, and N is a code length; y isnSoft information for the nth channel;
3) calculating a codeword bit confidence factor En：
Wherein M (n) ═ m: hm,n＝1}；smRepresents an element in syndrome S;
4) according to the code word bit credibility factor EnAnd according to a set turning rule, turning the bit which is determined as the error bit to obtain a turned sequence Zk；
5) According to S ═ ZkHTCalculating a syndrome S; if S obtained by current calculation is 0, or the iteration number K reaches K +1 > KmaxStopping iterative decoding, and outputting a current decoding result; otherwise, returning to the step 3), and adding 1 to the k value.
The acquisition process of the non-negative parameter factor alpha comprises the following steps: the experiment is carried out by using code words with the length of N being 2KB and the code rate of R being 90 percent, the initial error rate of the code words RBER being 0.01and RBER being 0.007, and d is respectively taken by the weight of the check matrixv＝3、d v4 and d v5, the maximum iteration number upper limit KmaxWhen check matrix column number d is 100vWhen the value is 3, the value of alpha is [0.825,0.85 ]](ii) a When check matrix column weight dvWhen the value is 4, the value of alpha is [0.85,0.87 ]5](ii) a When check matrix column weight dvWhen the value is 5, the value of alpha is [0.9,0.95 ]]. Compared with the prior art, the invention has the beneficial effects that: the invention effectively improves the throughput in the high-speed storage system; the global search operation with the maximum reliability factor of the prior bit flip search in the decoding process is overcome, and the error correction capability is improved; meanwhile, the restriction between the error correction capability and the operation speed is optimized, and the parallel decoding is effectively realized.
Drawings
FIG. 1 is a basic decoding flow chart of various conventional BF and WBF decoding methods;
FIG. 2 is a flowchart illustrating WMBF decoding according to the present invention;
FIG. 3 is a diagram of a WMBF decoder Flip Logic module according to the present invention;
FIG. 4 is a comparison graph of error correction capability of the standard WBF decoding method and the method of the present invention when the column weight is 5;
FIG. 5 is a comparison graph of error correction capability of the standard WBF decoding method and the method of the present invention when the column weight is 3;
FIG. 6 is a comparison graph of the average number of iterations for decoding in the standard WBF decoding method and the method of the present invention when the column weight is 5 according to the present invention;
FIG. 7 is a comparison graph of average iterative times for decoding by the standard WBF decoding method and the method of the present invention when the column weight is 3 according to the present invention;
fig. 8 is a graph of α value and decoding success rate corresponding to RBER 0.01;
fig. 9 is a graph of α value and decoding success rate corresponding to RBER 0.007.
Detailed Description
The whole decoding process of the WMBF method is roughly divided into three steps, wherein the first step is to read the channel soft information Y ═ Y1,y2,y3,...,yN]Setting a codeword bit flipping weight factor U ═ U1,u2,u3,...,uN],ui＝α|yiL, |; the second step is to calculate the codeword bit reliability factor Ei(ii) a And thirdly, carrying out overturn decoding and updating the code word bit overturn weight factor according to the overturn rule.
Fig. 2 shows an explanation of the WMBF decoding process.
Suppose (N, K) (d)v,dc) Is an LDPC codeword C with a code length of N, an information bit sequence length of K, and a variable node degree of dvCheck node degree of dc. Checking LDPC check matrix as H ═ (H)m,n) M is more than or equal to 1and less than or equal to M, and N is more than or equal to 1and less than or equal to N. The transmission sequence is X after modulation, Y (Soft-Information) is actually read out from the NAND Flash memory after noise (Gaussian noise) simulation, and the initial hard decision sequence is Z. Adjoint matrix S ═ Z × HT(mod 2); assume that the set of bit nodes associated with check nodes in the check matrix is n (m) ═ n: h m,n1, the check node set related to the same bit node is m (n) { m: h }m,n1 }. Bit discrimination inversion weight sequence U ═ U1,u2,u3,...,uN]Wherein u isi＝α|yiL (wherein alpha is a non-negative parameter factor which is related to the check matrix column and can obtain the optimal value through a large number of simulation experiments), and the maximum iteration number of the decoding is set to be Kmax。
The preparation method comprises the following steps: and (3) passing k bits of the original information through a generating matrix G to generate n-bit code words containing m bits of redundant information, and storing the n-bit code words in the flash memory, wherein n is m + k.
Initializing relevant parameters, such as alpha parameter, and codeword bit flipping weight sequence U ═ U1,u2,u3,...,un]Wherein u isi＝α|yiL, setting the maximum number of iterations KmaxThe initial iteration number k is 1;
the method comprises the following steps: obtaining a syndrome S by calculation according to the initial decision sequence ZmIf S ismWhen the decoding is stopped, 0 or k is reached; calculating a reliability intermediate parameter factor if none of the above conditions are met:
step two: calculating a codeword bit confidence factor En：
Step three: obtaining a code word bit credibility factor E according to calculationnAnd according to a set turning rule, turning the bit which is determined as the error bit to obtain a turned sequence Zk. The updating strategy of the flipping rule and the error bit discrimination standard is as follows:
step four: according to S ═ ZHTCalculating the syndrome Sm(ii) a If the current calculation S m0; or the iteration number K reaches K +1 > Kmax(ii) a Stopping iterative decoding and outputting a current decoding result; otherwise, returning to the step two. And k is k + 1;
the roll-over function in the WMBF method consists of two parts,
can be regarded as a codeword bit reliability factor, u, from the check equationi＝α|yiAnd l is regarded as a code word bit flipping weight factor. During each iteration, the roll-over function will be Ei＞uiThe syndrome corresponding to the bit is updated at the next iteration, so that the reliability information from the check equation is updated
However, the flipping weights in the conventional weight bit flipping method are not changed, and the flipping weights are updated iteratively in the WMBF method. When the bits with low reliability are turned over and then become the bits with higher reliability, the invention updates the bit reliability weight value of each iterative turning in order to reflect the increase of the reliability, thus effectively reducing the probability that the same bit is repeatedly turned over in the decoding process. Simultaneously with the existing BF&The maximum difference of WBF is on the standard of how to judge error bit, the WMBF of the invention realizes the possibility of parallel multi-bit parallel inversion, and can meet the condition Ei≥uiImplements one iteration to flip simultaneously even when all bits are at Ei＜uiUnder the condition, the decoding method can search the maximum globally
(or several of
) And the inversion is carried out, so that at least one bit of inversion is kept in the iterative computation decoding process each time, and the problems that the whole code word cannot be updated once iteration occurs in the conventional multi-bit inversion method, the iterative decoding enters a dead loop, and the decoding cannot be effectively converged until the decoding reaches the maximum iteration number are avoided. The mechanism effectively overcomes the defect that the prior improved weighted bit flipping method only needs to complete the search firstly in each iteration process and has the maximum value
Corresponding bits are then inverted, and decoding cannot realize the parallel defect.
The present invention will be described in detail in the WMBF method. In order to improve the parallelism of decoding, in each iteration decoding process, the WMBF method presets the self-overturning weight of each bit and sets the self-overturning weight as Ui. When calculating the confidence factor E of each bit from the check equationiBy comparison of EiAnd Ui：
●If Ei＝UiFlipping the bit;
●If Ei＞Uiupdate Ui＝EiWhile flipping the bit.
When All is present in each iteration decoding processi＜Ui. A serial decoding scheme for performing a global search operation is activated in the iterative decoding process. Due to the high code rate (at least 90%) adopted in the storage systemAnd the overall error rate of the data is low, more use rule codes of the LDPC code check matrix are adopted in the storage system, and the selection of the column weight is 3-5. So that the bits come from the reliability E of the check equationiWithin a very limited range, the confidence weight (flip weight) of each bit can be set to be Ui＝α|yiAnd l, wherein alpha is related to the column weight of the check matrix and can be obtained through simulation.
Conventional BF&WBF decoder Flip Logic needs to complete global search maximum Emax(or a maximum of q Emax) The comparison judgment and turning operation can be carried out later, namely the decoding adopts a serial design, and the design seriously influences the throughput rate of the decoder; simultaneous preferential global search maximum Ei(or a maximum of q Ei) It takes a large number of comparator arrays to perform, and the power consumption is large while a large amount of intermediate data needs to be saved, so that the space overhead is increased. In order to improve the parallel execution capacity of the decoder, the design of the invention adopts a parallel decoding strategy, and E is obtained through calculationiThe information is directly associated with uiComparing and judging whether the bit needs to be turned or not, and for Ei＞uiWill be given by EiUpdating the bit correspondence ui(solid line portion); meanwhile, when the iteration does not have the updating of the turnover weight, the global search module is executed to obtain the maximum EmaxThe flip has a maximum EmaxCorresponding bits.
The invention adopts simulation in Matlab environment, uses QC-PEG-LDPC regular code, selects code length N2 KB, and code rate 90% for convenient experiment and fully explaining the superiority of WMBF decoding method in decoding performance. Check matrix selects column weight dcThe initial bit error rate RBER ranges from 0.01 to 0.002.
To fully illustrate the superiority of the WMBF decoding method provided by the present invention. The invention adopts verification from two angles: firstly, comparing the error correction performance of the WMBF decoding method with that of the WBF and MWBF decoding method, and secondly, comparing the decoding speed, wherein the decoding speed is expressed by the average iteration number of decoding.
First, as shown in fig. 4 and 5, it can be seen that the two methods using DERM (DERM/NBF, DERM/GDBF) have a lower uncorrectable error rate than the original two methods (NBF, GDBF). In particular, when the column weight is 3, the effect of using DERM is more remarkable. This is because the DERM can effectively overcome the error syndrome information propagation introduced by even number bit inversion, reduce the search interval, improve the error correction capability, and have a strong error correction capability even when the column weight is small.
In order to fully test the effectiveness of the WMBF method, the MWBF is used, and the standard WBF decoding method is compared with the WMBF method. In the experiment, 2KB is used, the code rate is 90% of the regular QC-PEG-LDPC code, and the column weight is 3 and 5. The parameter α of the WMBF decoding method is set to 0.82,0.90 according to the column weight. Maximum number of iterations K max100. The initial bit error rate RBER ranges from 0.01 to 0.002. The error correction capability and the decoding average number of iterations are illustrated for example in fig. 6 and 7.
Experimental simulation shows that the error correction performance of the WMBF decoding method is not much different from that of the MWBF decoding method, and a small amount of improvement is provided, but it can be known from fig. 6 and 7 that the WMBF decoding method has a very large improvement in the average iteration number of decoding, and the decoding convergence speed is significantly accelerated. Particularly, the reduction of the decoding iteration number in the interval of 0.005 to 0.007 of RBER is peaked. The average decoding iteration number is reduced by 30-45%.
As the storage system adopts high code rate (at least 90 percent) and the overall data error rate is low, more regular codes are used in the LDPC code check matrix adopted in the storage system, and the column selection is 3-5. So that the bits come from the reliability E of the check equationiWithin a very limited range, so that the confidence weights u of the code word bitsi＝α|yiThe | factor α is also within a narrow range because of the bit confidence E from the check nodesiThe method adopts a large amount of experimental simulation to simulate the method, adopts QC-PEG-LDPC construction regular codes and uses the length of which the code rate is about 90 percentExperiment is carried out on code words with the length of N being 2KB, the initial error rate RBER of the code words is 0.01and RBER is 0.007, (which is already at the end of flash memory), and the check matrix column weights are respectively dv＝3、d v4 and d v5, the maximum iteration number upper limit K max100 as shown in fig. 8 and 9.
As can be seen from fig. 8 and 9, when RBER is 0.01 or 0.007, when the check matrix column weight d is usedvAt 3, the decoding success rate (note: decoding can converge successfully, i.e., S is 0) occurs at the highest when α is equal to [0.825,0.85]Nearby; when check matrix column weight dvWhen the decoding success rate is 4, the highest decoding success rate occurs when the alpha is equal to [0.85,0.875 [ ]]Nearby; when check matrix column weight dvWhen the value is 5, the decoding success rate is the highest when the values of alpha are equal to 0.9,0.95]Nearby.
Claims (2)
1. A weight multi-bit flipping LDPC decoding method suitable for SSD is characterized in that,
the method comprises the following steps:
1) initializing a non-negative parameter factor alpha and a codeword bit flipping weight sequence U ═ U1,u2,u3,...,un]，ui＝α|yiIn which the maximum number of iterations K is setmaxThe initial iteration number k is 1; 1,2, … n;
2) obtaining a syndrome S according to the initial decision sequence Z by calculation, wherein S is ZHTIf S is 0 or K reaches the maximum number of iterations KmaxIf yes, stopping decoding and outputting a decoding result; if none of the above conditions is met, calculating a reliability intermediate parameter factor wm：
Wherein N (m) ═ n: hm,n＝1}；hm,nIs an element in the check matrix H, H ═ Hm,n) M is more than or equal to 1and less than or equal to M, N is more than or equal to 1and less than or equal to N, M is a row of the check matrix, and N is a code length; y isnSoft information for the nth channel;
3) calculating codeword bit confidence factorSeed En：
Wherein M (n) ═ m: hm,n＝1}；smRepresents an element in syndrome S;
4) according to the code word bit credibility factor EnAnd according to a set turning rule, turning the bit which is determined as the error bit to obtain a turned sequence Zk(ii) a The turning rule is as follows: if E isi＝uiFlipping the bit; if E isi＞uiUpdate ui＝EiWhile flipping the bit; the updating method of the flipping rule and the error bit discrimination standard is as follows:
Eithe bit credibility factor is the ith code word;
5) according to S ═ ZkHTCalculating a syndrome S; if S obtained by current calculation is 0, or the iteration number K reaches K +1 > KmaxStopping iterative decoding, and outputting a current decoding result; otherwise, returning to the step 3), and adding 1 to the k value.
2. The method for decoding LDPC code with multi-bit flipping weights applicable to SSD according to claim 1, wherein the obtaining process of the non-negative parameter factor α is as follows: the experiment is carried out by using code words with the length of N being 2KB and the code rate of R being 90 percent, the initial error rate of the code words RBER being 0.01and RBER being 0.007, and d is respectively taken by the weight of the check matrixv＝3、dv4 and dv5, the maximum iteration number upper limit KmaxWhen check matrix column number d is 100vWhen the value is 3, the value of alpha is [0.825,0.85 ]](ii) a When check matrix column weight dvWhen the alpha value is 4, the alpha value is [0.85,0.875 ]](ii) a When check matrix column weight dvWhen the value is 5, the value of alpha is [0.9,0.95 ]]。
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