CN106160753B - Weight multi-bit flipping LDPC decoding method suitable for SSD - Google Patents

Abstract

The invention discloses a weight multi-bit flipping LDPC decoding method suitable for SSDThe first step is based on the read channel soft information Y ═ Y₁,y₂,y₃,...,y_N]Setting a codeword bit flipping weight factor U ═ U₁,u₂,u₃,...,u_N],u_i＝α|y_iL, |; the second step is to calculate the codeword bit reliability factor E_i(ii) a And thirdly, carrying out overturn decoding and updating the code word bit overturn weight factor according to the overturn rule. The invention effectively improves the throughput in the high-speed storage system; the global search operation with the maximum reliability factor of the prior bit flip search in the decoding process is overcome, and the error correction capability is improved; meanwhile, the restriction between the error correction capability and the operation speed is optimized, and the parallel decoding is effectively realized.

Description

A weighted multi-bit flip LDPC decoding method suitable for SSD

technical field

The present invention relates to a weight multi-bit inversion LDPC decoding method suitable for SSD.

Background technique

With the rapid development of the Internet and information systems in various fields of society, data is growing explosively, making large-capacity storage systems face huge challenges in terms of reliability and read/write performance. Solid-State Drive (SSD), which uses a new type of NAND Flash as a storage medium, has been gradually applied to data storage in many fields such as the Internet, military, vehicle, and aviation because of its excellent features such as high performance and low power consumption. It also provides more development opportunities for building large-capacity storage systems. It is one of the main development trends of storage systems to use Flash media to build high-capacity solid-state storage systems with high fault tolerance and high performance. Although researchers have carried out various researches on solid-state drives and have achieved a series of related results, the error correction coding technology of solid-state storage systems still follows the traditional error correction code (ECC, Error Correction Code) of traditional magnetic storage systems. Code) technology, the research on the error characteristics of Flash media and solid-state drives is not extensive and in-depth.

At the same time, with the continuous expansion of cloud computing applications, more IT manufacturers have established their own data centers, not only Internet companies, but also some traditional IT manufacturers have begun to focus on the development of data centers. Due to the large scale of the data center, tens of thousands of traditional magnetic media storage devices bring huge energy costs, and the problem of I/O performance bottlenecks is prominent, which gives solid-state drives a broad market space, and the low power consumption of solid-state storage systems. Features such as high power consumption, high performance, and low noise provide more space for the development of large-scale data centers and become the preferred configuration for future data centers or cloud computing. Therefore, the use of high-performance solid-state storage systems to build large-scale data centers is one of the main development trends of storage systems in the future. IDC's research report predicts that the sales of solid-state storage systems will grow at an annual rate of 105% from 2010 (2.4 billion US dollars), and will reach 10 billion US dollars per year, and is rated as one of the top ten new technologies in the storage field by IDC. . At the same time, IDC research data shows that in 2014, the total amount of global data storage will increase to 2.16ZB.

At present, NAND Flash is widely used in various fields related to storage. As a storage medium with excellent performance, it plays a key role in the application of solid-state drives in particular. However, limited by the internal structural characteristics of NAND Flash, how to improve and ensure The reliability of NAND Flash is one of the major topics in flash memory research. NAND Flash solves the error problem through error correction code ECC. In the process of development, RS code (Reed-Solomn) and BCH code (Bose-Chauhuri-Hocquenghem) are used as error correction codes [2][3]. With the advancement of Flash technology, the number of bits stored in a single Flash memory cell has increased. From the original SLC (Single-Level-Cell) to MLC (Multi-Level-Cell) and TLC, the storage density has increased significantly, and the storage space has been shrinking. In particular, when the process of Flash is below 25nm, the error rate of NAND Flash has risen sharply. The traditional error correction code mechanism has been unable to meet the growing demand for flash memory. As a kind of error correction with excellent error correction performance and parallel fast decoding Low-Density-Parity-Check-Code (LDPC) has been widely used in the field of channel coding, and LDPC codes have also been used in the field of flash memory error correction in recent years. The characteristics of high storage density and low cost of NAND Flash flash memory require high code rate, long code, high performance and low complexity for LDPC codes. Therefore, it is of great significance to study a new efficient decoding technology suitable for NAND Flash.

In a word, as the Flash technology goes deep into 25nm or below, and the structure changes from SLC to MLC to TLC, the storage capacity is getting larger and larger, and the data error rate is getting higher and higher. At present, the data error tolerance of solid-state storage systems still relies on traditional Some error correction technologies of magnetic storage systems are no longer fully in line with the technical characteristics of solid-state storage media, and it is difficult to give full play to their performance advantages. Therefore, it is of great significance to study the error correction coding technology that conforms to the random error characteristics of solid-state storage systems, and to develop error-correction coding chips with high error tolerance to ensure the reliability of large-capacity solid-state storage systems.

LDPC code, namely Low Density Parity Check Code, is a class of linear block codes defined by a parity check matrix proposed by Gallager in the 1960s. Because the check matrix contains a small number of non-zero elements, it gets its name. LDPC codes have become a research hotspot in recent years due to their high coding rate, fast decoding speed, few undetectable errors, simple hardware implementation, and relatively low error-generating platforms.

Bit-Flipping is a representative hard decoding method of LDPC. There are many versions. The basic idea is mainly based on the hard decoding proposed by Gallager. According to the comparison of the number of unsatisfied equations and the number of satisfied equations, the flipping decision is made. Since the Bit-Flipping decoding process has only simple operations, it is characterized by low hardware overhead, low computational complexity, and fast operation speed, but the error correction performance is relatively poor, and the decoding convergence speed is slow.

Zhao has improved the traditional Bit-Flipping method, which is called NBF (Novel Bit-Flipping) method. NBF solves the global search in the decoding process of the traditional method. The method used is to dynamically change the flip threshold. Experiments show that This method can effectively improve the decoding speed and save the hardware design overhead, but the disadvantage is that the error correction performance is further lost.

Yu PengHu et al. proposed a decoding strategy based on the main error interval of flash memory based on the study of the error characteristics of NAND Flash. Through the error interval strategy, the error bits and the correct bits can be effectively distinguished. This scheme can effectively improve the decoding efficiency and decoding error correction. ability.

Zhang T et al. proposed Hybrid Hard/Soft soft-hard decision mixed decoding strategy method according to the error characteristics of different stages of flash memory life cycle. In the early stage of the cycle, the hard-decision Bit-Flipping or Min-Sum decoding method is used. When the decoding is unsuccessful, the high-precision judgment Min-Sum decoding method is called, which improves the overall decoding error correction ability and decoding speed to a certain extent. The obvious defect is that the hardware overhead is large and the decoding performance improvement is limited.

According to whether the check equation is satisfied or not, Wu et al. modified the min-sum method with different correction factors. Under the condition of low signal-to-noise ratio, better decoding performance was obtained than using a single correction factor. LDPC codes with smaller code lengths have a relatively high floor effect, that is, under the condition of higher signal-to-noise ratio, there is still a bit error rate of the order of magnitude greater than 10-6.

As mentioned above, these researchers have studied the decoding methods of LDPC codes from different aspects, and they have obtained relatively good decoding performance under certain conditions.

At present, the decoding technologies existing in LDPC error correction codes mainly include soft decoding Soft-decision, hard decoding hard-decision and hybrid decoding. Soft-decision takes soft information as input, and decodes through sum, multiplication and even logarithmic operations. It is characterized by strong error correction ability, high decoding parallelism, fast convergence speed, close to the Shannon limit, but large computational complexity and hardware It is difficult to achieve. In a high-speed storage system, because of the need for high-precision soft information, the delay caused by accurately reading the voltage value of the memory cell occupies most of the time spent in the entire decoding process, which restricts the improvement of the decoding speed and improves the throughput. difficulty.

Hard-decision decoding takes simple 0 and 1 as input, and the decoding process only has simple integer operations, so it is characterized by low hardware overhead, low computational complexity, and fast operation speed. However, it has a fatal deficiency, poor error correction ability, and slow decoding convergence speed. The reasons are as follows: First, based on the XOR operation check matrix, in the decoding process, even-number bit flips will introduce wrong syndromes information, and the wrong syndrome information will be propagated in the subsequent decoding process, making it difficult to accurately decode and converge only by relying solely on syndrome information; second, the bit flip search has the greatest reliability in hard-decision decoding. The factor process is global, and the global search process makes the decoding appear pseudo-parallel decoding; third, the hard decision operation will lose most of the channel information, resulting in low utilization of channel information.

Hybrid decoding is an ideal decoding method, because this method combines the soft information of soft-decision and the decoding speed of hard-decision. This kind of method effectively improves the decoding error correction ability due to the introduction of channel soft information, and the computational complexity of decoding is not much different from that of the BF method. The decoding method of the present invention is improved and proposed on the basis of such methods.

Recently, a series of research results on improving the error correction performance of BF hybrid decoding methods and improving the convergence speed have been proposed, such as Weighted BF (WBF), Modified WBF (MWBF), Combined Modified WBF (CMWBF), Parallel WBF (PWBF) , Candidate bit BF (CBBF) and other decoding methods, this type of decoding method is also called a weighted bit flip method based on soft information. Since improving the convergence speed of the decoding method and reducing the average number of decoding iterations are effective ways to improve the throughput of the decoder, the parallelism of the decoding is improved, the hardware overhead of the decoder design is reduced, and the decoder can be effectively guaranteed at the same time. Having a higher error correction capability is the key to the research of the decoder.

The basic decoding process of various traditional BF and WBF decoding methods is shown in Figure 1. It can be seen that there are three main steps in each iterative decoding process: Step 1 For each given hard-decision codeword All bits, calculate the credibility information of each bit from the check equation, set as E _i ; Step 2 global search has the largest E _i (or the largest q E _i ); Step 3 flips all the E _i (or A maximum of q E _i ) corresponding bits. Among them, Step 3 can be executed after the global search is completed in Step 2. The decoder needs to store all E _i in this process, and the serial design of asynchronous execution limits the decoding speed.

Analysis of Fig. 1 shows that the existing improved BF or WBF methods involve a global search operation (searching for the bits with the largest E _i ) in each iterative decoding process, and then the weights flip specific bits. Such a serial design will lead to several disadvantages in the decoder design process: (i) the decoder needs to store a large amount of intermediate data, resulting in a large amount of silicon buffer space overhead; (ii) more attention should be paid to the decoding In the decoding process of the decoder, the global search operation must be completed first, and then the flip operation can be performed, so that parallel decoding is blocked, resulting in limited decoding throughput. In order to solve the above two defects, in particular, the decoding cannot be parallelized, and the weights of the existing WBF decoding method cannot be updated, so that the decoding is easy to enter the trap of the same bit cyclic flip, which seriously affects the decoding convergence speed.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a weight multi-bit inversion LDPC decoding method suitable for SSD in view of the deficiencies of the prior art.

In order to solve the above-mentioned technical problems, the technical solution adopted in the present invention is: a weight multi-bit flip LDPC decoding method suitable for SSD, comprising the following steps:

1) Initialize the non-negative parameter factor α, and the codeword bit flip weight sequence U=[u ₁ , u ₂ , u ₃ ,..., u _n ],

u _i =α|y _i |, where the maximum number of iterations K _max is set, and the initial number of iterations k=1;

i=1,2,...n;

2) Calculate the syndrome S according to the initial decision sequence Z, S=ZH ^T , if S=0 or k reaches the maximum number of iterations K _max , stop decoding and output the decoding result; if none of the above conditions are satisfied, the calculation is reliable Sexual intermediate parameter factor w _m :

Among them, N(m)={n:h _m , _n =1}; h _m,n are elements in the check matrix H, H=(h _m,n ), 1≤m≤M, 1≤n≤ N, M is the row of the check matrix, N is the code length, y _n is the soft information of the nth channel;

3) Calculate the bit reliability factor _En of the codeword:

Wherein, M(n)={ _m : _hm,n =1}; sm represents the element in syndrome S;

4) according to the codeword bit reliability factor E _n and according to the set inversion rule, flip the bit that is judged to be an error bit to obtain the flipped sequence Z ^k ;

5) Calculate the syndrome S again according to S=Z ^k H ^T ; if the current calculated S=0, or the iteration number k reaches k+1>K _max , stop iterative decoding, and output the current decoding result; otherwise, return to the step 3), and add 1 to the k value.

The acquisition process of the non-negative parameter factor α is as follows: use codewords with a code rate of R=90% and a length of N=2KB to conduct experiments. The initial error rates of the codewords are RBER=0.01 and RBER=0.007, and the column weight of the check matrix is d _v respectively. =3, d _v =4 and d _v =5, the upper limit of the maximum number of iterations K _max =100, when the check matrix column weight d _v =3, the value of α is [0.825, 0.85]; when the check matrix column weight is When d _v =4, the value of α is [0.85, 0.875]; when the column weight of the check matrix is d _v =5, the value of α is [0.9, 0.95]. Compared with the prior art, the present invention has the following beneficial effects: the present invention effectively improves the throughput in the high-speed storage system; overcomes the global search operation with the maximum reliability factor in the priority bit inversion search in the decoding process, and improves the Error correction ability; at the same time, the constraints between error correction ability and operation speed are optimized, and parallel decoding is effectively realized.

Description of drawings

Fig. 1 is the basic decoding flow chart of existing various traditional BF and WBF decoding methods;

Fig. 2 is the WMBF decoding flow chart of the present invention;

Fig. 3 is the Flip Logic module design diagram of the WMBF decoder of the present invention;

4 is a comparison diagram of the error correction capability of the standard WBF decoding method and the method of the present invention when the column weight of the present invention is 5;

5 is a comparison diagram of the error correction capability of the standard WBF decoding method and the method of the present invention when the column weight of the present invention is 3;

6 is a comparison diagram of the average number of iterations of decoding between the standard WBF decoding method and the method of the present invention when the column weight of the present invention is 5;

7 is a comparison diagram of the average number of iterations of decoding between the standard WBF decoding method and the method of the present invention when the column weight of the present invention is 3;

FIG. 8 is a curve diagram of the value of α corresponding to RBER=0.01 and the decoding success rate;

FIG. 9 is a curve diagram of the value of α corresponding to RBER=0.007 and the decoding success rate.

Detailed ways

The whole decoding process of the WMBF method of the present invention is roughly divided into three steps. The first step is to set the codeword bit flip according to the read channel soft information Y=[y ₁ , y ₂ , y ₃ ,...,y _N ] Weight factor U=[u ₁ , u ₂ , u ₃ ,...,u _N ], u _i =α|y _i |; the second step is to calculate the codeword bit reliability factor E _i ; the third step is Perform flip decoding and update codeword bit flip weight factor according to flip rule.

Figure 2 shows a description of the WMBF decoding process.

Suppose (N,K)(d _v ,d _c ) is an LDPC codeword C, where the code length is N, the information bit sequence length is K, the variable node degree is d _v , and the check node degree is d _c . The check matrix of the check LDPC is H=(h _m,n ), 1≤m≤M, 1≤n≤N. After modulation, the transmission sequence is X, and after simulation with noise (Gaussian noise), the channel soft information sequence actually read from the NAND Flash flash memory is Y (Soft-Information), and the initial hard decision sequence is Z. Syndrome matrix S=Z*H ^T (mod2); Assuming that the set of bit nodes related to the check node in the check matrix is N(m)={n:h _m,n =1}, the checksum related to the bit node is The set of test nodes is M(n)={m:h _m,n =1}. Bit discriminant flip weight sequence U=[u ₁ , u ₂ , u ₃ ,...,u _N ], where u _i =α|y _i | (where α is a non-negative parameter factor, which is the same as the test matrix column The optimal value can be obtained through a large number of simulation experiments), and the maximum number of iterations of decoding is set as K _max .

Preparation steps: pass the original information k bits through the generator matrix G to generate an n-bit codeword containing m-bit redundant information, and store it in the flash memory, where n=m+k.

Initialize and set relevant parameters, such as the α parameter, and the codeword bit flip weight sequence U=[u ₁ , u ₂ , u ₃ , . . . , u _n ], where u _i =α|y _i |, set The maximum number of iterations K _max , the initial number of iterations k=1;

Step 1: Calculate and obtain the syndrome S _m according to the initial decision sequence Z. If S _m = 0 or k reaches the stop decoding output result; if the above conditions are not satisfied, calculate the reliability intermediate parameter factor:

Step 2: Calculate the bit reliability factor _En of the codeword:

Step 3: Obtain the codeword bit reliability factor _En according to the calculation, and according to the set inversion rule, invert the bit determined as the wrong bit to obtain the inverted sequence Z ^k . The update strategy of the inversion rule and the error bit judgment criterion is as follows:

Step 4: recalculate the syndrome S _m according to S=ZH ^T ; if the current calculation S _m =0; or the iteration number k reaches k+1>K _max ; stop iterative decoding and output the current decoding result; otherwise, return to step 2. and k=k+1;

可以视为来自校验方程的码字比特可靠性因子，u_i＝α|y_i|视为码字比特翻转权值因子。在每一次迭代过程中，翻转函数会将E_i＞u_i的比特进行翻转，此比特对应的伴随式在下一次迭代时得到更新，因此来自校验方程的可靠度信息得到了更新

然而，现有权值比特翻转方法中翻转权值并未改变，在WMBF方法中翻转权值会迭代更新。当可信度低的比特被翻转后应变为具有较高可信度的比特，本发明为了体现出这种可信度的增加，将每次迭代翻转的比特可信度权值更新，这样能够有效降低译码过程中相同比特被反复翻转的概率，由于两种可信度译码过程中都迭代更新，译码精度得到提升。同时同现有BF&WBF最大的差别在于在如何判定错误比特的标准上，在本发明的WMBF，实现了并行多比特并行翻转的可能，能够满足条件E_i≥u_i的多个比特实现一次迭代同时翻转，即使在所有比特处于E_i＜u_i情况下，译码方法会全局搜索最大

(或者几个

)进行翻转，因此在每次迭代计算译码过程中至少保持一个比特的翻转，避免了现有多比特翻转方法出现一次迭代整个码字无法更新，迭代译码进入死循环，译码无法有效收敛，直到译码达到最大迭代次数。这种机制有效克服了现有改进加权比特翻转方法每次迭代过程中必须先完成只搜索具有最大

对应的比特，然后执行翻转操作，译码无法实现并行的缺点。The flip function in the WMBF method consists of two parts,

It can be regarded as the codeword bit reliability factor from the check equation, and u _i =α|y _i | is regarded as the codeword bit flip weight factor. In each iteration process, the flip function will flip the bit of E _i > _ui , the syndrome corresponding to this bit is updated in the next iteration, so the reliability information from the check equation is updated

However, in the existing weight bit flipping method, the flipping weight does not change, and in the WMBF method, the flipping weight is updated iteratively. When a bit with low reliability is flipped, it should be turned into a bit with higher reliability. In order to reflect this increase in reliability, the present invention updates the bit reliability weight of each iteration flipped, so that it can It effectively reduces the probability that the same bit is repeatedly flipped in the decoding process, and the decoding accuracy is improved due to iterative updating in the two reliability decoding processes. At the same time, the biggest difference from the existing BF&WBF lies in the standard of how to determine the error bit. In the WMBF of the present invention, the possibility of parallel multi-bit parallel flip is realized, and the multiple bits that can satisfy the condition E _i ≥ u _i can realize one iteration simultaneously. Flip, even if all bits are in the case of E _i < _ui , the decoding method will globally search for the maximum

(or a few

) to flip, so at least one bit flip is maintained in each iterative calculation and decoding process, avoiding the existing multi-bit flip method that the entire codeword cannot be updated in one iteration, the iterative decoding enters an infinite loop, and the decoding cannot effectively converge. , until the decoding reaches the maximum number of iterations. This mechanism effectively overcomes the fact that the existing improved weighted bit-flipping method must complete the search first in each iteration process.

The corresponding bits are then flipped, and the decoding cannot achieve the disadvantage of parallelism.

The present invention will be described in detail with the WMBF method. In order to improve the parallelism of decoding, in each iterative decoding process, the WMBF method presets the flip weight of each bit itself, which is set as U _i . When calculating the confidence factor E _i for each bit from the check equation, by comparing E _i with U _i :

If E _i =U _i , flip the bit;

• If E _i >U _i , update U _i =E _i while flipping the bit.

When there is All:E _i <U _i in each iterative decoding process. Then in the iterative decoding process, the serial decoding scheme that performs the global search operation is activated by activation. Since the storage system adopts a high code rate (at least 90%) and the overall data error rate is low, the LDPC code check matrix used in the storage system uses more regular codes, and the column re-selection selection is 3-5. Therefore, the credibility E _i of the bit from the check equation is in a very limited range, and the credibility weight (flip weight) corresponding to each bit itself can be set as U _i =α|y _i |, where α is related to the column weight of the check matrix and can be obtained by simulation.

The traditional BF&WBF decoder Flip Logic needs to complete the global search for the maximum E _max (or the maximum q E _max ) before performing the comparison decision flip operation, that is, the decoding adopts a serial design, which will seriously affect the decoder throughput. At the same time, the global search for the largest E _i (or the largest q E _i ) requires a large number of comparator arrays to execute, and the power consumption is relatively large, and a large amount of intermediate data needs to be saved, which increases the space overhead. In order to improve the parallel execution capability of the decoder, the design of the present invention adopts a parallel decoding strategy. When E _i is calculated, the information is directly compared with _{u i} to determine whether the bits need to be flipped _. The bit corresponding to _ui (solid line part) is updated with E _i ; at the same time, when there is no flip weight update in this iteration, the global search module is performed to obtain the maximum E _max , and the flip has the corresponding bit with the largest E _max .

The invention adopts the simulation under the Matlab environment and uses the QC-PEG-LDPC regular code. For the convenience of the experiment and fully explaining the superiority of the decoding performance of the WMBF decoding method, the selected code length is N=2KB, and the code rate is used as 90%. . The check matrix is selected with column weights d _c of 3 and 5 respectively, and the initial bit error rate RBER is in the range of 0.01 to 0.002.

In order to fully illustrate the superiority of the WMBF decoding method proposed by the present invention. The present invention is verified from two perspectives: firstly, the WMBF decoding method is compared with the WBF and MWBF decoding methods in terms of error correction performance, and secondly, the decoding speed is compared, wherein the decoding speed is based on the decoding average iteration number of times.

First, as shown in Figures 4 and 5, it can be seen that both methods using DERM (DERM/NBF, DERM/GDBF) have lower uncorrectable error rates than the original two methods (NBF, GDBF). Especially when the column weight is 3, the effect of using DERM is more obvious. This is because DERM can effectively overcome the error concomitant information propagation introduced by the even-numbered bit flip, narrow the search range, and improve the error correction ability. Even if the column weight is very small, it can still have a strong error correction ability.

In order to fully test the validity of the WMBF method of the present invention, the present invention uses MWBF, and the standard WBF decoding method is compared with the method of the present invention. In the experiment, 2KB is used, the code rate is 90% regular QC-PEG-LDPC code, the column weight is 3,5. The WMBF decoding method parameter α is set to 0.82, 0.90 according to the column reset. Maximum number of iterations K _max =100. The range of initial bit error rate RBER is 0.01 to 0.002. The comparison between the error correction capability and the average number of decoding iterations is illustrated in Figures 6 and 7 .

The experimental simulation shows that the error correction performance of the WMBF decoding method is not much different from that of the MWBF decoding method, and there is a small improvement, but it can be seen from Figure 6 and Figure 7 that the WMBF decoding method has a very large average number of decoding iterations. The improvement of the decoding convergence speed is significantly accelerated. Especially when the RBER is in the range of 0.005 to 0.007, the reduction in the number of decoding iterations reaches a peak. The average number of decoding iterations is reduced by 30%-45%.

Since the storage system adopts a high code rate (at least 90%) and the overall data error rate is low, the LDPC code check matrix used in the storage system uses more regular codes, and the column re-selection selection is 3-5. Therefore, the reliability E _i of the bit from the check equation is in a very limited range, so the reliability weight u _i = α|y _i | of the codeword bits is also in a narrow range, because from The bit reliability E _i of the check node is directly related to the column weight of the check matrix, so when the parameter factor α is set, it must also be related to the column weight of the check matrix. In order to obtain the optimal α value, the present invention adopts A large number of experimental simulations are used for simulation. The present invention uses QC-PEG-LDPC to construct regular codes, and uses codewords with a code rate of about R=90% and a length of N=2KB to conduct experiments. The initial error rate of the codeword is RBER=0.01 and RBER=0.007, (Already at the end of the flash memory), the column weights of the parity check matrix are d _v =3, d _v =4 and d _v =5 respectively, and the upper limit of the maximum number of iterations is K _max =100, as shown in FIG. 8 and FIG. 9 .

It can be seen from Figure 8 and Figure 9 that when RBER=0.01 or RBER=0.007, when the check matrix column weight is d _v =3, the decoding success rate (Note: The decoding can successfully converge, that is, S=0) appears at the highest at α The average value is equal to the vicinity of [0.825, 0.85]; when the check matrix column weight d _v = 4, the highest decoding success rate occurs when the α average value is equal to [0.85, 0.875]; when the check matrix column weight d _v = 5, the highest decoding success rate occurs when the value of α is equal to [0.9, 0.95].

Claims (2)

1. A weight multi-bit flipping LDPC decoding method suitable for SSD is characterized in that,

the method comprises the following steps:

1) initializing a non-negative parameter factor alpha and a codeword bit flipping weight sequence U ═ U₁,u₂,u₃,...,u_n]，u_i＝α|y_iIn which the maximum number of iterations K is set_maxThe initial iteration number k is 1; 1,2, … n;

2) obtaining a syndrome S according to the initial decision sequence Z by calculation, wherein S is ZH^TIf S is 0 or K reaches the maximum number of iterations K_maxIf yes, stopping decoding and outputting a decoding result; if none of the above conditions is met, calculating a reliability intermediate parameter factor w_m：

Wherein N (m) ═ n: h_m,n＝1}；h_m,nIs an element in the check matrix H, H ═ H_m,n) M is more than or equal to 1and less than or equal to M, N is more than or equal to 1and less than or equal to N, M is a row of the check matrix, and N is a code length; y is_nSoft information for the nth channel;

3) calculating codeword bit confidence factorSeed E_n：

Wherein M (n) ═ m: h_m,n＝1}；s_mRepresents an element in syndrome S;

4) according to the code word bit credibility factor E_nAnd according to a set turning rule, turning the bit which is determined as the error bit to obtain a turned sequence Z^k(ii) a The turning rule is as follows: if E is_i＝u_iFlipping the bit; if E is_i＞u_iUpdate u_i＝E_iWhile flipping the bit; the updating method of the flipping rule and the error bit discrimination standard is as follows:

E_ithe bit credibility factor is the ith code word;

5) according to S ═ Z^kH^TCalculating a syndrome S; if S obtained by current calculation is 0, or the iteration number K reaches K +1 > K_maxStopping iterative decoding, and outputting a current decoding result; otherwise, returning to the step 3), and adding 1 to the k value.

2. The method for decoding LDPC code with multi-bit flipping weights applicable to SSD according to claim 1, wherein the obtaining process of the non-negative parameter factor α is as follows: the experiment is carried out by using code words with the length of N being 2KB and the code rate of R being 90 percent, the initial error rate of the code words RBER being 0.01and RBER being 0.007, and d is respectively taken by the weight of the check matrix_v＝3、d_v4 and d_v5, the maximum iteration number upper limit K_maxWhen check matrix column number d is 100_vWhen the value is 3, the value of alpha is [0.825,0.85 ]](ii) a When check matrix column weight d_vWhen the alpha value is 4, the alpha value is [0.85,0.875 ]](ii) a When check matrix column weight d_vWhen the value is 5, the value of alpha is [0.9,0.95 ]]。

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