CN111224675A

CN111224675A - Efficient bit flipping decoder based on adaptive threshold

Info

Publication number: CN111224675A
Application number: CN201911161916.4A
Authority: CN
Inventors: 王中风; 崔航轩; 林军
Original assignee: Nanjing University
Current assignee: Nanjing University
Priority date: 2019-11-22
Filing date: 2019-11-22
Publication date: 2020-06-02

Abstract

The invention discloses a bit reversal (BF) decoder for a low-density parity check code under a binary symmetric channel, which is called an adaptive threshold BF decoder. Aiming at the problem that the clock frequency of the conventional BF decoder is limited by the global maximum value searching operation, the invention designs an adaptive threshold value to screen the bits needing to be overturned. By using the messages from the previous iteration, the threshold calculation can be performed in parallel with other decoding operations, thus greatly reducing the critical path. To further improve performance, the proposed decoder employs a non-uniform switching criterion. The invention also discloses a hardware architecture for implementing the proposed decoder and gives a comprehensive result. Design examples show that the disclosed decoder can achieve maximum throughput and best decoding performance compared to other BF decoders.

Description

Efficient bit flipping decoder based on adaptive threshold

Technical Field

The invention relates to decoder design in the technical field of communication coding, in particular to bit flipping decoder algorithm design and hardware implementation with high performance and high throughput rate under binary symmetric channels.

Background

Low density parity check codes (LDPC) have been extensively studied and used in many communication standards over the past for a long time due to the advantages of near shannon limit decoding performance and high parallelism. Among all decoding algorithms of the LDPC code, the belief propagation algorithm (BP) exhibits the best performance, but has relatively high decoding complexity, which is not favorable for hardware implementation. In order to reduce the complexity of the BP algorithm, a minimum sum algorithm (MS) and a modified minimum sum algorithm (OMS) are successively proposed, which can significantly reduce the decoding complexity with acceptable performance loss, and thus become an LDPC decoding algorithm which is widely used at present.

The bit flipping algorithm (BF) is less complex than the above algorithm, but its performance is poor. In order to improve the decoding performance of the BF algorithm, a number of improved algorithms have introduced soft messages to assist decoding, such as a gradient descent bit flipping algorithm (GDBF). However, the floating point operation greatly increases the overall complexity, and is not suitable for some application scenarios, such as NAND Flash Memory, in which soft messages are difficult to generate. Based on this, we limit the application scenario to Binary Symmetric Channels (BSCs), where only hard decision messages are available. At present, the decoding algorithms suitable for the channel mainly include three types, namely PGDBF, PPBF and TRGDBF. The TRGDBF performs best, and the other two algorithms perform comparably. However, the clock frequency of the PPBF is highest and the critical path is shortest. Therefore, there is a great deal of research space in designing BF decoders that satisfy both high performance and low latency requirements.

Disclosure of Invention

The purpose of the invention is as follows: the present invention is directed to solving the above problems by providing a high throughput, low latency bit flipping decoder. The specific invention content is as follows:

an adaptive threshold based high efficiency bit inverter (ATBF), comprising:

1) and (3) an efficient bit flipping decoding algorithm. The bits to be flipped are filtered based on an adaptive threshold, which is defined as the maximum energy value in the last iteration. By storing the energy value, the threshold value can be synchronously calculated when decoding is carried out, and the critical path is shortened. In order to ensure the accuracy of the calculated threshold, the energy value of the inverted bit needs to be inverted after each iteration, and then the energy value is stored in the memory for the threshold calculation of the next iteration. In addition, an uneven flipping criterion is incorporated. To highlight the importance of the checksum in the energy equation, bits with a probability p for the total checksum being greater than or equal to the threshold value₀Flip, remaining bitsBit with the medium energy value greater than or equal to the threshold value and probability p₁Flip, wherein 0 < p₁＜p₀Is less than 1. Through the operation, the algorithm improves the turnover probability of the bit with the second largest energy value on the premise of ensuring the turnover priority of the bit with the largest energy value, so that the decoding process can be more accurately matched, and the decoding performance is obviously improved;

2) an efficient decoder architecture for implementing the proposed algorithm. Mainly comprising the following units. The variable node unit is used for storing the current decoding code word and turning the current decoding code word; the check node unit is used for generating a check sum; and the energy value calculation unit is used for calculating the total checksum and the energy value of each bit. The resource consumption of the unit is reduced by adopting a mode of firstly calculating the total checksum and then calculating the energy value according to the total checksum in the proposed architecture; the indicating unit is used for judging whether the bit is overturned or not and updating the energy value of the overturned bit; an energy value store for storing energy values calculated in previous iterations; a maximum finder for generating a threshold; an early termination unit for judging whether the decoding is terminated; a random probability generator for generating a desired rollover probability value;

the decoder framework provided by the invention has the following beneficial effects:

first, the proposed ATBF exhibits significantly improved decoding performance compared to current BF decoders;

secondly, decoding delay is reduced, and higher throughput rate can be obtained;

based on the advantages, the performance of the decoder provided by the invention on the BSC channel is superior to that of the conventional BF decoder, and the problem that the BF decoder simultaneously meets high performance and high throughput rate is solved.

Drawings

FIG. 1 is a flow chart of the decoding algorithm of the present invention;

FIG. 2 is a schematic diagram of a top-level architecture of a proposed decoder;

FIG. 3 is a schematic diagram of some sub-modules of the decoder of the present invention;

FIG. 4 is a schematic diagram of a performance simulation of the decoder of the present invention;

fig. 5 is a schematic diagram of the integrated results of the decoder of the present invention.

Detailed Description

The decoder architecture proposed by the present invention will be further explained with reference to the accompanying drawings. It is specifically noted that the embodiments described with reference to the drawings are exemplary and intended to be illustrative of the invention and are not to be construed as limiting the invention.

FIG. 1 is a flow chart of the decoding algorithm of the present invention. The codeword length is denoted as N and the number of check equations is denoted as M. First, the value of the codeword y received from the channel is assigned to the decoded codeword c. Next, the checksum of all the check equations is calculated, as shown in the following formula. Wherein the symbols

Representing an exclusive OR operation, N_c(i) Is the set of variable nodes connected to the ith check node.

If all checksums are 0, judging that the decoding is successful and outputting the current decoding code word c, otherwise, continuing decoding. Next, a total checksum S for each variable node is calculated based on the check equation_kAnd energy value E_k. Wherein N is_v(k) Is the set of check nodes connected to the kth variable node.

In other bit-flipping decoding algorithms (GDBF, PGDBF, TRGDBF), the bit with the largest energy value is usually selected and flipped with a fixed probability. Therefore, after the energy values are calculated, a global maximum search operation needs to be performed on all the N energy values, and decoding delay is greatly increased. To solve the above problem, the proposed ATBF decoding uses the threshold TH to determine the bit to be flipped. TH is defined as the maximum energy value obtained in the last iteration cycle, so that other decoding operations can be carried out at the same timeAnd the critical path is shortened by parallel computing. To avoid excessive flipping, TH is assigned to the maximum value that can be achieved by the energy value, i.e. d, in the first iteration_v+1. Wherein d is_vThe representative column weight is the number of check nodes connected to a variable node. The second term of the check equation becomes more and more important than the first term as the errors in the codeword decrease. In order to highlight the importance of the checksum, the invention adopts a non-uniform flipping criterion to determine the bits to be flipped. Obtaining TH, S_kAnd E_kThen, for satisfying S_kMore than or equal to TH bit, and taking the bit with probability p₀Flip, remaining bits satisfy E_kProbability p of bit being more than or equal to TH₁Flip over of p₀＞p₁. In order to use the updated message in the threshold calculation, the energy value of the bit to be inverted is updated according to the following equation.

E_k＝d_v+1-E_k

When the maximum iteration number is reached, the decoding is terminated and the current decoding code word c is output.

Fig. 2 is a schematic diagram of the top-level architecture of the proposed decoder. First, a Variable Node Unit (VNU) initializes a decoded codeword c to a codeword y received from a channel. Next, the Check Node Unit (CNU) calculates a checksum of each check node. Thereafter, an energy value calculation unit (ECU) calculates an energy value and a total checksum of each bit, and outputs them to an Indication Unit (IU). While the above operation is performed, the Maximum Finder (Maximum Finder) reads out the energy value in the last iteration from the energy value memory (E-MEM) and calculates the threshold TH using it. The indicating unit determines whether each bit is flipped or not by using the above information in combination with a Random Probability value delivered from a Random Probability Generator (Random Probability Generator) and returns the determination result to the variable node unit. The bits determined to need to be flipped are flipped in the variable node unit. The indicating unit also needs to update the energy value of the bit which is determined to need to be inverted and input the energy value into the energy value storage. And finishing the operation and finishing one decoding iteration. An Early Stop Unit (Early Stop Unit) determines whether the correct codeword is obtained or whether the maximum number of iterations has been reached. The decoding is terminated when a termination condition is satisfied.

Fig. 3 is a schematic diagram of some sub-modules in the decoder according to the present invention. Fig. 3(a) is a schematic diagram of an energy value calculation unit. To reduce decoding delay, the total checksum S_kAnd energy value E_kAre shown in modified one-hot format. For example, for d_vCode words of 4, E_kFrom 4 bits E_k4E_k3E_k2E_k1Is represented by and E _ki1 when E_kI. Due to S_kIs E_kIn part, the invention calculates S first_kReuse of S_kAnd

calculation of E_kAs shown in fig. 3 (a). Therefore, the hardware consumption of a single energy value calculation unit can be reduced from 30 or gates to 8 or gates and 4 alternative MUXs. The threshold TH is also indicated in modified one-hot format. Fig. 3(b) is a schematic circuit diagram of a portion for updating an energy value in an indication unit. To avoid introducing complex digital format conversion and subtraction operations, the energy values are updated using fig. 3 (b). When I is_k1, namely the k bit needs to be flipped in the current iteration, and the energy value is updated to { -E_k1～E_k2～E_k3～E_k4Where sign-represents a bit negation operation. It can be shown that this method satisfies equation E_k＝d_v+1-E_k. When I is_k0, i.e. the k-th bit does not need to be flipped within the current iteration, its energy value is not updated, still { E }_k4E_k3E_k2E_k1}. This approach may only require the use of 4 alternative MUXs and inverters and is therefore very low in complexity.

Example (b): a codeword with a code length of 1296, a code rate of 1/2, a column weight of 3, and a row weight of 6 will be described as an example. Fig. 4 is a schematic diagram of a performance simulation of the decoder of the present invention. The maximum number of iterations for all BF algorithms is set to 300 and the maximum number of iterations for OMS algorithms is set to 20. It can be seen that the SABF disclosed in the present invention is more general than the currently optimized TRGDBF algorithmCan be raised by one order of magnitude while having a shorter critical path. When the maximum iteration number is increased to 1000, the performance of the SABF can be further improved by an order of magnitude to the decoding performance of the OMS algorithm. In addition, the proposed SABF decoder architecture is described by adopting Verilog language, the obtained RTL is synthesized by using Synopsys tool, and the adopted process is TSMC 90nm CMOS process. Fig. 5 is a schematic diagram of the integrated results of the decoder of the present invention. The combined results show that the SABF decoder reduces the decoding delay while providing the best performance. The frequency reaches 769MHz, which is increased by 76.8% compared with TRGDBF decoder. In addition, the SABF decoder may provide the highest throughput rate. For a more intuitive comparison, we also compare throughput-power consumption ratios. The throughput-power consumption ratio of the SABF is 546.4Mbps/mm²。

While the invention has been described with reference to specific preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An adaptive threshold based high efficiency bit flipper, characterized by:

1) screening bits to be turned over based on a self-adaptive threshold value, and shortening a key path of a decoder;

2) an uneven flip criterion for improving decoding performance;

3) an efficient decoder architecture for implementing the proposed decoder.

2. The adaptive threshold of claim 1, wherein:

1) the threshold is defined as the maximum energy value in the last iteration, and the threshold can be calculated in parallel when decoding is carried out by storing the energy value, so that the critical path is shortened;

2) in order to ensure the accuracy of the calculated threshold, the energy value of the flipped bit needs to be updated after each iteration and then stored in the memory for the threshold calculation in the next iteration.

3. The non-uniform rollover criterion as recited in claim 1, wherein bits having a total checksum greater than or equal to a threshold are assigned a probability p to emphasize the significance of the checksum in the energy equation₀Turning over, the bits with energy value larger than or equal to threshold in the rest bits are counted with probability p₁Flip, wherein 0 < p₁＜p₀＜1。

4. The efficient decoder architecture of claim 1, comprising the following units:

1) the variable node unit is used for storing the current decoding code word and turning the current decoding code word;

2) the check node unit is used for generating a check sum;

3) and the energy value calculation unit is used for calculating the total checksum and the energy value of each bit. The resource consumption of the unit is reduced by adopting a mode of calculating the total checksum firstly and then calculating the energy value according to the total checksum in the proposed architecture;

4) the indicating unit is used for judging whether the bit is overturned or not and updating the energy value of the overturned bit;

5) an energy value store for storing energy values calculated in previous iterations;

6) a maximum finder for generating a threshold;

7) an early termination unit for judging whether the decoding is terminated;

8) and a random probability generator for generating the required flip probability value.