Symmetrical capacitive coupling filter
Technical Field
The invention belongs to the technical field of filters.
Background
In recent years, with the rapid development of miniaturization of mobile communication, satellite communication and defense electronic systems, high performance, low cost and miniaturization have become the development direction of the microwave/radio frequency field at present, and higher requirements are made on the performance, size, reliability and cost of a microwave filter. In some defense-oriented devices, duplexers have become a key electronic component in the receive and transmit branches of this band, and the main indicators describing the performance of such components are: passband operating frequency range, stopband frequency range, isolation, passband insertion loss, stopband attenuation, passband input/output voltage standing wave ratio, insertion phase shift and delay frequency characteristics, temperature stability, volume, weight, reliability and the like.
The low-temperature co-fired ceramic is an electronic packaging technology, a multilayer ceramic technology is adopted, a passive element can be arranged in a medium substrate, and an active element can be attached to the surface of the substrate to form a passive/active integrated functional module. LTCC technology has shown numerous advantages in terms of cost, integrated packaging, wiring line width and spacing, low impedance metallization, design versatility and flexibility, and high frequency performance, and has become the dominant technology for passive integration. The microwave device has the advantages of high Q value, convenience for embedding a passive device, good heat dissipation, high reliability, high temperature resistance, shock resistance and the like, and by utilizing the LTCC technology, the microwave device which is small in size, high in precision, good in compactness and small in loss can be well processed.
Disclosure of Invention
The invention aims to provide a symmetrical capacitive coupling filter, which realizes a symmetrical capacitive coupling filter with a new structure, small volume, light weight, high reliability, excellent electrical property, simple structure, high yield, good batch consistency, low manufacturing cost and stable temperature performance, improves the out-of-band rejection degree, ensures the miniaturization of the filter, has larger separation distance of inductance and capacitance in the structure, reduces the process difficulty and improves the yield.
In order to achieve the purpose, the invention adopts the following technical scheme:
a symmetrical capacitive coupling filter comprises an input port P1, a first filtering unit, a capacitor CM, a second filtering unit and an output port P2, wherein the input port P1, the first filtering unit, the capacitor CM, the second filtering unit and the output port P2 are sequentially arranged at intervals from left to right;
the first filter unit comprises a strip line R1, an inductor L1, an inductor L2, an inductor L3, an inductor L4, a capacitor C1, a capacitor C2, a via V2 and a via V2, the first filter unit is divided into a first capacitor layer, a second capacitor layer, a third inductor layer and a fourth capacitor layer, the first capacitor layer, the second capacitor layer, the third inductor layer and the fourth capacitor layer are sequentially arranged at intervals from top to bottom, the capacitor C2 and the capacitor C2 are arranged on the first capacitor layer, the capacitor C2 and the capacitor C2 are arranged on the second capacitor layer, the capacitor C2, the inductor L8472, the inductor L2, the inductor L3, the inductor L4, the capacitor C2 and the fourth capacitor C2 are arranged on the capacitor C2;
a capacitor C1 is positioned above an inductor L1, a capacitor C1 is connected with an inductor L1 through a V1, an inductor L2 is positioned on the right side of an inductor L1, an inductor L1 is connected with an inductor L2, a capacitor C2 is positioned on the upper side of an inductor L2, a capacitor C3 is positioned on the upper side of a capacitor C2, a capacitor C2 is connected with an inductor L1 through a through hole V1, a capacitor C3 is connected with an inductor L2 through a through hole V7, strip lines R1 are arranged in front of the inductor L2 at intervals, strip lines R1 are arranged on the second capacitor layer, and the inductor L2 is connected with the strip lines R1 through a through hole V4;
an inductor L4 is arranged in front of the microstrip line R1, the inductor L4 is connected with the microstrip line R1 through a through hole V5, a capacitor C7 is positioned above the inductor L4, a capacitor C8 is positioned on the right side of the inductor L4, a capacitor C7 is connected with a capacitor C8 through a through hole V6, the inductor L4 is connected with a capacitor C7 through a through hole V6, and a capacitor CM is connected with a capacitor C8 through a through hole V6;
the capacitor C5 is positioned in front of the inductor L1, the capacitor C5 is connected with the inductor L1, and the capacitor C5 is also connected with the input port P1;
the inductor L3 is located in front of the capacitor C5, the inductor L3 is connected with the capacitor C5 through a through hole V2, the capacitor C4 is located above the inductor L3, the capacitor C6 is located above the capacitor C4, the capacitor C4 is connected with the inductor L3 through a through hole V2, and the capacitor C6 is connected with the inductor L3 through a through hole V3;
the second filter unit comprises a strip line R2, an inductor L5, an inductor L6, an inductor L7, an inductor L8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a via V8, a via V9, a via V10, a via V11, a via V12, a via V13 and a via V14, and is divided into a fifth capacitor layer, a sixth capacitor layer, a seventh inductor layer and an eighth capacitor layer, wherein the fifth capacitor layer and the first capacitor layer are on one level, the sixth capacitor layer and the second capacitor layer are on one level, the seventh inductor layer and the third inductor layer are on one level, and the eighth capacitor layer and the fourth capacitor layer are on one level;
a capacitor C9 and a capacitor C14 are arranged on the fifth capacitor layer, a strip line R2, a capacitor C10, a capacitor C11, a capacitor C13 and a capacitor C15 are arranged on the sixth capacitor layer, an inductor L5, an inductor L6, an inductor L7, an inductor L8 and a capacitor C12 are arranged on the seventh inductor layer, and a capacitor C16 is arranged on the eighth capacitor layer;
a capacitor C10 is arranged on the upper side of an inductor L5, a capacitor C9 is arranged on the upper side of a capacitor C10, the inductor L9 is connected with the capacitor C9 through a through hole V9, a strip line R9 is positioned on the lower side of the inductor L9, the strip line R9 is connected with the inductor L9 through a through hole V9, an inductor L9 is arranged on the lower side of the strip line R9, the inductor L9 is connected with the strip line R9 through a through hole V9, a capacitor C9 is arranged on the left side of the inductor L9, a capacitor C9 is arranged on the upper side of the inductor L9, the capacitor C9 is connected with the capacitor C9 through a through hole V9, the inductor L9 is connected with the capacitor C9;
inductor L6 is arranged on the right side of inductor L5, inductor L6 is connected with inductor L5, capacitor C11 is arranged on the upper side of inductor L6, capacitor C11 is connected with inductor L6 through via V14, capacitor C12 is arranged on the front side of inductor L6, capacitor C12 is connected with inductor L6, capacitor C12 is further connected with output port P2, inductor L8 is arranged on the lower side of capacitor C12, inductor L8 is connected with capacitor C12 through via V10, capacitor C14 is arranged on the upper side of inductor L8, capacitor C13 is arranged on the upper side of capacitor C14, capacitor C14 is connected with inductor L8 through via V13, and capacitor C13 is connected with inductor L8 through via V13.
The input port P2 and the output port P1 are both 50 ohm impedance ports of a coplanar waveguide structure.
The symmetrical capacitive coupling filter is manufactured by a multilayer low-temperature co-fired ceramic process.
The invention aims to provide a symmetrical capacitive coupling filter, which realizes a symmetrical capacitive coupling filter with a new structure, small volume, light weight, high reliability, excellent electrical performance, simple structure, high yield, good batch consistency, low manufacturing cost and stable temperature performance, improves the out-of-band rejection degree, ensures the miniaturization of the filter, has larger separation distance of an inductance and a capacitance in the structure, reduces the process difficulty, improves the yield and is suitable for occasions and corresponding systems with harsh requirements on volume, electrical performance, temperature stability and reliability, such as satellite communication and the like.
Drawings
FIG. 1 is a top plan view of the overall structure of the present invention;
fig. 2 is a schematic structural diagram of a first filtering unit according to the present invention.
Detailed Description
1-2, the symmetric capacitive coupling filter includes an input port P1, a first filter unit, a capacitor CM, a second filter unit, and an output port P2, where the input port P1, the first filter unit, the capacitor CM, the second filter unit, and the output port P2 are sequentially disposed at intervals from left to right;
the first filter unit comprises a strip line R1, an inductor L1, an inductor L2, an inductor L3, an inductor L4, a capacitor C1, a capacitor C2, a via V2 and a via V2, the first filter unit is divided into a first capacitor layer, a second capacitor layer, a third inductor layer and a fourth capacitor layer, the first capacitor layer, the second capacitor layer, the third inductor layer and the fourth capacitor layer are sequentially arranged at intervals from top to bottom, the capacitor C2 and the capacitor C2 are arranged on the first capacitor layer, the capacitor C2 and the capacitor C2 are arranged on the second capacitor layer, the capacitor C2, the inductor L8472, the inductor L2, the inductor L3, the inductor L4, the capacitor C2 and the fourth capacitor C2 are arranged on the capacitor C2;
a capacitor C1 is positioned above an inductor L1, a capacitor C1 is connected with an inductor L1 through a V1, an inductor L2 is positioned on the right side of an inductor L1, an inductor L1 is connected with an inductor L2, a capacitor C2 is positioned on the upper side of an inductor L2, a capacitor C3 is positioned on the upper side of a capacitor C2, a capacitor C2 is connected with an inductor L1 through a through hole V1, a capacitor C3 is connected with an inductor L2 through a through hole V7, strip lines R1 are arranged in front of the inductor L2 at intervals, strip lines R1 are arranged on the second capacitor layer, and the inductor L2 is connected with the strip lines R1 through a through hole V4;
an inductor L4 is arranged in front of the microstrip line R1, the inductor L4 is connected with the microstrip line R1 through a through hole V5, a capacitor C7 is positioned above the inductor L4, a capacitor C8 is positioned on the right side of the inductor L4, a capacitor C7 is connected with a capacitor C8 through a through hole V6, the inductor L4 is connected with a capacitor C7 through a through hole V6, and a capacitor CM is connected with a capacitor C8 through a through hole V6;
the capacitor C5 is positioned in front of the inductor L1, the capacitor C5 is connected with the inductor L1, and the capacitor C5 is also connected with the input port P1;
the inductor L3 is located in front of the capacitor C5, the inductor L3 is connected with the capacitor C5 through a through hole V2, the capacitor C4 is located above the inductor L3, the capacitor C6 is located above the capacitor C4, the capacitor C4 is connected with the inductor L3 through a through hole V2, and the capacitor C6 is connected with the inductor L3 through a through hole V3;
the second filter unit comprises a strip line R2, an inductor L5, an inductor L6, an inductor L7, an inductor L8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a via V8, a via V9, a via V10, a via V11, a via V12, a via V13 and a via V14, and is divided into a fifth capacitor layer, a sixth capacitor layer, a seventh inductor layer and an eighth capacitor layer, wherein the fifth capacitor layer and the first capacitor layer are on one level, the sixth capacitor layer and the second capacitor layer are on one level, the seventh inductor layer and the third inductor layer are on one level, and the eighth capacitor layer and the fourth capacitor layer are on one level;
a capacitor C9 and a capacitor C14 are arranged on the fifth capacitor layer, a strip line R2, a capacitor C10, a capacitor C11, a capacitor C13 and a capacitor C15 are arranged on the sixth capacitor layer, an inductor L5, an inductor L6, an inductor L7, an inductor L8 and a capacitor C12 are arranged on the seventh inductor layer, and a capacitor C16 is arranged on the eighth capacitor layer;
a capacitor C10 is arranged on the upper side of an inductor L5, a capacitor C9 is arranged on the upper side of a capacitor C10, the inductor L9 is connected with the capacitor C9 through a through hole V9, a strip line R9 is positioned on the lower side of the inductor L9, the strip line R9 is connected with the inductor L9 through a through hole V9, an inductor L9 is arranged on the lower side of the strip line R9, the inductor L9 is connected with the strip line R9 through a through hole V9, a capacitor C9 is arranged on the left side of the inductor L9, a capacitor C9 is arranged on the upper side of the inductor L9, the capacitor C9 is connected with the capacitor C9 through a through hole V9, the inductor L9 is connected with the capacitor C9;
inductor L6 is arranged on the right side of inductor L5, inductor L6 is connected with inductor L5, capacitor C11 is arranged on the upper side of inductor L6, capacitor C11 is connected with inductor L6 through via V14, capacitor C12 is arranged on the front side of inductor L6, capacitor C12 is connected with inductor L6, capacitor C12 is further connected with output port P2, inductor L8 is arranged on the lower side of capacitor C12, inductor L8 is connected with capacitor C12 through via V10, capacitor C14 is arranged on the upper side of inductor L8, capacitor C13 is arranged on the upper side of capacitor C14, capacitor C14 is connected with inductor L8 through via V13, and capacitor C13 is connected with inductor L8 through via V13.
The input port P2 and the output port P1 are both 50 ohm impedance ports of a coplanar waveguide structure.
The symmetrical capacitive coupling filter is manufactured by a multilayer low-temperature co-fired ceramic process.
During operation, a signal enters the filter from the input port P1, is filtered by the first filtering unit, is transmitted to the second filtering unit through the capacitor CM for filtering, and is filtered by the second filtering unit and then is output from the output port P2.
The invention aims to provide a symmetrical capacitive coupling filter, which realizes a symmetrical capacitive coupling filter with a new structure, small volume, light weight, high reliability, excellent electrical performance, simple structure, high yield, good batch consistency, low manufacturing cost and stable temperature performance, improves the out-of-band rejection degree, ensures the miniaturization of the filter, has larger separation distance of an inductance and a capacitance in the structure, reduces the process difficulty, improves the yield and is suitable for occasions and corresponding systems with harsh requirements on volume, electrical performance, temperature stability and reliability, such as satellite communication and the like.