CN106158750B - Semiconductor element and its manufacturing method - Google Patents
Semiconductor element and its manufacturing method Download PDFInfo
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- CN106158750B CN106158750B CN201510144098.2A CN201510144098A CN106158750B CN 106158750 B CN106158750 B CN 106158750B CN 201510144098 A CN201510144098 A CN 201510144098A CN 106158750 B CN106158750 B CN 106158750B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The invention discloses a kind of manufacturing methods of semiconductor element.In forming stack layer in substrate.Stack layer is patterned, to form the multiple stack architectures extended along a first direction, there is the channel extended along a first direction, each channel has multiple width portions and multiple narrow portions between two adjacent stack architectures.Wide portion is greater than narrow portion along the maximum width of second direction along the maximum width of second direction.Electric charge storage layer is formed, with the bottom surface in covering width portion and side wall and fills up narrow portion.Conductor layer is formed, to fill up wide portion.A kind of semiconductor element as made by the above method is separately provided.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacturing methods.
Background technique
It is integrated with semiconductor element, in order to reach high density and dynamical target, in manufacture semiconductor element
When part, tendency forms the structure of upward storehouse, more effectively to utilize wafer area.Therefore, there is high-aspect-ratio (high
Aspect ratio) semiconductor structure frequently appear in small-sized component.
Manufacture the above-mentioned semiconductor structure with high-aspect-ratio, it will usually multiple etching is carried out, to form different pattern
Material layer.However, causing alignment to be not easy due to size microminiaturization, etching technics is not easy figure after controlling or etching and generates shape
Become, even result in structural collapse, and the yield of semiconductor element technique may be influenced.Therefore, time of etching technics how is reduced
The phenomenon that figure generates deformation or structural collapse after number, and reduction etching is the project of current desired research.
Summary of the invention
The present invention provides a kind of manufacturing method of semiconductor element, can reduce the number of etching technics, and after reducing etching
Figure generates the phenomenon that deformation or structural collapse.
The present invention provides a kind of manufacturing method of semiconductor element comprising following steps.In forming stack layer in substrate.
Stack layer is patterned, to form the multiple stack architectures extended along a first direction, is had between two adjacent stack architectures
The channel extended along a first direction, each channel have multiple width portions for alternateing and multiple narrow portions, wherein wide portion along
The maximum width of second direction is greater than narrow portion along the maximum width of second direction.Electric charge storage layer is formed, to cover width portion
Bottom surface and side wall and fill up narrow portion.Conductor layer is formed, to fill up wide portion.
In one embodiment of this invention, above-mentioned width portion is narrow portion along second direction along the maximum width of second direction
2-5 times of maximum width.
In one embodiment of this invention, the shape in above-mentioned width portion include circle, ellipse, square, rectangle, diamond shape or
A combination thereof.
In one embodiment of this invention, above-mentioned electric charge storage layer is composite layer, and composite layer includes oxide skin(coating), nitride
Layer or combinations thereof.
In one embodiment of this invention, above-mentioned stack layer includes conductor layer, dielectric layer or combinations thereof.
In one embodiment of this invention, each width portion on above-mentioned channel second direction with it is every on adjacent channel
The arrangement mode in one width portion includes being arranged side by side, being alternately arranged or combinations thereof.
The present invention provides a kind of semiconductor element again, semiconductor element include substrate, stack architecture, electric charge storage layer and
Conductor layer.Above-mentioned stack architecture has the ditch extended along a first direction in substrate between two adjacent stack architectures
Road, each channel has the multiple width portions alternateed and multiple narrow portions, wherein wide portion is big along the maximum width of second direction
In narrow portion along the maximum width of second direction.Electric charge storage layer covers bottom surface and the side wall in width portion and fills up narrow portion.Conductor
Layer, fills up wide portion.
In one embodiment of this invention, above-mentioned width portion is narrow portion along second direction along the maximum width of second direction
2-5 times of maximum width.
In one embodiment of this invention, the shape in above-mentioned width portion include circle, ellipse, square, rectangle, diamond shape or
A combination thereof.
In one embodiment of this invention, above-mentioned electric charge storage layer is composite layer, and composite layer includes oxide skin(coating), nitride
Layer or combinations thereof.
In one embodiment of this invention, above-mentioned stack architecture includes conductor layer, dielectric layer or combinations thereof.
In one embodiment of this invention, each width portion on above-mentioned channel second direction with it is every on adjacent channel
The arrangement mode of one narrow portion includes being arranged side by side, being alternately arranged or combinations thereof.
Based on above-mentioned, the present invention passes through the channel for forming wide portion and narrow portion with different in width, subsequent in channel with benefit
When middle formation electric charge storage layer, while wide portion forms electric charge storage layer, being formed by electric charge storage layer in narrow portion can be directly
As insulating layer, just it is not required to additionally carry out the technique to form insulating layer again later.The program of technique can be reduced whereby, and then is reduced
Figure generates the phenomenon that deformation or structural collapse after etching.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate institute's accompanying drawings
It is described in detail below.
Detailed description of the invention
Figure 1A to Fig. 1 E is the top view according to the manufacturing method of semiconductor element depicted in one embodiment of the invention.
Fig. 2A to Fig. 2 E shows for the section of the manufacturing method of semiconductor element depicted in the A-A ' line along Figure 1A to Fig. 1 E
It is intended to.
Fig. 3, Fig. 4 and Fig. 5 are the top view according to semiconductor element depicted in connection with several embodiments of the invention.
[symbol description]
10: substrate
11: stack layer
12: stack architecture
14: conductor layer
16: dielectric layer
18: hard mask layer
22: electric charge storage layer
23: groove
24: conductor layer
30: wide portion
40: narrow portion
100,200,300: semiconductor element
D1, D2, D3: direction
T: channel
W1, w2, w3, w4: width
T1: thickness
A-A ': line
Specific embodiment
Figure 1A to Fig. 1 E is according to the upper depending on showing of the manufacturing method of semiconductor element depicted in one embodiment of the invention
It is intended to.Fig. 2A to Fig. 2 E illustrates for the section of the manufacturing method of semiconductor element depicted in the A-A ' line along Figure 1A to Fig. 1 E
Figure.Fig. 3, Fig. 4 and Fig. 5 are the top view according to semiconductor element depicted in connection with several embodiments of the invention.
Referring to Figure 1A and Fig. 2A, first offer substrate 10.Substrate 10 may include semiconductor material, insulator material
Any combination of material, conductor material or above-mentioned material.The material of substrate 10 be, for example, be selected from by Si, Ge, SiGe, GaP,
The material or any suitable use that at least one of group substance is constituted composed by GaAs, SiC, SiGeC, InAs and InP
In the physical structure of present invention process.Substrate 10 includes single layer structure or multilayered structure.Furthermore, it is possible to use silicon on insulating layer
(silicon on insulator, SOI) substrate.Substrate 10 is, for example, silicon or germanium silicide.
Referring to Figure 1B and Fig. 2 B, in formation stack layer 11 in substrate 10.Stack layer 11 is, for example, to lead including multilayer
Body layer 14 and multilayer dielectric layer 16 are constituted.Stack layer 11 is, for example, with multilayer dielectric layer 16 with multi-layer conductive layer 14 with mutual
Alternate mode is constituted toward 10 top storehouse of substrate.In one embodiment, stack layer 11 is, for example, 8 layers, 16 layers, 32 layers or more
Layer stack is constituted, but invention is not limited thereto.The material of conductor layer 14 includes undoped semiconductor or doped half
The polysilicon of conductor, e.g. polysilicon or doping.The thickness of conductor layer 14 is, for example, between 200 angstroms to 600 angstroms.It leads
The forming method of body layer 14 includes chemical vapour deposition technique.In one embodiment, conductor layer 14 is, for example, as semiconductor element
100 bit line or wordline.The material of dielectric layer 16 includes that oxide, nitride, nitrogen oxides or dielectric constant are low less than 4
Dielectric constant material.The thickness of dielectric layer 16 is, for example, between 200 angstroms to 600 angstroms.The forming method of dielectric layer 16 is for example
It is thermal oxidation method or chemical vapour deposition technique.
Please continue to refer to Figure 1B and Fig. 2 B, further include to form hard mask layer 18 to 11 property of can choose of stack layer.Hard mask
Layer 18 is, for example, the top layer positioned at stack layer 11, but invention is not limited thereto.Hard mask layer 18 can be single-layer or multi-layer.Firmly
The material of mask layer 18 is, for example, silica, silicon nitride or other suitable materials.The method for forming hard mask layer 18 includes changing
Learn vapour deposition process or Metalorganic chemical vapor deposition method (MOCVD).
Referring to Fig. 1 C and Fig. 2 C, stack layer 11 is patterned, to form multiple heaps that D1 extends along a first direction
Stack architecture 12.The method for patterning stack layer 11 is, for example, photoetching and etching method.Etching method is, for example, dry etching method.Dry type is carved
Erosion method can be ise, reactive ion etching etc..There is D1 along a first direction between two neighboring stack architecture 12
The channel T of extension.Each channel T has alternate multiple wide portions 30 and multiple narrow portions 40 each other.From semiconductor element
The plane (plane that first direction D1 and second direction D2 are constituted) that 100 upward angle of visibility degree is seen, the shape in wide portion 30 can
To be rectangle (Fig. 1 E), round (Fig. 3), ellipse (Fig. 4, long axis D1 in a first direction；Fig. 5, long axis in second direction D2), just
Rectangular, diamond shape or combinations thereof；The shape of narrow portion 40 can be rectangle (Fig. 1 E, Fig. 3-4), square, ampuliform or combinations thereof.But this
Invention is not limited.From the point of view of the plane that second direction D2 and third direction D3 are constituted, the section in wide portion 30 and narrow portion 40
Shape can be arbitrary shape, e.g. V-type, U-shaped, diamond shape or combinations thereof.
Wide portion 30 is greater than narrow portion 40 along the maximum width w2 of second direction D2 along the maximum width w1 of second direction D2.
In one embodiment, wide portion 30 is maximum width of the narrow portion 40 along second direction D2 along the maximum width w1 of second direction D2
2-5 times of w2.In another embodiment, narrow portion 40 is formed after being less than or equal to along the maximum width w2 of second direction D2
Electric charge storage layer 22 along the thickness t1 of third direction D3 2 times (please referring to following Fig. 2 D).First direction D1 and second direction
D2 is different.Third direction D3 is different from first direction D1 and different with second direction D2.For example, first direction D1 and second
Direction D2 is substantially perpendicular；First direction D1 and third direction D3 are substantially perpendicular；Second direction D2 and third direction D3 essence
It is upper vertical.
In one embodiment, wide portion 30 is, for example, between 300 angstroms to 1500 angstroms along the maximum width w1 of second direction D2
Between, narrow portion 40 is, for example, between 150 angstroms to 450 angstroms along the maximum width w2 of second direction D2.
Fig. 1 E, Fig. 3 and Fig. 4 are please referred to, each wide portion 30 of channel T is in second direction D2 and adjacent another channel T
Each wide portion 30 arrangement mode be staggered.However, invention is not limited thereto.In another embodiment, channel T
Arrangement mode of each wide portion 30 in each wide portion 30 of second direction D2 and adjacent another channel T is also possible to arrange side by side
Column.
Referring to Fig. 1 D and Fig. 2 D, electric charge storage layer 22 is formed in channel T.Specifically, position is in the portion channel T wide
30 electric charge storage layer 22 only covers the bottom surface and side wall in wide portion 30, and the wide portion 30 of unfilled channel T；And position is in channel T
The electric charge storage layer 22 of narrow portion 40 then fills up channel T.That is, after forming electric charge storage layer in channel T, in channel T
Wide portion 30 can leave groove 23, and subsequent conductor layer of inserting is as wordline or bit line；And channel T narrow portion 40 is then because electric
Lotus storage layer 22 is filled up, and can not be further filled with conductor layer.Electric charge storage layer 22 is, for example, dielectric layer.Electric charge storage layer 22 can be
Composite layer, for example, electric charge storage layer 22 is e.g. constituted including oxide skin(coating), nitride layer or combinations thereof compound
Layer.More specifically, the material of electric charge storage layer 22 includes silicon nitride, silica or combinations thereof.In one embodiment, charge stores up
Depositing layer 22 is, for example, the composite layer being made of oxide layer/nitration case/oxide layer (Oxide/Nitride/Oxide, ONO).Electricity
Lotus storage layer 22 need to be greater than each narrow portion 40 along the maximum width w2 of second direction D2 along the thickness t1 of third direction D3
1/2 times or more, narrow portion 40 can be filled up when ensuring to be formed electric charge storage layer 22.Electric charge storage layer 22 along third direction D3 thickness
T1 is spent e.g. between 100 angstroms to 250 angstroms, but invention is not limited thereto.The forming method of electric charge storage layer 22 is for example
It is thermal oxidation method or chemical vapour deposition technique.
Referring to Fig. 1 D, Fig. 1 E, Fig. 2 D and Fig. 2 E, conductor layer 24 is formed, to fill up wide portion 30.Specifically, leading
Body layer 24 fills up groove 23.The material of conductor layer 24 is, for example, polysilicon, the polysilicon of doping, metal, metal alloy or its group
It closes.Metal is, for example, tungsten.Metal alloy is, for example, alusil alloy.The method for forming conductor layer 24 includes chemical vapour deposition technique.
In one embodiment, barrier layer first can be formed in the side wall in wide portion 30 and bottom before forming conductor layer 24.Barrier layer
Material be, for example, include titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.The thickness of barrier layer is, for example, between 10 angstroms to 200 angstroms
Between.The forming method of barrier layer is, for example, chemical vapour deposition technique.The invention is not limited thereto.In another embodiment, complete
Before holotype is at conductor layer 24, the electric charge storage layer 22 of the bottom in wide portion 30 is handled, to form 24 channel of conductor layer, but,
Invention is not limited thereto.Conductor layer 24 is, for example, the wordline or bit line as memory element.In one embodiment, conductor layer 24
It is the wordline (such as channel architecture) as memory element；The position of conductor layer 14 in stack architecture 12 as memory element
Line (such as gate structure).In another embodiment, conductor layer 24 is the bit line as memory element；In stack architecture 12
Conductor layer 14 as memory element wordline.The invention is not limited thereto.
In embodiments of the present invention, 40 maximum width w2 of channel T narrow portion is set as the electricity formed after being less than or equal to
2 times of 22 thickness t1 of lotus storage layer, allow electric charge storage layer 22 to fill up narrow portion 40；And conductor layer 24 can insert wide portion 30
Because of groove 23 left by unfilled electric charge storage layer 22.Therefore, it can directly be done positioned at the electric charge storage layer 22 of narrow portion 40
For insulating layer, completely cut off two neighboring conductor layer 24 on D1 along a first direction with electrical.And it is subsequent no longer need to carry out it is other exhausted
Edge layer technique.That is, can be stored simultaneously in the charge that wide portion 30 is formed by forming the single technique of electric charge storage layer 22
Layer 22, and insulating layer is formed in narrow portion 40.
On the other hand, there is alternate multiple wide portions 30 and multiple narrow portions 40 each other by each channel T, and
Arrangement mode of each wide portion 30 of each channel T in second direction D2 Yu each wide portion 30 of adjacent another channel T is to hand over
For arranging, being arranged side by side or combinations thereof, it can reach and compared with the stack architecture in known technology regardless of wide portion and narrow portion be not easy to collapse
Effect.Specifically, regardless of in the stack architecture of wide portion and narrow portion in known technology, between two adjacent channels stack architecture away from
From the distance between the wide portion for being all the present embodiment.The embodiment of the present invention can then pass through the side in above-mentioned width portion and narrow portion arrangement
Formula increases the distance of stack architecture between adjacent two channel, and then reduces the phenomenon that semiconductor structure collapses.
Fig. 1 E and Fig. 2 E is please referred to, the semiconductor element 100 of the embodiment of the present invention includes substrate 10, stack architecture 12, electricity
Lotus storage layer 22 and conductor layer 24.Stack architecture 12 is located in substrate 10 and it has channel T each other.Channel T along
First direction D1 extends, and has alternate multiple wide portions 30 and multiple narrow portions 40 each other.Electric charge storage layer 22, is filled in
Among channel T.Electric charge storage layer 22 among the wide portion 30 of channel T, unfilled wide portion 30 only cover bottom surface and side wall,
And there are grooves 23；Electric charge storage layer 22 among the narrow portion 40 of channel T, then fill up narrow portion 40.Conductor layer 24 is filled up recessed
Slot 23.Material and the manufacturing method of conductor layer 24 in this as described above, repeat no more.
The material of the insulating layer of semiconductor element 100 of the invention is identical as the material of electric charge storage layer 22.Specifically,
The electric charge storage layer 22 that semiconductor element 100 of the invention is located at narrow portion 40 can be used as subsequent insulating layer, positioned at wide portion 30
Electric charge storage layer 22 can be used as subsequent electric charge storage layer.In one embodiment, when narrow portion 40 is along the maximum of second direction D2
When width w2 is less than electric charge storage layer 22 along 2 times of the thickness t1 of third direction D3, then it is located at narrow portion 40 and is located at wide portion 30
The number of plies of electric charge storage layer 22 can not be identical.
Referring to Fig. 1 E, 3 and 4, in the above-described embodiment (Fig. 1 E), the shape in wide portion 30 is rectangular.At other
In embodiment, unlike the embodiments above is the shape in wide portion 30 for round (Fig. 3) or oval (Fig. 4 and Fig. 5), other knots
Structure, material, thickness and manufacturing method in this as described above, repeat no more.
The manufacturing method of the semiconductor element of the embodiment of the present invention can be applied to dynamic random access memory (DRAM), with
NOT gate flash memory (NAND flash), NOR type flash memory (NOR-flash) etc., but invention is not limited thereto.
In conclusion in the embodiment of the present invention to separate stack architecture channel have different in width wide portion with it is narrow
Portion, therefore be subsequently formed electric charge storage layer and the narrow portion of channel can be filled up electric charge storage layer, directly as insulating layer.Therefore,
It is subsequent to be not required to carry out other techniques for forming isolation structures again, the number of etching technics can be reduced whereby, and then after reduction etching
Figure generates the phenomenon that deformation or structural collapse, promotes the electrical performance and process yields of semiconductor element.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the invention
Protection scope subject to be defined depending on appended claims range.
Claims (12)
1. a kind of manufacturing method of semiconductor element, comprising:
In forming a stack layer in a substrate；
The stack layer is patterned, to form the multiple stack architectures extended along a first direction, two adjacent stack architectures
Between there is the channel that extends along a first direction, each channel with the multiple width portions and multiple narrow portions alternateed,
Wherein these wide portions are greater than these narrow portions along the maximum width of the second direction along the maximum width of a second direction, wherein
The first direction is perpendicular to the second direction, and the first direction and the second direction constitute the upward angle of visibility degree of the semiconductor element
The plane seen；
An electric charge storage layer is formed, to cover the bottom surface in these width portions and side wall and fill up these narrow portions；And
A conductor layer is formed, to fill up these width portions.
2. the manufacturing method of semiconductor element according to claim 1, wherein these width portions along the second direction most
Big width is these narrow portions along 2-5 times of the maximum width of the second direction.
3. the manufacturing method of semiconductor element according to claim 1, wherein the shape in these width portions includes round, oval
Shape, square, rectangle, diamond shape or combinations thereof.
4. the manufacturing method of semiconductor element according to claim 1, wherein the electric charge storage layer is a composite layer, this is multiple
Closing layer includes oxide skin(coating), nitride layer or combinations thereof.
5. the manufacturing method of semiconductor element according to claim 1, wherein the stack layer include conductor layer, dielectric layer or
A combination thereof.
6. the manufacturing method of semiconductor element according to claim 1, wherein each wide portion on each channel this
The arrangement mode in each width portion on two directions and adjacent each channel includes being arranged side by side, being alternately arranged or combinations thereof.
7. a kind of semiconductor element, comprising:
One substrate；
Multiple stack architectures are located in the substrate, have one extended along a first direction between two adjacent stack architectures
Channel, each channel have multiple width portions for alternateing and multiple narrow portions, wherein these wide portions along a second direction most
Big width is greater than these narrow portions along the maximum width of the second direction, and wherein the first direction is perpendicular to the second direction, and
The first direction and the second direction constitute the plane that the upward angle of visibility degree of the semiconductor element is seen；
One electric charge storage layer covers the bottom surface in these width portions and side wall and fills up these narrow portions；And
One conductor layer fills up these width portions.
8. semiconductor element according to claim 7, wherein these width portions are this along the maximum width of the second direction
A little narrow portions are along 2-5 times of maximum width of the second direction.
9. semiconductor element according to claim 7, wherein the shape in these width portions include round, ellipse, square,
Rectangle, diamond shape or combinations thereof.
10. semiconductor element according to claim 7, wherein the electric charge storage layer is a composite layer, which includes
Oxide skin(coating), nitride layer or combinations thereof.
11. semiconductor element according to claim 7, wherein these stack architectures include conductor layer, dielectric layer or its group
It closes.
12. semiconductor element according to claim 7, wherein each width portion on these channels is in the second direction and phase
The arrangement mode of each narrow portion on these adjacent channels includes being arranged side by side, being alternately arranged or combinations thereof.
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| CN112017951B (en) * | 2020-08-07 | 2022-03-04 | 福建省晋华集成电路有限公司 | Method for forming pattern layout |
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| CN103137645A (en) * | 2011-11-25 | 2013-06-05 | 三星电子株式会社 | Semiconductor memory device having three-dimensionally arranged resistive memory cells |
| CN103928467A (en) * | 2013-01-11 | 2014-07-16 | 三星电子株式会社 | Three-dimensional semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103137645A (en) * | 2011-11-25 | 2013-06-05 | 三星电子株式会社 | Semiconductor memory device having three-dimensionally arranged resistive memory cells |
| CN103928467A (en) * | 2013-01-11 | 2014-07-16 | 三星电子株式会社 | Three-dimensional semiconductor device |
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